JPH01103757A - Device for transferring data - Google Patents

Abstract

PURPOSE:To attain the transferring of high accuracy by providing a storing means to store one of command data and address data to be transferred at least and a storing means to store data main body, switching either of those storing means and executing an input. CONSTITUTION:Based on a lock signal CK, with which the command data and the address data are inputted from an arithmetic and control device 21 as transmitting data D1, the data are transferred to a command register 27 and an address register 28 and latched. Simultaneously with this operation, a changing-over switch 33 is changed-over to a data register 32 side by a data latch control part 34. Next, a transferring control signal the inverse of TE goes to be a low level and the data main body, which is stored to an address to be stored in the register 28, is transferred to a signal processor 22. A device 21 outputs a clock signal CK and transfers the data main body to the data register 32. When latch operation is finished, the switch 33 is changed-over to the side of the registers 27 and 28 again.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a data transfer device suitably implemented in, for example, in-vehicle electronic equipment.

Prior Art FIG. 4 is a block diagram showing the configuration of the prior art. Fourth
The configuration of the prior art will be described with reference to the drawings. This conventional example includes an arithmetic control bag W1 such as a microcomputer, and a digital signal processing device (DSP, hereinafter abbreviated as signal processing device) 2. The arithmetic control device 1 includes a transmission buffer register 3 and a reception buffer register 4. These buffer registers 3.4 are
Connected to transmit register 5 and receive register 6.

The signal processing device 2 stores an address register 7 in which command data and address data of the transmission data D1 transferred from the transmission register 5 of the arithmetic control device 1 are stored, and main body data included in the transmission data D1. A data register 8 is included. The register 7.8 is used for reception, and the command data in the received transmission data Dl is decoded by the cycle still control section, and various processes are executed within the signal processing device 2.

The signal processing device 2 is equipped with a data register 10 for transmission. This data register 10 and the data register 8 described above are connected to a data bus 11. Further, the address register 7 and the data register 8 are supplied with a latch control signal LC from the arithmetic and control unit 1.

FIG. 5 shows the signal processing device 2 of the arithmetic and control device 1 of this conventional example.
6 is a timing chart illustrating the operation of writing data to the signal processing device 2. FIG. 6 is a timing chart illustrating the operation of reading data from the signal processing device 2. The operation of this conventional example will be described with reference to these drawings. At time t1 in FIG.
The chip select signal C3 for selecting the signal processing device 2 is set to low level, and the signal processing device 2 is selected. Next, the transfer control signal TE shown in FIG. 5 is generated from the signal processing device 2, and data transfer with the arithmetic and control device 1 becomes possible.

Subsequently, the clock signal CK is supplied from the arithmetic and control device 1 to the signal processing device 2, and from time t2 shown in FIG. 5(3),
The transmission data D1 starts to be transferred to the signal processing device 2. Here is the symbol ■ in Figure 5 (3).

■, . . . , ■ indicate the order assigned to the transfer unit of data, each of which is transferred by a predetermined number of bits. When the transfer of the transmission data D1 is started, the arithmetic and control unit 1 switches the latch control signal LC to low level, and the transmission data D1 is stored in the address register 7 and the data register 8. In this way, the data writing process is completed.

Here, after time t3 when the transfer of the data ■ to ■ is completed and the latch control signal LC becomes high level, there is a period T until the timing when the level of the transfer control signal TE is switched again.
3 is an internal processing period in which the transmission data D1 received by the register 7.8 is written to various storage means provided in the signal processing device 2 via the data bus 11 or the like.

Next, when performing a process of reading data from the signal processing device 2, the arithmetic and control device 1 switches the chip select signal C9 to a low level at time t4 in FIG.
), the transfer control signal TE is generated. Among these, as shown in FIG. 6(3), a command for a read operation to the signal processing device 2 and data such as an address where data to be read are stored in the signal processing device 2 are sent.

Here, as explained in FIG. 4, the transmitter register is composed of two blocks of address registers 7 and three blocks of data registers 8, where one block is one byte. Therefore, in the case of the write operation shown in FIG. 5, data (1) and (2) are combined data of command data and address data, and data (2) to (2) are data transferred in the data transfer to be transferred. The data format in which these data are composed of five blocks is fixed to this conventional example.

Therefore, as shown in FIG. 6, for a read operation, only read command data and address data are required. Therefore, data (1) and (2) are a combination of these data, and data (2) to (2) use dummy data for formatting. After transferring the write command to the signal processing device, the transfer control signal TE is generated again at time t5, and the sixth
As shown in FIG. 4, the corresponding data ■a, ■a, ■a, ■a are read out from the signal processing device 2, and
will be forwarded to. In this way, the read operation is completed.

FIG. 7 is a timing chart illustrating the time required for various operations in this conventional example. Referring also to FIG. 7, in the data write operation shown in FIG. 7 (1), in the example shown in FIG. 7, the time required to write a single piece of data is 745μ.
It becomes s. Further, the read operation using dummy data described with reference to FIG. 6 also requires a similar amount of time.

The operations shown in FIG. 7(1) and FIG. 7(2) are for the case where the format of the transferred data and hence the data length is fixed.In the case of a variable length method in which the format is changed according to the amount of data to be transferred, As shown in FIG. 7 (3), it takes 325 μs.

Problems to be Solved by the Invention In the prior art as described above, unnecessary dummy data ■ to ■ are used to realize data transfer between the arithmetic and control device 1 and the signal processing device 2, which reduces the transfer speed. However, as shown in FIG. 4, the transfer efficiency deteriorates, and since the receiving register 7.8 and the transmitting register 10 are separately provided, the structure becomes large. there were.

SUMMARY OF THE INVENTION An object of the present invention is to provide a data transfer device that can solve the above-mentioned problems, shorten the transfer time of transferred data, and simplify the configuration.

Means for Solving the Problems The present invention is a data transfer device that transfers serial data to and from a control device, and stores at least one of command data and address data transferred from the control device. a first storage means; a second storage means for storing the main body of data to be transferred between the control device; and a second storage means for storing each of the above-mentioned data transferred from the control device in either the first storage means or the second storage means. A data transfer device is characterized in that it includes a switching means for switching and inputting data.

In a preferred embodiment, the second storage means is a write/reader that selectively stores the data body received from the control device and the data body sent to the control device, and the switching means is configured to store the data body sent to the control device. It is characterized in that the clock signal input from the control device is switched to either the first storage means or the second storage means and outputted according to the ON/OFF signal input from the device.

Operation According to the present invention, data is transferred between the control device and the data transfer device. At least one of the command data and address data transferred from the control device at this time is stored in the first storage device based on a clock signal input from the control device via the switching device. When the command data and address data have been transferred from the control device and the subsequent data body is to be transferred, the switching means is switched to the second storage means and the data body is stored. In this way, data writing processing is realized.

On the other hand, when reading data from the data transfer device to the control device, only at least one of command data and address data is transferred from the control device. These data are stored in the first storage means, and the data transfer device reads out the retained contents based on the address data and transfers them to the second storage means.
Once stored in the storage means, the switching means switches the clock signal from the control device to the second storage means, thus achieving a read operation.

Embodiment FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. This embodiment will be described with reference to FIG. In this embodiment, one arithmetic and control device 21 is constructed including an arithmetic and control device 21 realized by, for example, a microcomputer, and a digital signal processing device (DSP, hereinafter abbreviated as signal processing device) 22. includes a transmission buffer register 23 and a reception buffer register 24, and these buffer registers 23 and 24 are connected to an address bus and a data bus included in the arithmetic and control unit 21,
Data is accessed. A transmission register 25 and a reception register 26 are connected to these buffer registers 23 and 24.

The signal processing device 22 includes, for example, a 4-bit command register 27 and a 12-bit address register 28.
Transmission data D1 is input from the transmission register 25 of. Further, the contents of this command register 27 are analyzed by two command decoders, and corresponding operations are performed within the signal processing device 22. On the other hand, the registers 27 and 28 are read by the cycle still control unit 30, and send and receive address data to and from the address bus 31 between the timings of various calculation processes.

Further, the signal processing device 22 stores, for example, a data main body to be transferred included in the transmission data D1.
A 4-bit data register 32 is provided. It is an object of this embodiment that the data register 32 can be used for both transmission and reception to the arithmetic and control unit 21. The registers 27 and 28 and the data register 32 receive a clock signal CK generated from the arithmetic control unit W21.
are switched and input via a changeover switch 33, which is a changeover means, as will be described later.

Further, a latch control signal LC output from the arithmetic and control device 21 as described later is input to a data latch control section 34 provided in the signal processing device 22, and correspondingly, the data latch control section 34 controls the changeover switch 33. switching mode and registers 27, 28. '32 data latch operations are controlled respectively. The contents of the data register 32 are written to and read from a memory 36, which is implemented, for example, by a random access memory, by means of address data supplied to the address bus 31 via a data bus 35.

FIG. 2 is a timing chart illustrating a write operation performed in the configuration example shown in FIG.

The write operation of this embodiment will be explained with reference to FIG. At time t1 in FIG. 2, the arithmetic and control unit 21:
The chip select signal C8 is switched to low level as shown in FIG. 2(1), and the signal processing device 22 is selected. The signal processing device 22 switches the transfer control signal TE to low level to enable data transmission between the arithmetic and control device 21 and the signal processing device 22. At this time, the data latch control section 34 is also reset, and the changeover switch 33 is thereby switched to the register 27, 28 side.

Thereafter, as shown in FIG. 2 (4), command data meaning a write command and address data indicating the write destination of the data body are inputted from the arithmetic and control unit 21 as transmission data D1 using a clock signal CK. is transferred to the command register 27 and address register 28 based on. When the transfer starts, the latch control signal LC is set to the second
As shown in Figure (3), set to low level. Furthermore, at time t2 when this transfer is completed, the latch control signal LC is set to high level as shown in FIG. 2 (3). At this timing, the command data and address data are latched into the command register 27 and address register 28. At the same time, the changeover switch 33 is switched to the data register 32 side by the data latch control section. Next, as shown in FIG. 2(2), the transfer control signal TE becomes high level, and the transfer is prohibited.

Next, at time t3, the transfer control signal TE becomes low level, and the transfer becomes possible again, and as shown in FIG. 2 (4), the main body of data to be stored at the address stored in the address register 28 is The data is transferred to the device 22.

The arithmetic control unit 21 outputs a clock signal CK and transfers the data body to the data register 32. At the same time, the latch control signal LC is set to low level. When this latch operation is completed, the latch control signal LC is set to high level, and the changeover switch 33 is switched to the register 27, 28 side again.

Subsequently, the transfer control signal TE becomes high level, and the transfer is prohibited. After this, the chip select signal C8 becomes high level, and the write operation ends.

FIG. 3 is a timing chart illustrating the process of reading data from the signal processing device 22 by the arithmetic and control unit 21 in the configuration example shown in the first figure.

The reading process will be explained with reference to FIG. 3 as well. When attempting to perform a read process in this configuration example, first, as shown in FIG. 3(1), the chip select signal C8 is set to low level at time t5, and the signal processing device 22 is selected. Next, the transfer control signal TE becomes low level, and data transfer between the arithmetic control device 21 and the signal processing device 22 becomes possible. From the arithmetic and control unit 21, the information shown in Fig. 3 (
4) Command data indicating a read command as shown in 4);
Address data indicating the address of, for example, the memory 36 of the signal processing device 22 in which data to be read is stored is transferred to the signal processing device 22. At the same time, the latch control signal LC is set to low level.

At this time, as in the case of FIG. 2, the chip select signal C
Since the latch control signal is reset by the rise of 8, the selector switch 33 is switched to the register 27, 28 side. In this way, the command data and address data which are the transmission data D1 are written into the command register 27 and the address register 28. This register 2
The contents of 7 and 28 are latched into the command register 27 and address register 28 at the timing when the latch control signal LC becomes high level at time 6 in FIG. At this time, the changeover switch 33 is switched to the register 32 side.

Next, the contents of the latched address are decoded by the cycle still control unit 30, and data at the corresponding address is read out from, for example, a memory 36 provided in the signal processing device 22.
The data is stored in the data register 32. At time t7 after such storage is performed, the transfer control signal TE becomes low level.

From now on, as shown in FIG. 3 (5), the arithmetic and control unit 21
Data register 32 based on clock signal CK from
The data stored in is read out and stored as received data D2 of the arithmetic and control unit 21.

When the data transmission is completed in this way, the latch control signal LC becomes high level as in the case of FIG. 2, and then the transfer control signal TE and chip select signal C8 each become high level, and the read process ends.

In the above write process and read process, if the data written after time t3 in FIG. 2 is, for example, 24 bits, the time required for this write operation is approximately 753 μs, as in the conventional example. calculated by someone.

On the other hand, when reading data from the signal processing device 22,
As explained with reference to FIG. 3, the address of the data to be read is transferred, and it has been confirmed that the required time is approximately 753 μs in this case as well, as in the conventional example.

As described above, with the configuration example shown in FIG. 1, the present embodiment can achieve the same operation as the configuration described in the prior art. At this time, in this embodiment, the data register 32 is used for both reception and transmission, and it has been confirmed that this allows the transfer-related configuration to be reduced by about 30% compared to the conventional technique shown in FIG. . Furthermore, since the data length to be transferred may be, for example, 40 bits (5 bytes) for both read and write processing, it has been confirmed that the transfer time can be reduced by approximately 36% during data read operations compared to the conventional technology. There is.

Here, an example has been shown in which the input light of each data outputted from the control device is switched by switching the tarok given to the first and second storage means, but the data transfer path to the first and second storage means is It may also be possible to switch itself.

However, in this case, the configuration must be configured to import the data immediately after a specified number of data are input, which has the disadvantage of complicating the hardware configuration and stipulating the timing for data import. arise.

Further, although this example shows an example of synchronous communication synchronized with an external clock, it is also applicable to asynchronous communication (start-stop synchronous communication) using an internally generated clock, etc.

Effects As described above, according to the present invention, highly efficient data transfer is possible with a simple configuration.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, FIG. 2 is a timing chart for explaining the write operation of this configuration example, and FIG. 3 is a timing chart for explaining the read operation of this embodiment. , FIG. 4 is a block diagram showing a typical configuration example of the prior art, FIG. 5 is a timing chart explaining a write operation in the prior art, FIG. 6 is a timing chart explaining a read operation in the prior art, and FIG. The figure is a timing chart illustrating the time required for a write operation/read operation in the prior art. 21... Arithmetic control device, 22... Signal processing device, 2
7... Command register, 28... Address register, 29... Command decoder, 30... Cycle still control unit, 33... Changeover switch, 34...
Data latch control section, 36...memory, C8...chip select signal, LC...latch control signal, TE...
・Transfer control signal agent Patent attorney Keiichi Kazuzu

Claims (3)

[Claims] (1) A data transfer device that transfers serial data to and from a control device, the device comprising: a first storage means for storing at least one of command data and address data transferred from the control device; and a control device. a second storage means for storing the main body of data to be transferred between the controllers; and a switching means for switching and inputting the respective data transferred from the control device to either the first storage means or the second storage means. A data transfer device comprising: (2) The second storage means is a writing/reading device that selectively stores the data body received from the control device and the data body transmitted to the control device. Data transfer device as described in section. (3) The switching means switches the clock signal input from the control device to either the first storage means or the second storage means and outputs the clock signal according to the latch signal input from the control device. A data transfer device according to claim 1.