JP3459542B2 - Serial data transfer device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a serial data transfer device for serially transferring data in synchronism with a clock, and particularly for reducing the transfer time when the same instruction is simultaneously applied to a plurality of controlled circuits. The present invention relates to a serial data transfer device.

[0002]

2. Description of the Related Art A TV receiver or a VTR for home use may have a plurality of ICs therein, and the plurality of ICs may be controlled by a single controller (microcomputer). There are serial and parallel control methods, but the serial method is often used because the number of lines is small. In the serial method, a start signal, a slave address signal, transfer data, a stop signal, and the like are created using a combination of “H” and “L” logical values of data and a clock, and one cycle is configured including the plurality of signals. It uses a repetitive signal. Various information is added to the transfer data.

FIG. 2 shows data and clocks of such a serial type serial data transfer device. Figure 2 (a)
Shows data and FIG. 2 (b) shows a clock. Time t1 indicates a start point and time t2 indicates a stop point. In the meantime, necessary transfer data exists. The start point is when the data changes from "H" to "L" when the clock is "H". The stop point is when the data changes from "L" to "H" when the clock is "H". Then, at the falling edge of the clock (for example, t3)
Data is read by reading the value of the data.

When one transfer data is completed, a stop signal is generated to signal the end of data transfer. Then, the next start signal arrives and the next transfer data is sent.

[0005]

However, the serial method has a problem that it takes time to send instructions to a plurality of ICs simultaneously because it is serial. For example, in a home VTR, it is necessary to simultaneously switch a plurality of ICs (for example, a main YC signal processing IC, a head amplifier IC, an OSD IC) to a reproduction mode or a recording mode. In that case, if the mode change information is sent serially, a plurality of ICs cannot be operated at the same timing.

At present, mode switching is officially performed after mode switching is completed in all ICs.

[0007]

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and is a serial data transfer device for serially transferring data in synchronization with a clock, the start signal utilizing the data and the clock. A controller for generating a repeat signal of a slave address signal, transfer data and a stop signal, a temporary memory for temporarily storing the transfer data, a memory for storing the transfer data from the temporary memory, and a CHG command signal. CH to detect
A plurality of controlled circuits including a G detection circuit, and after serially transferring the same instruction to each temporary memory of the plurality of controlled circuits using the transfer data, A CHG command signal using data and a clock is transferred between the start signal and the start signal, and the transfer data is simultaneously fetched from the temporary memories of the plurality of controlled circuits to the memories.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a serial data transfer apparatus according to the present invention, in which (1) repeats a start signal, a slave address signal, a sub address signal, transfer data and a stop signal using data and a clock. A controller for generating a signal, (2) a temporary memory A and a temporary memory B for temporarily storing the transfer data, a memory A ′ and a memory B ′ for storing the transfer data from the temporary memory, and a CHG command A controlled circuit including a CHG detection circuit (3) for detecting a signal, and (4) is a controlled circuit having an internal configuration similar to that of the controlled circuit (2).

FIG. 3 shows the structure of serial data generated by the controller (1). It is composed of a start, a slave address, a sub address, transfer data, and a stop. After that, the same repetition is repeated from the start of the next serial data. The master memory (5) of FIG. 1 temporarily stores the serial data of FIG. At the same time, the start is applied to the start / stop detection circuit (6).

The serial data shown in FIG. 3 is similarly applied to the controlled circuit (4). When the start / stop detection circuit (6) detects the start, the gate (7) is opened. When the gate (7) is opened, serial data is applied to the slave address detection circuit (8) and the slave address is decoded. The slave address indicates the address of the controlled circuit that receives the transfer data.

When it is detected that the decoded slave address belongs to the controlled circuit (2), the switch (9) is closed. When the switch (9) is closed, the serial data is further applied to the sub address detection circuit (10). The sub address indicates the address of the memory A or B that receives the transfer data. For example, if the sub-address specifies the memory A as the memory for receiving the transfer data, the switch (11) is closed and the switch (1
2) opens. As a result, the transfer data is temporarily stored in the memory A. Then, the information from the memory A is transferred to the terminal (13).
Can be obtained.

Here, the relationship between the data generated from the controller (1) and the clock (indicated by one line in FIG. 1 but actually two lines of data and clock) is shown in FIG.
Shown in. The start signal defines that when the clock has the first logical value "H", the data changes from the first logical value "H" to the second logical value "L", and the stop signal has the first clock value "H". Is defined to change from the second logical value "L" to the first logical value "H". Then, the data output at the time of the falling of the data in FIG. 4B is taken in by the controlled circuit side.

In the serial data transfer of FIG. 4, FIG.
Is operated when the clock signal of "H" or "H" falls from "H" to "L", and is not used when the clock signal is "L". Therefore, the time when the data changes from "H" to "L" when the clock signal is "L" and becomes "H" again is defined as a CHG instruction. Then, immediately before this command, for example, a recording command is stored in the temporary memory of each controlled circuit. After that, the CHG command is applied to each controlled circuit. Transfer data (recording command) in the temporary memory of each controlled circuit is transmitted to each memory all at once, and a plurality of ICs (for example, main YC signal processing I
The recording command is transmitted to C, head amplifier IC, OSD IC). Therefore, there is no time loss due to the waiting time peculiar to the serial.

That is, before the CHG command shown in FIG. 4, a recording command (may be immediately before) is put in the memory B, for example. Similarly, a recording command is stored in the memory inside the controlled circuit (4). After that, the CHG instruction of FIG. 4 is generated. CH
Generation of the G instruction is detected by the CHG detection circuit (3) and the switch (14) corresponding to the memory B is closed. Then, the recording command of the memory B is transferred to the memory B ′.

The same operation is performed in the controlled circuit (4). Therefore, in serial data transfer, it is possible to transfer the same command to a plurality of ICs in a short time. FIG. 5 is a specific circuit example of the CHG detection circuit (3). The rising detection circuit (20), the falling detection circuit (21), the D-type flip-flops (22) and (23), and the inverter (24).

The clock signal shown in FIG. 6A is applied to the D-type flip-flops (22) and (23). Figure 6 (b)
The rising edge and the falling edge of the data signal are detected by the rising edge detection circuit (20) and the falling edge detection circuit (21) and are applied to the D-type flip-flops (22) and (23). As a result, D-type flip-flop (23)
The detection pulse of FIG. 6C can be obtained from the Q output of FIG.

[0017]

As described above, according to the present invention, in a serial data transfer device that transfers data serially in synchronization with a clock, the transfer time can be reduced when the same instruction is applied to a plurality of controlled circuits at the same time. Can be shortened. In particular, according to the present invention, after the same instruction is serially transferred to each temporary memory of a plurality of controlled circuits by using transfer data, data and clock are provided between the stop signal and the start signal of the repeat signal. Since the used CHG command signal is transferred and the transfer data is simultaneously taken into each memory from each temporary memory of the plurality of controlled circuits, the transfer time can be shortened.

[Brief description of drawings]

FIG. 1 is a block diagram showing a serial data transfer device of the present invention.

FIG. 2 is a waveform diagram for explaining conventional serial data transfer.

FIG. 3 is a structural diagram of serial data.

FIG. 4 is a waveform diagram for explaining serial data transfer of the present invention.

FIG. 5 is a specific circuit example of a CHG detection circuit (3).

FIG. 6 is a waveform diagram for explaining the operation of FIG.

[Explanation of symbols]

(1) Controller (2) Controlled circuit (3) CHG detection circuit (4) Controlled circuit (A) Memory (B) Memory (A ') Memory (B ') memory

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Claims (2)

(57) [Claims] 1. A serial data transfer device for serially transferring data in synchronism with a clock, and a controller for creating a repeat signal of a start signal, a slave address signal, transfer data and a stop signal using the data and the clock. A temporary memory for temporarily storing the transfer data, a memory for storing the transfer data from the temporary memory, C
A plurality of controlled circuits including a CHG detection circuit for detecting an HG command signal, and after the same instruction is serially transferred to each temporary memory of the plurality of controlled circuits using the transfer data, A CHG command signal using data and a clock is transferred between the stop signal and the start signal of the repetitive signal, and the transfer data is simultaneously taken into each memory from each temporary memory of the plurality of controlled circuits. Characteristic serial data transfer device. 2. The start signal defines that the data changes from the first logic value to the second logic value when the clock has the first logic value, and the stop signal has the first clock value.
, The data changes from the second logic value to the first logic value, and the CHG command signal specifies that the data changes when the clock has the second logic value. The serial data transfer device according to claim 1, wherein the serial data transfer device is a serial data transfer device.