JP3354493B2 - Serial data transfer device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a serial data transfer device for serially transferring data in synchronization with a clock. And a serial data transfer device.

[0002]

2. Description of the Related Art In some cases, a TV receiver or a home VTR has a plurality of ICs inside, and the plurality of ICs are controlled by a single controller (microcomputer). There are serial and parallel control methods, but the serial method is often used because the number of lines is small. In the serial method, a start signal, a slave address signal, transfer data, a stop signal, and the like are created by using a combination of logical values of “H” and “L” of data and a clock, and one cycle includes the plurality of signals. To use repetitive signals. Various information is added to the transfer data. FIG. 2 shows data and a clock of such a serial data transfer device of the serial system. FIG. 2A shows the data in FIG.
(B) shows a clock. Time t1 indicates a start point, and time t2 indicates a stop point. During this time, necessary transfer data exists.

[0003] A start point is when data changes from "H" to "L" when the clock is "H". The stop point is when the data is "L" when the clock is "H".
It is time to change from "H" to "H". Then, by reading the value of the data at the falling edge of the clock (for example, t3), the data is taken in.

When one transfer data ends, a stop signal is generated to notify the end of the data transfer. Then, when the next start signal arrives, the next transfer data is sent.

[0005]

However, the serial method has a problem that it takes a long time to send an instruction to a plurality of ICs at the same time because the instruction is serial.

For example, in a home VTR, a plurality of ICs (for example, a main YC signal processing IC, a head amplifier IC,
Although there is an equalizer IC), the instructions are executed after all the instructions arriving at each IC arrive. However, in such a case, since the timing of the latest one is used as the overall reference, the transfer takes a long time as a result.

[0007]

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and is directed to a serial data transfer device for serially transferring data, comprising: an input terminal to which serial data is applied; A first memory for temporarily storing serial data from the first memory, a first memory for storing data from the first temporary memory, and a second memory for temporarily storing serial data from the input terminal. And a second memory for storing data from the second temporary memory, and a first memory for generating a first control signal indicating that serial data from the input terminal is being transferred.
A transfer state detecting circuit, a second transfer state detecting circuit for generating a second control signal indicating that serial data from the input terminal is being transferred, and the first transfer state detecting circuit when a transfer command arrives. When it is determined that the control signal has not arrived, the data from the first temporary memory is transferred to the first memory, and when the transfer command arrives, the second control signal has not arrived. That the second
And a control circuit for transferring data from the temporary memory to the second memory.
And data is transferred to the second memory and the second memory.

Further, the present invention has been made in view of the above points, and is a serial data transfer device for transferring data serially, comprising: an input terminal to which serial data is applied; and a serial data from the input terminal. A first temporary memory for temporarily storing data, a first memory for storing data from the first temporary memory, and a second temporary memory for temporarily storing serial data from the input terminal. A second memory for storing data from the second temporary memory, and a first transfer state detection circuit for generating a first control signal indicating that serial data from the input terminal is being transferred. A second transfer state detection circuit for generating a second control signal indicating that serial data from the input terminal is in the middle of transfer, and a control signal according to a change in state of a transfer pulse indicating a transfer instruction. And a system control circuit for generating a detection pulse corresponding to a change in the state of the transfer pulse, and that the first control signal has not arrived during the generation of the control pulse from the system control circuit. A first latch determination circuit that determines whether the second control signal has not arrived during the generation of the control pulse from the system control circuit; and a first latch determination circuit that determines that the second control signal has not arrived. A first switch that passes or blocks the detection pulse according to a determination output signal of the determination circuit; and a second switch that passes or blocks the detection pulse according to a determination output signal of the second latch determination circuit. The data from the first temporary memory is transferred to the first memory and the data from the second temporary memory is transferred to the second memory. , Data in the second memory and said first memory in response to the transfer pulse is characterized in that to be forwarded.

[0009]

FIG. 1 shows a serial data transfer apparatus according to the present invention, wherein 1 is an input terminal to which serial data is applied, and 2 is a memory for temporarily storing serial data from the input terminal 1. A first temporary memory 3 for storing data from the first temporary memory 2; a second temporary memory 4 for temporarily storing serial data from the input terminal 1; Is a second memory for storing data from the second temporary memory 4, and 6 is a first control signal A1 indicating that serial data from the input terminal 1 is being transferred, and a transfer of the serial data. A first transfer state detection circuit for generating a second control signal B1 indicating that the serial data from the input terminal 1 is being transferred, and a third control signal A2 indicating that serial data from the input terminal 1 is being transferred.
A second transfer state detection circuit for generating a fourth control signal B2 indicating that the transfer of the serial data has been completed;

When the transfer command from the terminal 9 arrives, the controller 8 determines that the first and third control signals A1 and A2 have not arrived, and transfers the data from the first temporary memory 2 to the terminal. A control circuit for transferring the data from the second temporary memory 4 to the first memory 3 and for transferring the data from the second temporary memory 4 to the second memory 5, a switch 10 that opens and closes in response to an output signal of the control circuit 8, and a control circuit 11 A switch that opens and closes in response to an output signal of the circuit 8, 12 is an equalizer IC used for recording and reproducing video signals of a home VTR, and 13 is a YC signal processing used for recording and reproducing video signals of a home VTR. IC.

In the apparatus shown in FIG. 1, the mode of the equalizer IC of the home VTR and the mode of the YC signal processing IC are switched according to the Cyril data. The serial data in that case has a form as shown in FIG.

That is, the data D2 includes the YC signal processing I
The C information is included in the data D1, and the equalizer IC information is included in the data D1.

The serial data shown in FIG. 3A is applied to the input terminal 1 shown in FIG. The serial data is serially stored in the first temporary memory 2 and the second temporary memory 4. The serial data is transmitted to the first transfer state detecting circuit 6.
Is applied to the second transfer state detection circuit 7. The first transfer state detection circuit 6 decodes the serial data and outputs a pulse A1 indicating that the data D1 is being transferred (FIG. 3B).
To the first temporary memory 2. Then, the first temporary memory 2 starts storing the serial data from the input terminal 1.

The first transfer state detecting circuit 6 decodes the serial data and applies a pulse B1 indicating that the data transfer is completed to the first temporary memory 2. Then, the first temporary memory 2 stops storing the serial data from the input terminal 1.

The second transfer state detecting circuit 7 performs the same operation, and applies the pulse A2 shown in FIG. 3 (c) to the second temporary memory 4. Then, the second temporary memory 4 stores the input terminal 1
To start storing the serial data from. Further, the second transfer state detection circuit 7 decodes the serial data and applies a pulse B2 indicating that the data transfer is completed to the second temporary memory 4. Then, the second temporary memory 4 stops the operation of storing the serial data from the input terminal 1.

The first transfer state detection circuit 6 and the second transfer state detection circuit 7 decode incoming serial data and can determine to which block the contents are transferred. Therefore, when data D1 arrives,
The first temporary memory 2 operates so that the data is transmitted to the equalizer IC 12, and when the data D2 arrives,
In order for the data to be transmitted to the YC signal processing IC 13,
The temporary memory 4 operates.

In this way, the data D1 and D2 transferred serially are stored in the first temporary memory 2 and the second temporary memory 2.
Is temporarily stored in the temporary memory 4.

It is assumed that a transfer command arrives at the terminal 9 from this state. This transfer command is for transferring data from the temporary memory to the original memory (the first memory 3 and the like).

This transfer instruction is composed of data D1 and data D
2 is asynchronous in timing. Therefore, a transfer command is issued while the serially transferred data D1 and data D2 are being written to the first temporary memory 2 and the second temporary memory 4.

First temporary memory 2 and second temporary memory 4
If data is transferred while data is being written to the data, data information will be lost.

Therefore, in the present invention, when a transfer command is received by the control circuit 8, it is confirmed that the data transfer period is not in progress, and then the transfer is performed from the temporary memory to the original memory (for example, the first memory 3). are doing.

More specifically, the transfer command shown in FIG. 3F is applied to the control circuit 8, and the transfer command shown in FIG.
The pulse of (h) is created. During the "H" level period of the pulse of FIG. 3H, the pulse A1 of FIG.
Is at the “H” level.

FIG. 4 shows a specific example of the control circuit 8 shown in FIG. The transfer pulse of FIG. 3F is applied to the terminal 20 of FIG. The system control circuit 21 generates a control pulse shown in FIG. 3 (h) and a detection pulse shown in FIG. 3 (g) according to the transfer pulse. This detection pulse is transmitted or cut off when the first and second switches 22 and 23 open and close. When the detection pulse is transmitted, the memory contents are transferred. Switching between opening and closing of the first and second switches 22 and 23 is performed by a first and second latch determination circuit 24.
25. The first latch determination circuit 24 determines whether the pulse A1 in FIG. 3B is at the “H” level or the “L” level while the control pulse in FIG. 3H is at the “H” level. . The second latch determination circuit 25 outputs the pulse A2 in FIG. 3C during the period when the control pulse in FIG.
Is "H" level or "L" level.

Now, assuming that the pulse of FIG. 3 (h) is in the “H” level period T1, the pulse A1 in that period is “H”.
Cannot transfer because it is level. Therefore, a control signal for opening the switch 22 is generated from the first latch determination circuit 24. Then, the detection pulse is not transmitted. Also, during the same period T1, the pulse A2 is at the "L" level, so that it can be transferred. Therefore, a control signal for closing the switch 23 is generated from the second latch determination circuit 25. Then, FIG.
The pulse of (j) is transmitted. For this reason, the switch 10 opens according to the control signal from the control circuit 8, and the switch 1
1 closes. If the switch 10 is open as shown, there is no transfer from the temporary memory to the original memory (for example, the first memory 3). At this time, the data immediately before the data D2 is transferred to the second memory 5.

Next, when a transfer command at the next timing of FIG. 3 (f) is applied to the control circuit 8, the pulse (period T2) of FIG. 3 (h) and the corresponding pulse of FIG. The detection pulse of (g) is created. In the "H" level period of the pulse (period T2) in FIG.
The pulse A1 in FIG. 3B and the pulse A2 in FIG.
It detects whether it is a level or not.

In this case, the pulse A1 in FIG. 3B is at the "L" level, and the pulse A2 in FIG. 3C is at the "H" level. Therefore, the first switch 22 is closed and the second switch 23 is opened by the latch determination circuit. for that reason,
3 (i) and 3 (j) are generated from the control circuit 8, and the switch 10 is closed and the switch 11 is opened according to the control signal.

Next, when a transfer command at the next timing in FIG. 3F is applied to the control circuit 8, the pulse (period T3) in FIG. The detection pulse of (g) is created. In the "H" level period of the pulse (period T3) in FIG.
The pulse A1 in FIG. 3B and the pulse A2 in FIG.
It detects whether it is a level or not.

In this case, since both the pulse A1 in FIG. 3B and the pulse A2 in FIG. 3C are at the "L" level, it is clear that the transfer is not in progress. For this reason, the first and second switches 22 and 23 are closed by the latch discriminating circuit, and the control signals of FIGS. close. When the switches 10 and 11 are closed, the stored data is transferred from the temporary memory to the original memory (for example, the first memory 3).

Therefore, the first memory 3 and the second memory 5
Will be transferred.

[0030]

As described above, according to the present invention, the transfer time can be reduced when an instruction is simultaneously applied to a plurality of controlled circuits.

In particular, according to the present invention, during the data transfer to the temporary memory, the data is not transferred to the original memory, so that the data can be transferred reliably.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a serial data transfer device of the present invention.

FIG. 2 is a waveform diagram for explaining a conventional serial data transfer.

FIG. 3 is a waveform chart for explaining serial data transfer according to the present invention;

FIG. 4 is a specific circuit diagram of a control circuit 8 of the present invention.

[Explanation of symbols]

 (1) Input terminal (2) First temporary memory (3) First memory (4) Second temporary memory (5) Second memory (6) First transfer state detection circuit (7) Second Transfer state detection circuit (8) Control circuit

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04L 13/08 G06F 13/38 350

Claims (2)

(57) [Claims] 1. A serial data transfer device for serially transferring data, comprising: an input terminal to which serial data is applied; a first temporary memory for temporarily storing serial data from the input terminal; A first memory for storing data from a first temporary memory; a second temporary memory for temporarily storing serial data from the input terminal; and a second memory for storing data from the second temporary memory. 2, a first transfer state detection circuit that generates a first control signal indicating that serial data from the input terminal is being transferred, and that the serial data from the input terminal is being transferred. A second transfer state detecting circuit for generating a second control signal indicating that the first temporary control signal has not arrived when a transfer command has arrived. And transferring the data from the second temporary memory to the first memory by determining that the second control signal has not arrived when a transfer command arrives. And a control circuit for transferring data to the second memory, wherein data is transferred to the first memory and the second memory in accordance with the transfer command. 2. A serial data transfer device for serially transferring data, comprising: an input terminal to which serial data is applied; a first temporary memory for temporarily storing serial data from the input terminal; A first memory for storing data from a first temporary memory; a second temporary memory for temporarily storing serial data from the input terminal; and a second memory for storing data from the second temporary memory. 2, a first transfer state detection circuit that generates a first control signal indicating that serial data from the input terminal is being transferred, and that the serial data from the input terminal is being transferred. A second transfer state detection circuit for generating a second control signal indicating a transfer command; A system control circuit that generates a detection pulse according to a state change; a first latch determination circuit that determines that the first control signal has not arrived during the generation of the control pulse from the system control circuit; A second latch discriminating circuit for discriminating that the second control signal has not arrived during the generation of the control pulse from the system control circuit, and a discriminating output signal of the first latch discriminating circuit. A first switch that passes or blocks the detection pulse; and a second switch that passes or blocks the detection pulse in accordance with a determination output signal of the second latch determination circuit. Is transferred to the first memory, and data from the second temporary memory is transferred to the second memory. The first memory is transferred in response to the transfer pulse. Serial data transfer apparatus Mori data in the second memory and is characterized in that to be forwarded.