JP2783794B2 - Asynchronous input interface method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to, for example, a control unit (microcomputer) for controlling a video tape recorder (hereinafter referred to as VTR) and a signal processing unit or function switching unit provided inside the VTR. The present invention relates to an asynchronous input interface method useful for an interface section of a control signal.

[0002]

2. Description of the Related Art For example, when the control of a video signal processing unit is performed based on a control signal of a microcomputer to change the state of a screen or the like, it is preferable that the control contents be switched simultaneously during a vertical synchronizing signal period. For example, if some control signals are output during the previous screen and the remaining control signals are output during the next screen, the image may appear as an unnatural image on the screen. In order to solve this, it is conceivable to forcibly synchronize the microcomputer itself with the vertical synchronizing signal and output the control signal during the vertical synchronizing signal period. Occurs.

[0003]

As described above, when an attempt is made to control a video signal processing unit or the like with a control signal from a microcomputer, an unnatural control state appears on the screen unless control signals are sent all at once. May be. If the microcomputer is forcibly synchronized with the vertical synchronizing signal, the load on the microcomputer increases.

An object of the present invention is to provide an asynchronous input interface method capable of reliably receiving and transmitting a control signal when an external device such as a microcomputer receives a control signal asynchronously.

[0005]

In order to achieve the above object, the present invention decodes a plurality of address signals input in a predetermined order and specifies each register corresponding to each address signal. When storing the data corresponding to each of the address signals in each of the specified registers, only during a period from when the first address signal in the order of each of the address signals is detected to when the last address signal is detected, The data to be transmitted is stored in the respective registers by permitting the storage of the data in the respective registers and prohibited during other periods, and the data stored in the respective registers is defined as the arrival of the respective address signals. It is designed to capture and output during an asynchronous synchronization signal period. By the above method, the control data to be sent is taken in stably,
And they can be output all at once.

[0006]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows an embodiment of the present invention. The address ADD from the control unit 21 indicates the location of the device to be controlled and is supplied to the decoder 22, and the control data COND is supplied to the latch circuit 24. The decoder 22 decodes the contents of the address and obtains a decoded output at a location corresponding to the address. This decoded output is supplied as a clock (latch pulse) to a latch circuit 24 via a gate circuit 23 that passes the decoded output under the conditions described later. Latch circuit 24
Are driven by the decode output to latch the control data from the control unit 21. Therefore, the address ADD and the control data COND are associated with each other, and the address indicates the control location of the controlled device and the control data indicates the control content. The contents of the latch circuit 24
5 to all the control units simultaneously. The output timing of the control data is, for example, a VTR blanking period.

The period until the control data of the latch circuit 24 is stored is asynchronous with the timing at which the control data is output from the latch circuit 25. As described above, the reason why the data fetch and transfer error does not occur even when asynchronous is provided is because the following configuration is further provided.

That is, when a synchronization signal (vertical synchronization signal) is input to the input terminal 26, the release circuit 27
To allow the decoded output to pass. Next, when outputting the address, the control unit 21 sequentially outputs the address in a predetermined address period so as to designate all the control points of the controlled device. In response to the address output, control data at the designated location is also output. Therefore, during the vertical blanking period,
When the address output period of the control unit 21 exists, the decoded output is supplied to the latch circuit 24 via the gate circuit 23. Here, the output order of each address corresponding to each control point of the controlled device is predetermined.
The first address in the address output period is detected by the address period start detection circuit 28. When the address period start detection circuit 28 detects the start of the address period, the address period end detection circuit 29 detects whether or not the last address (the last address of the address period) obtained from the gate circuit 23 has been decoded.

When the end of the address period is detected by the address period end detection circuit 29, the output thereof inhibits the gate circuit 23 from passing the decode output. Further, when the address period end detection circuit 29 detects the end of the address period, the latch pulse generation circuit 30 is enabled. The latch pulse generation circuit 30 detects the start of the address period by the previous address period start detection circuit 28,
When the end of the address period is detected by the address period end detection circuit 29, the enable state is set only. When a vertical synchronization signal is input from the terminal 26, a latch pulse is generated. The latch pulse is supplied to the latch circuit 24, whereby all of the control data stored in the latch circuit 24 is simultaneously output and supplied to each control point of the controlled device.

When the first vertical synchronizing signal of the video signal is input by the above configuration, the gate circuit 23 is released and a clock (decode output) is input to the latch circuit 24 so that control data can be taken in. The control data stored in 24 is control data output from the start to the end of the address period in any case. When the release circuit 27 releases the gate circuit 23, the address period end detection circuit 29 detects the start of the address period even if the third address in the address period is sent out and is not the first address. In this case, the control data at this time is not transferred from the latch circuit 24 to the latch circuit 25. The data held after the address is detected by the address period start detection circuit 28 is used. Moreover, the control data at this time is used only when the address is decoded continuously from the beginning to the end.

With the above-described apparatus, the control data output from the control unit 21 can be stably taken in even if the control unit 21 is completely asynchronous with the controlled device. FIG.
FIG. 3 and FIG. 4 are signal waveforms of various parts of the circuit of FIG. 2, and the same reference numerals as in FIG. 2 correspond to the signal waveforms in FIG. This shows where the waveform can be obtained. FIG. 4 shows a continuation of FIG.

In an actual circuit, a canceling circuit 27, an address period start detecting circuit 28, an address period end detecting circuit 29, and the like include a pulse generating circuit 31, as shown in FIG.
It comprises a flip-flop FF1, a NAND circuit NAND, a flip-flop FF2, a NOR circuit NOR, and the like.
The pulse generating circuit 31 uses the system clock (k), the vertical part ranking pulse (b), and the horizontal part ranking (a) to generate timing pulses (c), (d), (e),
(F) is generated. The flip-flop FF1 is reset by the timing pulse (d), and enters a state of waiting for detection of an address start. The gate control signal (g) for controlling the gate circuit 23 is supplied with the timing pulse (c) to the NOR circuit NOR, so that the gate circuit 23 is controlled to be able to pass the decode output from the decoder 22. The gate circuit 23 has the address AD
AND circuits AND1 corresponding to respective outputs of AD1 to AD11
AND11 and a transfer unit TR1 for transferring the outputs of the AND circuits AND1 to AND11 in synchronization with the system clock
To TR11.

Assuming that there is a decode output corresponding to the address AD1, the transfer unit TR1 transfers the decode output to the register R1 of the latch circuit 24 as a clock and supplies the address period start detection signal (1) to the flip-flop FF1. I do. As a result, the flip-flop F
F1 is set, and the NAND circuit NAD enters a standby state for detecting the last address (the last address in the address period). Addresses are sequentially sent (in this embodiment, it is assumed that there are 11 control items). When there is a decode output of the last address, an output is obtained from the AND circuit AND11, and the transfer unit TR11 Supplies the decoded output as a clock for the register R11 of the latch circuit 24. At the same time, an address period end detection signal (m) is obtained and supplied to the NAND circuit NAND. As a result, the flip-flop FF2 is set, the gate control signal (g) is inverted by the output (r), and the signal passage in the gate circuit 23 is inhibited.

In this state, the next timing pulse (f)
Is obtained, since the signal (r) is at the high level, the latch pulse generating circuit 30 can be driven by the system clock (k) to generate the latch pulse (s). Therefore, all control data stored in the registers R1 to R11 of the latch circuit 24 during the address period are simultaneously transferred to the registers R01 to R011 of the latch circuit 25. FIG. 3 shows a state (0) in which the control data (n) is latched by the latch circuit 24 and a state (t) in which the control data (n) is transferred to the latch circuit 25 and output.

In the above embodiment, the controlled device is a VTR
However, it is needless to say that the present invention is not limited to this and can be applied to any device that handles video signals.

[0016]

As described above, according to the present invention,
When a control signal is asynchronously received from an external device such as a microcomputer, it is possible to provide an asynchronous input interface method capable of reliably receiving and transmitting the control signal.

[Brief description of the drawings]

FIG. 1 is a diagram showing an embodiment of the present invention.

FIG. 2 is a diagram showing a specific circuit of the block diagram of FIG. 1;

FIG. 3 is a diagram shown for explaining the operation of the circuit in FIG. 2;

FIG. 4 is a diagram shown for explaining the operation of the circuit of FIG. 2;

[Explanation of symbols]

21: control unit, 22: decoder, 23: gate circuit, 2
4, 25: latch circuit, 27: release circuit, 28: address period start detection circuit, 29: address period end detection circuit, 30: latch pulse generation circuit

Continuation of front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G11B 20/10

Claims (1)

(57) [Claims] A plurality of address signals input in a predetermined order are decoded, a register corresponding to each address signal is specified, and data corresponding to each address signal is stored in each specified register. When storing, the data is allowed to be stored in each register only during a period from the detection of the first address signal in the order of the address signals to the detection of the last address signal, and the other periods are By prohibiting, the data to be transmitted is stored in each of the registers, and the data stored in each of the registers is fetched and output during a synchronous signal period asynchronous with the arrival of each of the address signals. Asynchronous input interface method.