JPH07249021A - Microcomputer system - Google Patents

Abstract

PURPOSE:To input the data to a CPU by detecting a data change on a data bus. CONSTITUTION:This microcomputer system consists of the CPU 1 which processes data and controls respective parts, a memory control part 2 which receives a memory access instruction from the CPU 1 and generates and outputs necessary address data and a control instruction, a memory 3 which outputs stored data to the data bus 4 on the basis of the address data and control data supplied from the memory control part 2, and a data detection part 5 which is connected to the data bus 4 and detects a signal change on the data bus 4 and outputs a detection signal 7 or 17.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer system capable of fetching data from a data bus at high speed with a small number of wait states when a CPU (central processing unit) reads data from an external memory.

[0002]

2. Description of the Related Art A CPU in a conventional microcomputer system
When the CPU reads data from the external memory, as shown in the time chart of FIG. 3 and the block diagram of FIG.
1 is a memory read command to the memory control unit 2, for example,
A machine language or the like corresponding to "READ XXX" is given, and the memory control unit 2 supplies required address data and control signals to the memory 3 and a wait signal to the CPU 1. After a lapse of a predetermined access time t1, the data read from the memory 3 is output to the data bus 4 to be fixed. Conventionally, when designing a system, based on the access time data from the specifications of the memory device to be used (the performance is guaranteed even in the worst case in consideration of product variations), further, for example, the condition of the load condition of the data bus 4. In consideration of the above, the number of wait states is determined in consideration of some margin time, and after the time corresponding to the number of wait states has elapsed, the memory control unit 2 sets the CP
The wait release signal was supplied to U1.

Therefore, in an actual microcomputer system, the data read from the memory 3 is stored in the data bus 4 before the time corresponding to the number of wait states elapses.
However, even in that case, the CPU 1 operates to fetch the read data for the first time after an unnecessary waiting time has elapsed.

However, in the microcomputer system, there is a strong demand for cost reduction as well as a demand for high-speed system processing. Therefore, in many cases, the microcomputer system is constructed using an inexpensive memory element having a slow access time,
It was difficult to realize high-speed system processing.

[0005]

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and provides a microcomputer system in which the CPU can take in the data immediately when the data read from the memory is confirmed by the data bus. The purpose is to provide.

[0006]

In order to achieve the above object, a CPU for processing data and controlling each unit, and the CP
In a microcomputer system including a memory that outputs stored data to a data bus based on address data supplied by U and a control command, the microcomputer system is connected to the data bus,
A data detection unit for detecting a signal change of the data bus is provided, and the CPU fetches data from the data bus at the timing when the detection signal output from the data detection unit is received.

[0007]

With the above configuration, the data detection section detects a change in the data on the data bus, and the CPU inputs a detection signal based on the change and takes in the data on the data bus. When the data detection unit does not detect the data change of the data bus, the CPU releases the wait after the preset number of wait states and fetches the data of the data bus.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A microcomputer system according to the present invention will be described in detail below with reference to the drawings. FIG. 1 is a block diagram of an embodiment of a microcomputer system according to the present invention. The same parts as those in the conventional example are denoted by the same reference numerals, and a part of the description is omitted. C processes data and controls each part.
It is PU. A memory control unit 2 receives a memory access command from the CPU 1 and generates and outputs required address data and a control command. Reference numeral 3 is a memory for outputting the stored data to the data bus 4 based on the address data and the control command supplied by the memory control unit 2. A data detector 5 is connected to the data bus 4, detects a signal change of the data bus 4, and outputs a detection signal 7 or 17.

The operation of the microcomputer system according to the present invention will be described with reference to FIG. When the CPU 1 gives a memory access command, for example, a machine language equivalent to “READ XXX” to the memory control unit 2, the memory control unit 2 causes the memory 3 to receive address data specifying, for example, address m. , A read control signal and a wait time (t) based on the number of wait states stored in advance.
During 2), a wait signal is supplied to the CPU1. The data detection unit 5 checks the data on the data bus 4 and outputs the detection signal 7 or 17 to the memory control unit 2 at the time when the data change occurs (t1 time after designation of the address m). The memory control unit 2 uses the detection signal 7 or 17
Based on the above, a wait release signal is supplied to the CPU 1,
The PU 1 takes in the data of which the data bus 4 has been determined, within the wait time (t2). The contents of the address m and the address n are the same, for example, both contents are F
In the case of F (H) or the like, the data detection unit 5 cannot detect a change in the data on the data bus 4. Therefore, the memory control unit 2 sends a wait release signal after the wait time (t2) elapses in the same manner as the conventional method. Supply to.

A specific configuration of the data detection section of the microcomputer system according to the present invention will be described with reference to FIG. Reference numeral 10 is a latch circuit for temporarily storing the data on the data bus 4 based on the clock signal 13 for detection. Reference numeral 11 compares the current data on the data bus 4 with the data one clock before output from the latch circuit 10 based on the clock signal 13 for detection, and when a change in data occurs, the first detection signal 11 It is a comparator that outputs 7. The detection clock signal 13 is n times the system clock 15, for example,
It is also possible to select twice or so and to make the detection time interval finer as Δt (FIG. 3). Further, in order to synchronize the first detection signal 7 output from the comparator 11 with the system clock 15, for example, a synchronization unit 12 using a latch circuit that operates in synchronization with the system clock 15 is provided, and the first detection signal 7 is provided. May be synchronized with the system clock 15 and the second detection signal 17 obtained as a result may be output.

[0011]

As described above, the present invention provides a microcomputer system in which the CPU fetches the data immediately after the data read from the memory has been fixed on the data bus. Therefore, in the conventional microcomputer system, there is a strong demand for cost reduction as well as system processing speed increase. Therefore, a microcomputer system is often constructed using an inexpensive memory with a slow access time. It has the merit of solving problems that were difficult to realize.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of a microcomputer system according to the present invention.

FIG. 2 is a block diagram showing a specific configuration of a data detection unit of the microcomputer system according to the present invention.

FIG. 3 is a time chart showing the operation of the microcomputer system.

FIG. 4 is a block diagram of an embodiment of a conventional microcomputer system.

[Explanation of symbols]

 1 CPU 2 Memory Control Section 3 Memory 4 Data Bus 5 Data Detection Section 7 First Detection Signal 10 Latch Circuit 11 Comparator 12 Synchronization Section 13 Clock Signal for Detection 15 System Clock 17 Second Detection Signal

Claims (4)

[Claims] 1. A CPU for processing data and controlling each unit
And a memory for outputting the data stored on the basis of the address data supplied by the CPU and the control command to the data bus, the microcomputer system being connected to the data bus to detect a signal change of the data bus. A microcomputer system comprising a data detector, wherein the CPU fetches data from a data bus at the timing of receiving a detection signal output from the data detector. 2. A CPU for processing data and controlling each part
And a memory control unit that receives a memory access command from the CPU and generates required address data and a control command,
In a microcomputer system including a memory that outputs stored data to the data bus based on address data supplied by the memory control unit and a control command, a signal change of the data bus is detected by connecting to the data bus. And a data detection section for performing data fetching from the data bus at the timing when the memory control section receives the detection signal output from the data detection section and the memory control section outputs the wait release signal. Microcomputer system featuring. 3. A latch circuit that connects the data detection unit to a data bus and temporarily stores data on the data bus based on a clock signal for detection, and data on the current data bus based on the clock signal for detection. And a data output from the latch circuit, and when a data change occurs, the comparator outputs a detection signal based on the occurrence of the data change. The described microcomputer system. 4. The clock signal for detection is selected to be several times as high as the system clock, and a synchronizing unit is provided for synchronizing the output of the comparator with the system clock. 2. Microcomputer system described in 2.