KR0168202B1 - Clock switching device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an I / O board controller of a microprocessor, and more particularly, to a clock switching device of a digital processor for controlling I / O devices having different access timings. A clock switching device of a digital processor for efficiently operating at a high speed suitable for a processing speed of an I / O device, the clock switching device comprising: an address generator for outputting an address to the predetermined I / O device to be accessed; An address detecting unit for detecting whether all levels of the bit lines of the address are high; A decoder unit for introducing and decoding the address signal; A delay unit for introducing a value of the decoder unit and delaying a time for a predetermined period during which an I / O device processes data; A gate unit for introducing a delay signal output from the delay unit, a decoder unit and an address signal to maintain an address signal for accessing the I / O device for a predetermined period; And a processor controller configured to control the I / O device at an appropriate speed by setting the I / O clock to a low level when the address detecting unit detects an address for accessing the I / O device. The clock switching device of the digital processor of the present invention can increase the efficiency of the system by optimally adjusting the I / O control clock according to the speed of the I / O device according to the processing speed of the accessed I / O devices.

Description

Clock switching device of digital processor

1 is a schematic block diagram of a clock switching device of a digital processor for explaining the present invention.

2 is a detailed block diagram of the block shown in FIG.

3 is a timing diagram when data write is performed in a clock switching device of a digital processor according to the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an I / O board controller of a microprocessor, and more particularly, to a clock switching device of a digital processor for controlling I / O devices having different access timings.

In the prior art, microprocessors used the same system clock to access memory or I / O devices. However, as the speed of microprocessors increased, the memory and I / O devices also required faster speeds.

In this case, since the RAM is always accessed from the microprocessor in the case of memory, the access speed of the RAM decisively affects the processing speed of the microprocessor, while in the case of display I / O devices, humans may not recognize it. Microprocessors often access slower I / O devices because they need to be as fast as they need, so there is no need to increase the I / O throughput as high as a microprocessor.

However, in order to control I / O devices while maintaining the high speed of the microprocessor, a method of controlling other slow I / O devices simultaneously is to control the clock using a phase locked loop (PLL). There is a problem that the duty should be 50%.

In addition, the technology disclosed in Intel Corporation U.S. Patent No. 5,247,636 requires the microprocessor to generate a slow / fast signal for each of the I / Os, and when using multiple slow devices, the system is designed to match the speed of the slowest device. There was a problem that the overall speed is reduced.

In the case of using the wait mode, the I / O was controlled all at once, and thus could not be a selective control.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and to provide a clock switching device of a digital processor that efficiently operates at a high speed for each of a plurality of I / Os having various processing speeds.

A clock switching device of a digital processor that efficiently operates a plurality of I / O devices connected to a microprocessor to achieve the above object at a high speed suitable for the processing speed of each I / O device. An address generator for outputting an address to the predetermined I / O device; An address detecting unit for detecting whether all levels of the bit lines of the address are high; A decoder unit for introducing and decoding the address signal; A delay unit for introducing a value of the decoder unit and delaying a time for a predetermined period during which an I / O device processes data; A gate unit for introducing a delay signal output from the delay unit, a decoder unit and an address signal to maintain an address signal for accessing the I / O device for a predetermined period; And a processor controller configured to control the I / O device at an appropriate speed by setting the I / O clock to a low level when the address detecting unit detects an address for accessing the I / O device.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1 is a schematic block diagram of a clock switching device of a digital processor for explaining the present invention.

The apparatus shown in FIG. 1 includes a microprocessor 110, a pull-up unit 120, an I / O unit 130 having a high processing speed, and an I / O unit 140 having a slow processing speed.

In FIG. 1, when accessing and writing the slow I / O unit is performed, the microprocessor 110 processes the data with a clock corresponding to the slow I / O unit 140 until the data processing is completed. Keep the address value.

FIG. 2 is a detailed block diagram of the block shown in FIG.

The apparatus shown in FIG. 2 includes a processor controller 200, an address buffer 212, an address detector 214, a data I / O unit 216, a pull-up unit 224, a decoder unit 226, and a delay unit. 228, a gate portion 230, and an I / O portion 236.

Referring to the operation of writing data from the microprocessor A according to the configuration of FIG. 2 to the I / O device B, the address generator 212 addresses address data for accessing the I / O device B. FIG. To bus 218.

At this time, the n address lines are pulled up by the pull-up unit 224 composed of pull-up resistors, and are maintained at the high level by the pull-up unit 224 when no address is applied to the address bus 218. Therefore, the address detecting unit 214 detects whether the levels of the address buses are all high, and if the high level is confirmed, the address detecting unit 214 notifies the processor control unit 200 that the address bus is not currently in use.

The decoder unit 226 in the I / O device transmits a low level signal to the noar gate 232 and the time control unit 228 of the gate unit 230 when the introduced address is an address corresponding to its own I / O device. Output

At this time, the time controller 228 maintains the low level for a predetermined period of time to extend the access period of the address of the fast microprocessor until the I / O device B completes writing data. ) The NOA gate 232 inputs the output signal of the decoder unit 226 and the time control unit 228 and predetermined line bits of the address bus 218 and outputs a high level to the gate of the NMOS transistor 234. do. The transistor 234 introduces a high level signal into the gate and maintains the zero bit line of the address at the zero level for the delay time set by the time controller 228. If the 0 bit line of the address bus 218 is at the high level, the high level is delayed for a predetermined time.

Here, the gate portion composed of the transistor 234 and the noah gate 232 is connected to the address bus bit lines, respectively, and the gate portion 230 maintains the level of the corresponding bit line by the number of bit lines of the address bus 218. It is one of a plurality of gate parts.

On the other hand, when the processor controller 200 applies a low level to the read / write control line to the I / O device B, the I / O controller 236 injects and stores data through the data bus 222.

3 is a timing diagram when data write is performed in the clock switching device of the digital processor according to the present invention.

CLK is a system clock of the microprocessor and when the gate portion 230 of the I / O device 230 maintains the bits of the address bus for the period of data processing, the address sensing unit 214 detects whether all addresses are high level. If not, the low level signal is applied to the processor controller 200. At this time, the processor control unit 200 maintains the clock of CLK0 at a low level and applies it to the data I / O unit 216 to match the processing speed of the I / O control unit 236 in the data I / O unit 216. Allows you to send data to write.

The decoder unit 226 of the I / O device B receives and decodes the address at T1 of the system clock CLK. At this time, if the decoding data is at the low level, the address line is latched and the output is kept at the low level for a predetermined period of time.

The processor control unit 200, which has received the low level signal of the address detecting unit 214 at T2 of the microprocessor clock CLK, maintains the I / O control clock CLK0 at a low level and takes data from the I / O control unit 236. When it is time to complete the write, the output of the time control unit 228 becomes high level at T3 of CLK, and the output signal of the NOA gate 232 becomes low level, and the NMOS transistor 234 is cut off, thereby making the address bus line high level. Keep it at Accordingly, the output signal of the address detecting unit 214 becomes high level, and under the control of the processor control unit 200, the I / O control clock CLK0 is operated at the same period as the microprocessor clock CLK. Although the above operation description is described only for performing the write, the same operation is performed when performing the read.

Accordingly, as described above, the clock switching device of the digital processor of the present invention optimizes the efficiency of the system by adjusting the I / O control clock according to the speed of the corresponding I / O device according to the processing speed of the accessed I / O devices. It can increase.

Claims (5)

A clock switching device of a digital processor that operates a plurality of I / O devices connected to a microprocessor at a speed suitable for each I / O device, the clock switching device comprising: generating an address for outputting an address to the I / O device part; An address detecting unit for detecting whether an address of the address bus is active; A decoder unit for decoding the address to determine whether the I / O device is accessed; A delay unit for introducing an output signal of the decoder unit and outputting a delay signal for a predetermined period; A gate unit for introducing a delay signal output from the delay unit, an output signal of the decoder unit, and bits of the address bus to maintain bit values of the address bus while the delay signal is output; And a processor controller configured to control the I / O device by outputting an I / O clock at an active level while the address sensing unit senses an address in an active state and outputs a detection signal. Switching device. The clock switching device of claim 1, wherein the address detecting unit determines that the address is not active when all of the line bits of the address bus are at a high level. The clock switching device of claim 1, wherein the delay unit outputs a delay signal corresponding to a processing speed of each I / O device. The clock switching device of claim 1, wherein the address bus is pulled up. 2. The gate circuit of claim 1, wherein the gate part comprises a series of line bits of the address bus, a noa gate for inputting and outputting output signals of the decoder part and the delay part, and an output of the noa gate and a line of the address bus. And a gate of an NMOS transistor connected between the gates of the NMOS transistor and configured as many as the address bits.