JP3125685B2 - Synchronous semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a synchronous semiconductor memory device.

[0002]

2. Description of the Related Art In recent years, the speed of microprocessors has been remarkably increased, and accordingly, semiconductor storage devices (semiconductor memories)
There is a growing demand for faster speeds. Higher speeds and higher integration of semiconductor memory devices have been achieved by miniaturization of processing technology so far. However, due to the physical limit of process miniaturization and the increase in chip size due to the increase in capacity, demands for higher speeds have been increasing. Is not always fully achieved. In addition, for speeding up, miniaturization and circuit contrivance are being advanced, and as a high-speed memory, a synchronous semiconductor that has an internal pipeline structure and inputs and outputs signals in synchronization with an external clock signal A storage device (synchronous semiconductor memory) has been proposed.

In a conventional semiconductor memory device, RASB (RAS = Row Address Strobe), CASB (CAS = Column Address Strobe), WEB (WE = Write Enable) are provided as external terminals. ), OEB (OE = Output Enable: output enable), and the like, and has control terminals for inputting signals. Various operations are defined by the input level to these control terminals and the context of input timing. Was. Here, the letter "B" added at the end of each signal name
Is used to indicate that the signal or terminal is in negative logic, instead of adding a bar symbol (overline) for indicating that the signal or terminal is in negative logic to the signal name or terminal name.

On the other hand, the operation of the synchronous semiconductor memory device is controlled by inputting a command in synchronization with a system clock (CLK). That is, as shown in FIG. 4, as command input terminals, RASB, CASB,
There are external terminals to which WEB, DQM, and CSB (chip select) signals are respectively input, and various commands can be executed by a combination of logical levels of these external terminals. Further, the synchronous semiconductor device is provided with a plurality of address input terminals to which an address signal generally represented by ADD is input. In this synchronous semiconductor device, an address signal A11 of the plurality of address signals is used to perform bank switching in a memory cell array. Further, the synchronous semiconductor memory device has an input terminal for a system clock CLK,
An input terminal for the clock enable signal CKE is provided.

[0005] In the conventional synchronous semiconductor memory device shown in FIG. 4, signals ADD, CSB, A11, RAS are provided.
B, CASB, WEB, and DQM input circuits 1, 2, 6, 7, 8, 9, and 10, respectively, and a system clock CLK
And an internal clock generating circuit 3 for generating an internal clock ICLK based on a clock enable signal CKE, and an address signal A input via input circuits 1 and 6 in response to a chip select signal CSB input via input circuit 2.
An address latch circuit 4 that latches DD and A11 in synchronization with an internal clock ICLK and outputs the same as an internal address signal IADD, and a command decoder 5 that generates various signals used inside the synchronous semiconductor memory device. , Is provided. Specifically, the command decoder 5
Are signals CSB, A11, RASB, CASB, and WE input via input circuits 22, 6, 7, 8, 9, and 10, respectively.
Based on B and DQM, two systems of row selection control signals ARAS, BRAS, column selection control signal CAS, read signal READ, write signal WRITE, and bank activation signal BANK are output in synchronization with internal clock ICLK.

As shown in FIG. 5, a specification of a command input in such a synchronous semiconductor memory device is, as shown in FIG. 5, from the rising or falling of each signal (represented by the input signal INPUT in FIG. 5) to the system clock CLK. , And a hold time tH, which is a time from the rise of the system clock CLK to the rise or fall of each signal. Here, the signals RASB, CASB, WEB, CSB, DQM,
In addition to CKE, ADD, and All, a data signal DQ input to each of a plurality of data input terminals is included. In order for the synchronous semiconductor memory device to operate normally, a predetermined setup time tS and a predetermined hold time tH must be secured for each signal.

In the above-mentioned synchronous semiconductor memory device,
Among the signals supplied to the command input terminal, the chip select signal CSB has a function of validating the input of each terminal in the synchronous semiconductor memory device only when this signal is at a low level. This chip select signal CS
B is a case where a large number of synchronous semiconductor memory devices are used in a matrix, or a SIMM (Single In-line Memory) is used.
This is effectively used when selecting a specific one from a plurality of synchronous semiconductor memory devices in a module configuration such as a module.

Each address signal ADD is normally fixed to a high level, for example, (or has an indefinite value), and each of the address signals ADD has a desired value during a period (enable period) during which a valid address is provided in a memory cycle. High level or low level to represent the address of The chip select signal CSB is also normally fixed at a high level, and is at a low level only during a specific period in a memory cycle. In order to access the synchronous semiconductor memory device, the chip select signal CSB must be set to a low level in synchronization with the system clock, and at the same time, an address signal ADD specifying a desired address must be supplied to the synchronous semiconductor memory device.

The configuration of a conventional synchronous semiconductor memory device from the input of a signal to an external terminal until the output of internal address signal IADD in synchronization with internal clock ICLK by address latch circuit 4 will be described in detail. . FIG.
1 is a circuit diagram showing a configuration of a portion for generating an internal address signal IADD in a conventional synchronous semiconductor memory device. In the following description, the address signal A11 used for bank switching is generically referred to as an address signal ADD without distinguishing it from other address signals.

On the output side of the input circuit 1 receiving the address signal ADD input to each external address terminal, five inverters INV1 to INV5 are connected in series, and the output of the inverter INV5 at the fifth stage is an internal signal. CADD. Similarly, on the output side of the input circuit 2 that receives the chip select signal CSB input to the external terminal, five inverters INV6 to INV10 are connected in series.
The output of the fifth inverter INV10 is the internal signal CCS.
B. Internal signal CADD and internal signal CCSB
Are input to the NOR gate NR1, and the output of the NOR gate NR1 is input to the address latch circuit 4 as the internal signal EADD. The internal signal CCSB is also input to the command decoder 5. Internal clock ICLK
Is generated in the internal clock generation circuit 3 based on the system clock CLK and the clock enable signal CKE, and is generated by the address latch circuit 4 and the command decoder 5.
Supplied to

In this synchronous semiconductor memory device, NO
An R gate NR1 is provided to output the internal signal CCSB to this NOR.
The reason why the internal signal CADD generated from the address signal ADD input to the gate NR1 is input or not input to the address latch circuit 4 depending on the value of the internal signal CCSB (that is, the internal signal CADB is masked by the internal signal CSSB). This is because only the selected synchronous semiconductor memory device is activated when a large number of synchronous semiconductor memory devices are used in a matrix or when a SIMM configuration is used. That is, by setting the external terminal for the chip select signal CSB to high level in an unused synchronous semiconductor memory device or a synchronous semiconductor memory device not accessed at that time,
The input to each input terminal of the synchronous semiconductor memory device is invalidated to reduce the current. Therefore, FIG.
Although a NOR gate operated by an internal signal CCSB is illustrated as being provided corresponding to one address terminal, a NOR gate operated by an internal signal CCSB is actually provided corresponding to each address terminal. It is provided, and is provided corresponding to each command input terminal as needed. Further, since the internal signal CCSB is an important signal for activating or deactivating the synchronous semiconductor memory device as described above, it is supplied to many circuits in the synchronous semiconductor memory device.

Next, the operation of the conventional synchronous semiconductor memory device will be described with reference to FIG.

An internal clock ICLK is generated in synchronization with the system clock CLK. When the address signal ADD input to the address terminal and the chip select signal input to the command input terminal go to low levels, the internal signals CCSB and CADD both go to low level after a predetermined delay time. The internal signal EADD becomes high level. On the other hand, when the address signal ADD and the chip selector signal CSB go to high levels, the internal signals CCSB and CADD go to high levels, respectively, and the internal signal EADD goes to low level.

In this conventional synchronous semiconductor memory device, as shown in FIG. 8, when an address signal ADD input to an address terminal and a chip select signal CSB input to a command input terminal each become low level, an internal The timing when the signal CCSB changes to the low level is
If the timing at which the internal signal CADD changes to a low level is later than the timing at which the internal signal EADD changes, the timing at which the internal signal EADD changes is restricted by the internal signal CCSB, and the setup time (tAS) of the address signal ADD is limited by the chip select signal CSB. Will be done. Here, that the setup time (tAS) is limited means that even if a signal having a sufficient setup time with respect to the system clock CLK is input to the address terminal as the address signal ADD, the internal portion of the synchronous semiconductor memory device is Because the change of the signal EADD was delayed,
At the input end of the address latch circuit, the internal signal EAD
This means that the interval from the determination of D to the rise of the internal clock ICLK is considerably shorter than the setup time of the input address signal ADD. That is, the address latch circuit 4 latches the internal signal EADD representing the address at the rising edge of the internal clock ICLK, but this means that the internal setup time for the latch operation cannot be sufficiently secured.

Similarly, as shown in FIG. 9, when the address signal ADD and the chip select signal CSB each go high, the internal signal CADD goes higher than the timing when the internal signal CCSB goes high. If the timing is late, the timing of the change of the internal signal EADD is restricted by the internal signal CCSB, and the hold time (tAH) of the address signal is limited by the chip select signal CSB. That is, from the rising of the internal clock ICLK,
In some cases, the time until the internal signal EADD becomes invalid cannot be sufficiently secured.

[0016]

As described above, in the conventional synchronous semiconductor memory device, at the same time as or before the internal signal CADD for an address is determined to be enabled at a low level or a high level and enabled. Internal signal C
If CSB does not become low level, the address set-up time (tAS) becomes longer than the chip select signal CS.
B, and the internal signal CADSB becomes high level at the same time as or after the internal signal CADD is disabled (that is, the internal signal CADD is disabled), or the enable period of the internal signal CADD. , The address hold time (tAH) is limited by the chip select signal CSB.

The internal signal CCSB generated from the chip select signal CSB is used for masking the internal signal CADD generated from the address signal ADD input to each address terminal, and also used in the synchronous semiconductor memory device. To other various circuits. Both the chip select signal CSB and the address signal ADD are generally obtained from a signal on an address bus connected from a CPU or the like. The length of the period when the chip select signal CSB is at a low level and the address signal ADD is enabled. Considering that the lengths of certain periods are considered to be substantially equal, it is difficult to match the timing of the internal signal CCSB with the timing of the internal signal CADD. That is, for each of the plurality of internal signals CADD corresponding to the address terminals, the internal signal CCS
B is set to low level and the internal signal CADD is enabled at the same time, and the internal signal CCS
It is virtually impossible to make B go high and simultaneously disable internal signal CADD. After all, in the conventional synchronous semiconductor memory device, the address setup time (tAS) or the hold time (tAS)
AH) is restricted by the chip select signal CSB.

An object of the present invention is to provide a setup time (tAS) and a hold time (tAH) for an address.
Are to provide a synchronous semiconductor memory device which is not limited by the chip select signal CSB.

[0019]

According to a first aspect of the present invention, an address signal and a chip select signal are input, and a second internal signal based on the chip select signal is disabled. In a synchronous semiconductor memory device having a circuit in which a first internal signal based on a signal is masked, a second internal signal is enabled prior to a first internal signal, and a second internal signal is enabled by the first internal signal. Disabled after signal.

A second synchronous semiconductor memory device according to the present invention comprises:
An address signal and a chip select signal are input, a first internal signal is generated based on the address signal, a second internal signal is generated based on the chip select signal, and a first internal signal is generated based on a value of the second internal signal. A synchronous semiconductor memory device having a gate circuit for masking the internal signal of
A signal delay time from the input terminal of the address signal to the input terminal of the gate circuit is defined as a first delay time, and a signal delay time from the input terminal of the chip select signal to the input terminal of the gate circuit is defined as a second delay time. When the first internal signal is changed from the mask to the unmask, the second delay time is shorter than the first delay time, and when the first internal signal is changed from the unmask to the mask, the second delay time is longer than the first delay time. .

A third synchronous semiconductor memory device according to the present invention comprises:
A first input circuit to which an address signal is input, a second input circuit to which a chip select signal is input, and a first internal circuit which delays an output of the first input circuit by a predetermined time to form a first internal signal A signal generation circuit, a second internal signal generation circuit for generating a second internal signal based on an output of the second input circuit, and a mask for masking the first internal signal with a value of the second internal signal. A gate circuit, wherein a signal delay time in the first internal signal generation circuit is defined as a first delay time, and a signal delay time in the second internal signal generation circuit is defined as a second delay time. When the internal signal is changed from the mask to the unmask, the second delay time is shorter than the first delay time, and when the first internal signal is changed from the unmask to the mask, the second delay time is longer than the first delay time.

[0022]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows an internal address signal I in a synchronous semiconductor memory device according to an embodiment of the present invention.
FIG. 3 is a circuit diagram illustrating a configuration of a part that generates ADD. The synchronous semiconductor memory device of the present embodiment has the same configuration as the conventional synchronous semiconductor memory device shown in FIG.
As shown in FIG. 1, a circuit configuration of a portion that receives an address signal ADD and a chip select signal CSB and generates an internal address signal IADD is different from the conventional synchronous semiconductor memory device shown in FIG.

On the output side of the input circuit 1 receiving the address signal ADD input to the external address terminal, five inverters INV1 to INV5 are connected in series, and the output of the fifth inverter INV5 is the internal signal CADD. It has become. On the other hand, the output of the input circuit 2 receiving the chip select signal CSB input to the external input terminal is branched into two, and one of the branches has five inverters INV6-IV
NV10 is connected in series, and the inverter I of the fifth stage
The output of the NV 10 is supplied to the command decoder 5 as an internal signal CCSB. The other of the branched outputs of the input circuit 2 is input to the inverter INV11, and the output of the inverter INV11 is supplied to the first NAND gate ND1.
Is input to one of the input terminals. The output of the first NAND gate ND1 is input to one input terminal of the second NAND gate ND2 and is input to the inverter INV12. The output of the second NAND gate ND2 is
The signal is input to the other input terminal of the first NAND gate ND1. Further, an inverter INV13 for receiving the output of the inverter INV8 is provided.
The output of V13 is input to the other input terminal of the second NAND gate ND2.

As is apparent from this configuration, the NAND gates ND1 and ND2 constitute an RS flip-flop, and the output of the inverter INV11 becomes a set signal to the RS flip-flop, and the inverter INV13
Is a reset signal to the RS flip-flop. A signal obtained by inverting the output of the RS flip-flop by the inverter INV12 is an internal signal CCSAD.
B, and the internal signal CCSADB is input to the NOR gate NR1 together with the internal signal CADD on the address signal side. The output of the NOR gate NR1 is the internal signal EAD.
D is input to the address latch circuit 4.

An internal clock ICLK is supplied to the address latch circuit 4 and the command decoder 5, and the internal clock ICLK is supplied to the system clock C.
It is generated in the internal clock generation circuit 3 from LK and the clock enable signal CKE. Address latch circuit 4
Latches the internal signal EADD in synchronization with the internal clock ICLK and outputs it as the internal address signal IADD.

Next, the operation of the synchronous semiconductor memory device of this embodiment will be described with reference to FIG. In the synchronous semiconductor memory device of the present embodiment, it is assumed that the signal delay times of input circuit 1 and input circuit 2 are substantially the same. Also, each logic gate (inverter, NAND gate and N
The gate delay time for each OR gate is almost the same, and the delay time in the logical path can be represented by the number of gate stages.

Address signal AD input to the address terminal
D and a chip select signal C input to the command input terminal
Assuming that SB goes low at almost the same time, the output of the inverter INV11 goes low and the above-mentioned RS
The flip-flop is set and the inverter INV12
Becomes low level. Due to the difference between the number of gate stages from the input circuit 1 to the inverter INV5 and the number of gate stages from the input circuit 2 to the inverter INV12 on the path via the inverter INV11, the internal signal CADD remains at a high level at this time. The signal EADD also remains at the low level. Thereafter, the internal signal CADD changes to low level, and the internal signal EADD changes to high level.
Note that, due to the difference between the number of gate stages from the input circuit 2 to the inverter INV12 and the number of gate stages from the input circuit 2 to the inverter INV10 in the path via the inverter INV11, the internal signal CCSB A
Changes to low level earlier.

Address signal AD input to the address terminal
D and a chip select signal C input to the command input terminal
Assuming that SB goes high at almost the same time, the internal signal CADD goes high and the internal signal EADD goes low. At this time, the output of the inverter INV13 remains at a high level due to the difference between the number of gate stages from the input circuit 1 to the inverter INV5 and the number of gate stages from the input circuit 2 to the inverter INV12 in the path via the inverter INV13. After that, the inverter IN
The output of V13 goes low, the RS flip-flop is set, and the internal signal CCSADB output from the inverter INV12 goes high, but the internal signal EADD remains low. Note that due to the difference between the number of gate stages from the input circuit 2 to the inverter INV12 in the path via the inverter INV13 and the number of gate stages from the input circuit 2 to the inverter INV10, the internal signal CCSB becomes higher in level earlier than the internal signal CCSADB. Is changing.

That is, in the present embodiment, the internal signal CCSADB goes low before the internal signal CADD generated from the address signal ADD is enabled, and the internal signal CCSADB goes high after the internal signal CADD is disabled. Therefore, the address setup time (tAS) and the hold time (tA)
H) is not limited by the chip select signal CSB.

Next, a synchronous semiconductor memory device according to another embodiment of the present invention will be described with reference to FIG. FIG.
1 is a circuit diagram showing a configuration of a portion for generating an internal address signal IADD in the synchronous semiconductor memory device.

This synchronous semiconductor memory device is the same as the synchronous semiconductor memory device shown in FIG.
ＩＮINV13 and NAND gates ND1 and ND2 are replaced by inverters INV14 and INV15, a delay element DL1 and a NOR gate NR2. That is, the output of the input circuit 2 is, in addition to the inverter INV6,
The input to the inverter INV14 and the delay element DL1, the output of the inverter INV14 is input to the inverter INV15, the output of the inverter INV15 and the output of the delay element DL1 are input to the NOR gate NR2, and the NOR gate NR
2 outputs the signal CCSADB as the NOR gate NR1.
Is being entered. The delay time of the delay element DL1 is, for example, a value corresponding to five stages in terms of the number of gate stages.

Next, the operation of the synchronous semiconductor memory device will be described.

Address signal AD input to the address terminal
D and a chip select signal C input to the command input terminal
Assuming that SB goes low at almost the same time, the output of the inverter INV15 goes high, and the internal signal CCSADB output from the NOR gate NR2 goes low. Due to the difference between the number of gate stages from the input circuit 1 to the inverter INV5 and the number of gate stages from the input circuit 2 to the NOR gate NR2 in the path via the inverter INV14, the internal signal CADD remains at a high level at this time. The internal signal EADD also remains at the low level. Thereafter, the internal signal CADD changes to low level, and the internal signal EADD changes to high level. Note that the internal signal CCSB depends on the difference in the number of gate stages.
The internal signal CCSADB changes to the low level earlier than that of the internal signal CCSADB.

Address signal AD input to the address terminal
D and a chip select signal C input to the command input terminal
Assuming that SB goes high at almost the same time, the internal signal CADD goes high and the internal signal EADD goes low. At this time, the output of the delay element DL1 remains at the high level, and the internal signal CCSADB output from the NOR gate NR2 remains at the low level. After that, the output of the inverter INV14 and the output of the delay element DL1 both go low, and the internal signal CCSADB from the NOR gate NR2 goes high, but the internal signal EADD remains low. Note that, due to the difference in delay time, the internal signal C
The CSB changes to the high level earlier.

That is, also in the synchronous semiconductor memory device shown in FIG. 3, in the present embodiment, the internal signal CCSADB goes low before the internal signal CADD generated from the address signal ADD is enabled, and the internal signal CADD goes low. Internal signal CCS after disabled
Since ADB is at high level, the setup time (tAS) and the hold time (tAH) of the address are not limited by the chip select signal CSB.

[0036]

As described above, according to the present invention, the internal signal based on the chip select signal is enabled prior to the internal signal based on the address signal, and the internal signal based on the chip select signal is enabled based on the address signal. By configuring so as to be disabled after a signal, there is an effect that neither the setup time (tAS) nor the hold time (tAH) of the address is limited by the chip select signal.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a main part of a synchronous semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is an operation waveform diagram illustrating an operation of the synchronous semiconductor memory device shown in FIG.

FIG. 3 is a circuit diagram showing a configuration of a main part of a synchronous semiconductor memory device according to another embodiment of the present invention.

FIG. 4 is a block diagram illustrating a configuration of a synchronous semiconductor memory device.

FIG. 5 shows setup time tS and hold time t
It is a waveform diagram explaining H.

FIG. 6 is a circuit diagram showing a configuration of a main part of a conventional synchronous semiconductor memory device.

7 is a waveform diagram illustrating an example of an operation in the conventional synchronous semiconductor memory device shown in FIG.

8 is a waveform diagram illustrating another example of the operation in the conventional synchronous semiconductor memory device shown in FIG.

FIG. 9 is a waveform diagram illustrating still another example of the operation in the conventional synchronous semiconductor memory device shown in FIG.

[Explanation of symbols]

 1, 2, 6 to 10 Input circuit 3 Internal clock generation circuit 4 Address latch circuit 5 Command decoder INV1 to INV15 Inverter NR1 to NR2 NOR gate ND1 to ND2 NAND gate DL1 Delay element

Claims (4)

(57) [Claims] 1. A circuit in which an address signal and a chip select signal are input and a first internal signal based on the address signal is masked by disabling a second internal signal based on the chip select signal. Wherein the second internal signal is enabled prior to the first internal signal, and the second internal signal is disabled after the first internal signal. A synchronous semiconductor memory device. 2. An address signal and a chip select signal are input, a first internal signal is generated based on the address signal, a second internal signal is generated based on the chip select signal, and the second internal signal is generated. A synchronous semiconductor memory device having a gate circuit for masking the first internal signal according to the value of the internal signal, wherein an internal address signal is generated in accordance with an output of the gate circuit. A signal delay time from an end to an input terminal of the gate circuit is defined as a first delay time, and a signal delay time from an input terminal of the chip select signal to an input terminal of the gate circuit is defined as a second delay time. When the internal signal 1 is changed from the mask to the unmask, the second signal
Wherein the second delay time is longer than the first delay time when the first internal signal is changed from unmasked to masked. apparatus. 3. A first input circuit to which an address signal is inputted, a second input circuit to which a chip select signal is inputted,
The output of the first input circuit is delayed for a predetermined time,
A first internal signal generation circuit for generating an internal signal of
A second internal signal generating circuit that generates a second internal signal based on an output of the input circuit of the second embodiment, and a gate circuit for masking the first internal signal with a value of the second internal signal. The first internal signal is defined as a signal delay time in the first internal signal generation circuit as a first delay time, and a signal delay time in the second internal signal generation circuit as a second delay time. When the mask is changed from the mask to the unmask, the second delay time is shorter than the first delay time. When the first internal signal is changed from the unmask to the mask, the second delay time is shorter than the first delay time. Long synchronous semiconductor memory device. 4. An internal clock generation circuit for generating an internal clock based on an input system clock, an address latch circuit for latching an output of the gate circuit in synchronization with the internal clock to generate an internal address signal, 4. An internal chip select signal generation circuit for delaying an output of the second input circuit for a predetermined time to generate an internal chip select signal, and a command decoder to which the internal chip select signal and the internal clock are input.
3. The synchronous semiconductor memory device according to item 1.