KR100218301B1 - Semiconductor memory device - Google Patents

Abstract

In the semiconductor memory device of the present invention, when an input address is stored and a new address is input, a plurality of comparison and latch units for determining whether or not a hit is compared with the stored address and the determination result of the comparison and latch unit are input. And a hit controller configured to generate a control signal to immediately access the information of the corresponding memory cell, omitting the enable of the word line driver and the sense amplifier, and if the address stored in the compare and latch unit and the input address signal are hit, By directly accessing the data of the corresponding memory cell without enabling the word line and the sensing, the power consumption can be reduced and the data processing speed can be improved.

Description

Semiconductor memory device

1 shows the structure of a semiconductor memory device according to the prior art,

2 shows a configuration of a semiconductor memory device according to the present invention.

3 shows a detailed circuit of the hit controller of FIG.

4 shows a detailed circuit of the word line driver of FIG.

* Explanation of symbols for main parts of the drawings

110: address buffer 120: comparison and latch unit

130: hit control unit 140: low decoder

150: word line driver 160: memory cell unit

170: sense amplifier 180: column decoder

The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device for minimizing power consumption and improving access speed.

As the use of semiconductor memory devices has been widely expanded in large computers, such as PCs, communication devices, and imaging devices, demands for high performance and multifunctionality are increasing. The research to minimize the increase of power consumption and improve the processing speed is active.

FIG. 1 shows a conventional semiconductor memory device, comprising n address buffers 10 for latching an address signal ADD in synchronization with an external clock, and the address. A row decoder 20 for decoding a signal and selecting a word line, a word line driver 30 for driving a word line selected by the row decoder 20, A memory cell unit 40 in which a plurality of memory cells are arranged, a sense amplifier 50 for amplifying information of the selected memory cell, and a column decoder for selecting the sense amplifier 50 It consists of 60.

In operation, the address buffer 10 latches an address signal in synchronization with an external clock, selects and drives a word line in the row decoder 20 to select a memory cell of the memory cell unit 40, thereby selecting information on the selected memory cell. Is transmitted to a data line, which is amplified by the sense amplifier 50.

The column decoder 60 selects the sense amplifier 50 so that the information is sent to an output buffer (not shown) through a bus line. This series of operations is performed to prevent destruction of memory cell information. It is controlled by an internal clock and executed in a predetermined order and timing.

However, in the conventional semiconductor memory device as described above, after enabling the word line and the sensing every time the address signal is input, since the information of the memory cell is output through the output buffer, power consumption is high, and processing speed is increased. There is a problem that is difficult to improve.

Accordingly, an object of the present invention is to solve the above problems, by directly accessing the information of the memory cell without enabling the word line and the sensing to reduce the power consumption, improve the data processing speed To provide a semiconductor memory device that can be made.

In order to achieve the above object, the memory device of the present invention stores an input address and inputs a plurality of comparison and latch parts for determining whether a hit is made by comparing with the stored address when a new address is input and input of a result of the comparison and latch part. In this case, the hit control unit for generating a control signal is configured to omit the enable of the word line driver and the sense amplifier and immediately access the information of the corresponding memory cell.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

As shown in FIG. 2, the semiconductor memory device of the present invention stores an address buffer 110 for latching when an address is input, an address signal of the address buffer 110, and compares the stored address with the next address input. When the hit signal (HIT) is applied from the plurality of comparison and latch unit 120 and the comparison and latch unit 120 to determine whether the hit (HIT) is performed by performing a corresponding operation to sense in the column decoder 180 The hit control unit 130 for selecting the amplifier 170 to output the amplified data, and if the comparison and latching unit 120 discrimination results are not hit, decode the input address signal to decode the memory through word line selection. A row decoder 140 for designating a cell, a word line driver 150 for driving a word line selected by the row decoder 140, and a memory storing data A unit 160, a sense amplifier 170 for amplifying data of the selected memory cell, and a column decoder 180 for accessing data of the amplified memory cell by selecting the sense amplifier 170. .

The comparison and latch unit 120 stores the input address and compares it with the newly input address. As described above, each of the remarks and the latch unit 120 is allocated with one compare and latch unit 120 per memory cell that operates independently as a plurality, and thus can store an address for one memory cell. Word lines and sensing can be performed.

The hit controller 130 inverts the outputs of the NAND gate 131 and the NAND gate 131 which input the hit signal HIT and the refresh signal REFRESH as shown in FIG. An inverter 132 for outputting a hit control signal HITi, a delayer 133 for delaying the output of the NAND gate 131, an inverter for inverting the output of the delayer 133 ( 134, a NAND gate 135 that takes an output of the NAND gate 131 and an output of the inverter 134, and an output of the NAND gate 135 to generate a hit failure control signal MISSi. An inverter 136 for outputting.

In addition, as shown in FIG. 4, the word line driver includes an address coding unit 151 which receives a hit control signal HITi, a gate thereof is connected to the address coding unit 151, and a source is coded differently. An NMOS transistor 153 connected to the drain of the PMOS transistor 154, a drain of which is applied to the hit control signal, a voltage of Vpp to a source, and a drain of the NMOS transistor 153 connected to the drain of the PMOS transistor 154. As described above, the PMOS transistor 154 connected to the drain of the NMOS transistor 153 and the gate are connected to the drain of the PMOS transistor 154 through a connection point a, and the voltage Vpp is applied to the drain. The applied PMOS transistor 155, the drain and the gate of the PMOS transistor 154 are connected through the connection point a, and the drain is connected to the source of the PMOS transistor 155 through the connection point b. A source connected to the grounded NMOS transistor 156, an inverter 157 connected such that the connection point b inverts the signal and fed back to the input side of the connection point a, and the source is a word line 158. The NMOS transistor 159 is connected to the gate and is applied with the miss failure control signal MISSi.

Referring to the operation method, when an address is first input, the word line and the sensing enable process are skipped in comparison with the address stored in the comparison and latch unit 120, and the column decoder 180 of the memory cell unit 160 is immediately used. If the information of the selected memory cell is accessed, and the result of the hit fails, the corresponding address of the comparison and latch unit 120 is replaced with the newly entered address, and the data of the memory cell of the memory cell unit 160 is processed in the same order as before. Access.

At this time, the hit controller 130 outputs the hit control signal HITi through the inverter 132 when the hit signal and the refresh control signal REFRESH match, and the NAND gate 131 when the hit signals do not match. ) And a signal of the failure failure control signal MISSi by comparing the output signal of the signal with the delayed and inverted by the delayer 133 and the inverter 134 at the NAND gate 135 and generating the word line. The word line stopped by the comparing and latching unit 120 together with the driving unit 150 is always maintained in an active state regardless of an external control signal, and the hit control unit 130 controls the hit state. The signal HIT / MISS0... N-1 is applied to the word line driver 150 to perform an operation according to the hit or the failure.

In addition, the NMOS transistor 159 of the word line driver 150 clears the contents and the word line of the compare and latch unit 120 only when a refresh cycle is performed together with the compare and latch unit 120.

As described above, according to the present invention, when the address stored in the comparison and latch unit and the input address signal are hit, the power consumption is reduced by directly accessing the data of the corresponding merolicell without enabling the word line and the sensing. As a result, data processing speed can be improved.

Claims (3)

A plurality of comparison and latch units for storing an input address and comparing the stored address with a new address and determining whether a hit has been received, and if the result of the comparison and latch unit is determined as an input, the word line driver and the sense amplifier And a hit controller for generating a control signal so as to omit the enable and immediately access the information of the corresponding memory cell. The NAND gate of claim 1, wherein the hit controller is configured to invert the outputs of the NAND gate 131 and the NAND gate 131 as inputs of the hit signal HIT and the refresh signal REFRESH. Inverter 132, a delayer 133 for delaying the output of the NAND gate 131, an inverter 134 for inverting the output of the delayer 133, and the NAND gate 131. NAND gate 135 for inputting the output of the inverter and the output of the inverter 134, and an inverter 136 for inverting the output of the NAND gate 135 to output a hit failure control signal A semiconductor memory device, characterized in that. 2. The word line driver of claim 1, wherein the word line driver comprises an address coding unit 151 which receives a hit control signal HITi, an NMOS transistor 153 whose gate is connected to the address coding unit 151, The hit control signal is applied to the address coding unit 152 and the gate connected to the source side of the MOS transistor 153, the voltage Vpp is applied to the source, and the drain is connected to the drain of the NMOS transistor 153. A MOS transistor 154, a drain and a gate of the PMOS transistor 154 are connected through a connection point a, a PMOS transistor 155 to which a voltage Vpp is applied to a drain, and a gate of the PMOS transistor 154. A drain of the transistor 154 is connected through the connection point (a) and a drain is connected to a source of the PMOS transistor 155 through a connection point (b), the source of which is connected to the grounded NMOS transistor 156, and Connection point An inverter 157 and a source connected to the word line 158 connected to the inverter 157 connected to invert the signal of (b) and fed back to the connection point (a), and the NMOS transistor to which the hit failure control signal MISSi is applied to the gate 159) comprising a semiconductor memory device.