JP2003323393A - Peripheral device control circuit and electronic circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a peripheral device control circuit that outputs a control signal output from a CPU to a peripheral device as an optimal control signal synchronous with a clock signal. <P>SOLUTION: An edge detection part 22 detects a leading edge or trailing edge of a CS signal to output an edge detection signal. Upon input of the edge detection signal, a peripheral device selection part 25 captures various selection signals from an address decoding part 21 to determine which of a plurality of peripheral devices is operated. In dependence on the determination result, any of CSB1-3 signals, and a WRB signal or an RDB signal are output. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit for controlling the operation of peripheral devices.

[0002]

2. Description of the Related Art When a CPU (Central Processing Unit) controls a plurality of peripheral devices via a data bus, an address bus or the like, a chip select signal (hereinafter referred to as "CS signal") output from the CPU is called. Write enable signal (hereinafter referred to as "WE signal"), read enable signal (hereinafter referred to as "OE signal").
Say ) And other control signals are used for peripheral device control ASI.
It is output to each peripheral device via C (Application Specific Integrated Circuit).
The CS signal is a signal for starting the operation of the peripheral device, the WE signal is a signal for setting the peripheral device in the write mode, and the OE signal is a signal for setting the peripheral device in the read mode.

In particular, the WE signal output from the CPU and the O
When the end of the pulse of the E signal and the timing of data or address change propagating on the data bus or address bus are almost at the same time, the peripheral device may input uncertain data, which causes the circuit operation. Becomes unstable. Therefore, the WE signal and OE output from the CPU
For controlling the pulse width of control signals such as signals for peripheral device control
The circuit malfunction is prevented by the SIC adjusting and outputting to the peripheral device.

[0004]

However, the above-mentioned C
PU, peripheral device and ASIC for controlling peripheral device
Even if the same clock signal is input to the CPU, the CPU multiplies the clock signal by an internal circuit and performs circuit operation in synchronization with the high-speed clock signal. Therefore, the address signal, CS signal, WE signal and O output from the CPU
The E signal is likely to be input asynchronously to the peripheral device control ASIC operating in synchronization with the normal clock signal.

FIG. 4 is a diagram showing a time chart of a write cycle and a read cycle of the CPU. The ADR signal represents an address signal output from the CPU, and the DATA signal in FIG. 4A represents a data signal output from the CPU. The DATA signal shown in FIG. 4B represents a data signal input to the CPU. As shown in FIG. 4, the CS signal changes at the same time as the ADR signal changes, and at the same time, the WE signal or OE signal also changes. If this signal change is asynchronously input to the peripheral device control ASIC, the peripheral device control ASIC may latch an indefinite address signal or data signal, causing a malfunction of the circuit.

In order to solve this problem, the address strobe signal indicating that the address signal has been determined is sent to the CP.
There is a method of outputting from the U to the peripheral device control ASIC. Then, the peripheral device controlling ASIC latches the address signal based on the input of the address strobe signal, whereby the indefinite latching of the address signal can be prevented.

However, it is necessary to newly provide an input terminal for inputting the address strobe signal to the ASIC for controlling the peripheral device, which makes it difficult to secure the power supply terminal or the ground terminal, and the peripheral device controlling A
This causes a decrease in the reliability of the SIC. Further, there is a problem that the circuit board is enlarged by newly adding wiring for the address strobe signal on the circuit board.

An object of the present invention is to provide a peripheral device control circuit which outputs a control signal output from a CPU to a peripheral device as an optimum control signal synchronized with a clock signal.

[0009]

In order to solve the above problems, the invention according to claim 1 is configured such that predetermined data, an instruction signal and a clock signal can be externally input, and a plurality of peripheral devices are provided. A peripheral device control circuit to be connected, which decodes the predetermined data and outputs a decoded signal, and detects a rising or falling of the instruction signal and outputs a detection signal in synchronization with the clock signal. An edge detection unit, a selection that inputs the decode signal and the detection signal, and selectively selects a peripheral device from the plurality of peripheral devices based on the decode signal when the detection signal is input And a section.

According to the first aspect of the invention, even when the predetermined data and the instruction signal are asynchronously input to the peripheral device control circuit, the rising or falling of the instruction signal is detected and the clock signal is output. Peripheral devices are selected based on the decode signals obtained by decoding the predetermined data with the synchronized detection signal as a signal, so malfunctions caused by the decode signals of the predetermined data in an indeterminate state are prevented, and the peripheral devices are accurately selected. be able to.
Therefore, it is possible to cause the peripheral device to perform stable circuit operation.

Further, since it is not necessary to input an address strobe signal or the like indicating that the predetermined data has been determined, it is possible to add a power supply terminal or a ground terminal by reducing the input terminals, and reliability is provided by reinforcing the power supply and the ground. It is possible to realize a high peripheral device control circuit.

The invention according to claim 2 is the peripheral device control circuit according to claim 1, wherein the detection signal is input,
A counter unit that starts a count operation based on the clock signal when input, a storage unit that stores a given value, and a count value by the counter unit and a value stored in the storage unit are compared. A comparison unit, and when the comparison unit determines that the values are the same, outputs a control signal for performing a predetermined control for the peripheral device selected by the selection unit. .

Further, as in the invention described in claim 3, in the peripheral device control circuit according to claim 2, the storage section stores a first value and a second value, and the comparison section The count value is compared with the first value, and the count value is compared with the second value, and the comparison unit determines that the count value and the first value are the same. After that, the control signal may be output until the count value and the second value are determined to be the same.

According to the second and third aspects of the present invention, the output timing of the control signal can be adjusted by changing the value stored in the storage section. We can flexibly respond to changes. Further, it is not necessary to redesign the peripheral device control circuit due to changes in the specifications of the peripheral device, and it is possible to suppress development costs and the like.

The invention according to claim 4 is the peripheral device control circuit according to claim 2 or 3, wherein the control signal is a write enable signal or a read enable signal.

According to the invention of claim 4, the write enable signal is not required for redevelopment of the peripheral device control circuit according to the change of the specifications of the write cycle and the read cycle accompanying the replacement of the peripheral device. The output timing of the read enable signal can be adjusted.

According to a fifth aspect of the present invention, the peripheral device control circuit according to any one of the first to fourth aspects operates with a signal faster than the clock signal, and the predetermined data and the instruction signal are transmitted. It is characterized by comprising a processor for outputting to the peripheral device control circuit and a plurality of peripheral devices connected to the peripheral device control circuit.

According to the invention described in claim 5, by inputting the control signal output from the processor operating by the high-speed clock signal to the peripheral device control circuit according to any one of claims 1 to 4. The peripheral device control circuit can output a stable control signal to the peripheral device in synchronization with the clock signal. Therefore, it is possible to prevent malfunction of peripheral devices and provide an electronic circuit that performs stable circuit operation.

[0019]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to FIG.
~ It demonstrates together with FIG. In FIG. 1, the CPU 11 has peripheral devices 13 to 15 via an address bus and a data bus.
FIG. 3 is a block diagram showing a configuration of an electronic circuit for controlling the. In the figure, electronic circuits include a CPU 11, a peripheral device control ASIC 12, peripheral devices 13, 14, and 1.
5. It is composed of an address bus and a data bus.

The CPU 11 has a WE signal and an OE signal in accordance with instructions such as programs stored in a ROM (not shown).
A control signal such as a signal and one of a plurality of CS signals (for example, a CS0 signal; hereinafter simply referred to as “CS signal”) is output to the peripheral device control ASIC 12. Further, it controls the operation of each part of the circuit such as outputting necessary data to the address bus and the data bus and processing the data output from each circuit to the data bus.

The peripheral device control ASIC 12 is SY
The SCLK signal and the WE signal, the OE signal, and the CS signal from the CPU 11 are input, and the peripheral devices 13 to 15 are synchronized with the SYSCLK signal by the WRB signal (write enable signal), the RDB signal (read enable signal),
It outputs CSB1, 2 and 3 signals (chip select signal).

The SYSCLK signal is an A for controlling peripheral devices.
This is a clock signal for operating the SIC 12. W
The RB signal and the RDB signal are supplied to the peripheral devices 13 to 15
Is a signal for setting the write mode or the read mode, and is output as a common signal to the peripheral devices 13 to 15. The WRB signal and the RDB signal are not limited to this, and signals may be generated for the peripheral devices 13 to 15, respectively. The CSB1-3 signals are signals for starting the operation of the peripheral devices 13-15, and are output to each of the peripheral devices 13-15.

Further, the peripheral device control ASIC 12 is
Input data required for circuit operation from address bus and data bus. Details of the contents of the data will be described later. The peripheral device control ASIC 12 also has a function as a peripheral device control circuit, and the CS signal means an instruction signal.

The peripheral devices 13 to 15 are registers and Rs.
It is a semiconductor circuit provided with storage means such as OM or RAM, and receives WRB signal and RDB signal from the peripheral device controlling ASIC 12 and CSB1 to 3 signals respectively. When the write mode is set by the WRB signal, the address data and the data output from the CPU 11 to the address bus and the data bus are read, and the data are stored in the storage means in the peripheral devices 13 to 15. When the read mode is set by the RDB signal, the address data output from the CPU 11 to the address bus is read, the data is read from the storage means in the peripheral devices 13 to 15, and is output to the data bus.

FIG. 2 shows an ASIC 12 for controlling peripheral devices.
3 is a block diagram showing the internal configuration of FIG. The peripheral device control ASIC 12 includes an address decoding unit 21, an edge detection unit 22, a counter unit 23, a pulse width setting unit 24, and a peripheral device selection unit 25.

The address decoding unit 21 decodes the data output from the CPU 11 to the address bus. Here, the data output to the address bus by the CPU 11 is data indicating which semiconductor circuit of the peripheral device control ASIC 12 and the peripheral devices 13 to 15 is activated, and the address decoding unit 21.
Outputs to the peripheral device selection unit 25 any one of the ASIC select signal, the peripheral device 1 select signal, the peripheral device 2 select signal, and the peripheral device 3 select signal based on the decoded result. Book A
The SIC select signal is a signal indicating the start of operation of the pulse width setting unit 24. The peripheral device 1 to 3 select signals are transmitted by the peripheral device selection unit 25 to the peripheral devices 13 to 15
Among them, the peripheral device 1 select signal is the peripheral device 13, the peripheral device 2 select signal is the peripheral device 14, and the peripheral device 3 select signal is the peripheral device. This is a signal indicating that 15 is operated. Further, the address decoding unit 21 has a function as a decoding unit.

The edge detector 22 receives the CS signal output from the CPU 11 and the SYSCLK signal from the outside, and when it detects the trailing edge of the CS signal, the SYSCL
A pulse for one cycle of the K signal is output to the counter unit 23 and the peripheral device selection unit 25 as an edge detection signal.
In the present embodiment, the signal level of the CS signal is "Lo
In order to describe the case of w "as the active state, the edge detection unit 22 detects the falling edge of the CS signal and outputs the edge detection signal. However, not limited to this, when the signal level of the CS signal is" Hi ". When is activated, the rising edge of the CS signal is detected and an edge detection signal is output.

The counter section 23 receives the edge detection signal and the SYSCLK signal from the edge detection section, and when the pulse of the edge detection signal is input, it performs the counting operation in synchronization with the SYSCLK signal. The count value is output to the count value comparison unit 251 of the peripheral device selection unit 25.
The count value is reset to the initial value when it reaches a predetermined count value or when the CS signal rises. In this embodiment, the CS signal has a signal level of "L".
In order to explain the case of "ow" as an active state, CS
Although it has been stated that the count value is reset to the initial value by the rising edge of the signal, the present invention is not limited to this, and when the signal level of the CS signal is "Hi", the count value is initialized by the falling edge of the CS signal. Reset.

The pulse width setting unit 24 includes a register circuit and the like. When the peripheral device selecting unit 25 inputs the present ASIC chip select signal and the present ASIC write enable signal, the setting data is inputted from the data bus to the register circuit. Etc. Then, the stored data is output to the peripheral device selection unit 25 as a set value. Further, the pulse width setting unit 24 inputs the SYSCLK signal, and these circuit operations are performed in synchronization with the SYSCLK signal.

Here, the pulse width setting section 24 has a WRB
The setting values for starting and ending the signal and the RDB signal are stored. As the configuration of the pulse width setting unit 24,
For example, a pulse start setting register and a pulse end setting register are provided for the WRB signal and the RDB signal input to the peripheral devices 13 to 15, respectively. For example, as the setting value of the WRB signal of the peripheral device 13,
If “m” is stored in the pulse start setting register and “n” is stored in the pulse end setting register (n and m are integers of 1 or more, m <n), the WRB signal output from the peripheral device selection unit 25 is counted. When the value is "m", it is in the active state, and when the count value is "n", it is released from the active state. The pulse width setting unit 24 also has a function as a storage unit.

The peripheral device selection unit 25 uses the SYSCLK
Based on the signal, the peripheral device 1 to 3 select signal input from the address decoding unit 21, and the edge detection signal input from the edge detection unit 22, which one of the peripheral devices 13 to 15 is selected. CSB when deciding whether to operate and operating peripheral device 13
1 signal, CSB when operating the peripheral device 14
2 signals, CSB when operating the peripheral device 15
Outputs 3 signals. Further, when the real ASIC select signal is input from the address decoding unit 21, it is stored in another storage means such as a register provided in the pulse width setting unit 24 or the peripheral device control ASIC 12 according to the input real ASIC select signal. The present ASIC chip select signal and the present ASIC write enable signal are output.

The peripheral device selection unit 25 also includes a count value comparison unit 251. The count value comparison unit 251
The set value stored in the pulse width setting unit 24 is compared with the count value input from the counter unit 23. Then, the peripheral device selection unit 25 outputs the WRB signal and the RDB signal based on the comparison result of the count value comparison unit 251. The count value comparison unit 251 has a function as a comparison unit.

Next, the operation of the peripheral device control ASIC 12 will be described. Figure 3 shows the ASIC for controlling peripheral devices.
12 is a timing chart in the write mode of No. 12, as an example, a timing chart when the peripheral device 13 is accessed. The shaded time zones shown in the ADR signal and the peripheral device 1 select signal are
The uncertain time zone of data is shown. In the present embodiment, peripheral device 1 select signal, CS signal, CSB
The 1 signal, the WE signal, and the WRB signal will be described as active states when the signal level is “Low”.

Further, as an example of the set value of the WRB signal of the peripheral device 13, the pulse width setting section 24 is described assuming that "1" is stored in the pulse start setting register and "3" is stored in the pulse end setting register. To do.

First, the edge detector 22 detects the trailing edge of the CS signal and sets the edge detection signal to "Hi".
The edge detection signal corresponds to one cycle of the SYSCLK signal, that is,
From the rising edge of the cycle (2) of the SYSCLK signal
It becomes “Hi” and becomes “Low” at the moment of rising of cycle (3).

The edge detection signal changes from "Hi" to "Low".
Then, that is, at the rising edge of the cycle (3) of the SYSCLK signal, the peripheral device selection unit 25 inputs various selection signals from the address decoding unit 21. In FIG. 3, since the peripheral device 1 select signal is “Low” and is in an active state, the peripheral device selection unit 25 selects CS
The B1 signal is set to "Low". Further, the counter unit 23 is S
Counting is started in synchronization with the YSCLK signal.

Since the WE signal is "Low" and in the active state, the peripheral device selection unit 25 inputs the set value of the WRB signal of the peripheral device 13 from the pulse width setting unit 24, and the set value and the count value. To compare. WR
Since the pulse start register of the B signal stores "1", it is synchronized with the rising edge of the next SYSCLK signal when the count value becomes "1", that is, with the rising edge of the cycle (4) of the SYSCLK signal. Then, the peripheral device selection unit 25 sets the WRB signal to "Low".

Next, since the pulse end register of the WRB signal stores "3", it synchronizes with the next rising edge of the SYSCLK signal when the count value becomes "3", that is, the cycle of the SYSCLK signal ( The peripheral device selection unit 25 sets the WRB signal to "H" in synchronization with the rising edge of 6).
i ".

In this way, the trailing edge of the CS signal is detected, the edge detection signal is used as a pulse signal, and one cycle of the SYSCLK signal is output. At the same time as the end of the pulse signal, the peripheral device selection section 25 causes the address decoding section 25 to output the signal. 21
By further inputting the decode signal and determining the peripheral device to be operated, it is possible to prevent the peripheral device to be operated from being selected by the uncertain data of the ADR signal and the peripheral device 1 select signal shown by hatching.

In the read mode as well as in the write mode, the circuit operation is performed on the basis of the various select signals output from the address decoding section, the edge detection signal, the counter value and the set value stored in the pulse width setting section 24. Therefore, the description is omitted.

As described above, the peripheral device selection unit 25 inputs the decode signal from the address decoding unit 21 according to the edge detection signal output by the change of the CS signal, and the peripheral device to be operated among the peripheral devices 13 to 15 is operated. By selecting, even if the address signal output from the CPU 11 changes asynchronously to the ASIC 12 for controlling the peripheral device, the malfunction caused by decoding the address signal in the indeterminate state can be prevented, and the peripheral devices 13 to 15 can be prevented. Can be accurately selected. Further, since the address strobe signal indicating the data determination of the address signal is not required, a power supply terminal and a ground terminal can be added to the CPU 11 and the peripheral device control ASIC 12, and the power supply and the ground are reinforced so that the reliability is high. A peripheral device control ASIC 12 can be provided.

Furthermore, when the peripheral devices 13 to 15 are replaced with peripheral devices having different access cycles, access timings, etc., the set value stored in the pulse width setting section 24 is changed so that the peripheral devices can be changed according to the replaced peripheral device. It is possible to output the WRB signal and the RDB signal.
Therefore, it is not necessary to redevelop the peripheral device control ASIC 12 due to changes in the specifications of the peripheral device, and the development cost can be reduced.

The semiconductor integrated circuit of the present invention is not limited to the above-mentioned illustrated examples, and it goes without saying that various modifications can be made without departing from the gist of the present invention. For example, the WRB signal and the RDB signal are CS
The pulse may be ended according to the end of the active state of the B1 to B3 signals. This allows the WRB signal and RDB
The signal pulse end register becomes unnecessary, and the number of register circuits installed in the pulse width setting unit 24 can be reduced.

Further, in the present embodiment, the case where the peripheral devices are three peripheral devices 13 to 15 has been described, but the case where the peripheral devices are three or more is also assumed. In that case, a plurality of CS signals (for example, C
S0 signal, CS1 signal, CS2 signal, CS3 signal, ...
() Is output and those CS signals are input to the address record unit 21 and the edge detection unit 22, so that a large number of peripheral devices can be easily controlled.

[0045]

According to the first aspect of the present invention, even when the predetermined data and the instruction signal are asynchronously input to the peripheral device control circuit, the clock signal output by detecting the rising or falling of the instruction signal. Since the peripheral device is selected based on the decode signal in synchronization with the detection signal synchronized with, the malfunction caused by decoding the predetermined data in the indeterminate state can be prevented and the peripheral device can be accurately selected. . Therefore, it is possible to cause the peripheral device to perform stable circuit operation.

Further, since it is not necessary to input an address strobe signal or the like indicating that the predetermined data has been determined, it is possible to add a power supply terminal or a ground terminal by reducing the input terminal, and reliability can be improved by reinforcing the power supply and the ground. It is possible to realize a high peripheral device control circuit.

According to the second and third aspects of the present invention, since the output timing of the control signal can be adjusted by changing the value stored in the storage section, the access cycle or access timing of the peripheral device is changed. Even in the case of being equalized, it is possible to deal flexibly. Further, it is not necessary to redesign the peripheral device control circuit due to changes in the specifications of the peripheral device, and it is possible to suppress development costs and the like.

According to the invention described in claim 4, the write enable signal and the write enable signal are not required to be redeveloped in accordance with the change of the specifications of the write cycle and the read cycle accompanying the replacement of the peripheral device. The output timing of the read enable signal can be adjusted.

According to the invention described in claim 5, by inputting the control signal output from the processor operating by the high-speed clock signal to the peripheral device control circuit according to any one of claims 1 to 4, A stable control signal synchronized with a clock signal for operating the peripheral device control circuit can be output to the peripheral device connected to the peripheral device control circuit. Therefore, it is possible to prevent malfunction of peripheral devices and provide an electronic circuit that performs stable circuit operation.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an electronic circuit for a CPU to control peripheral devices via an address bus and a data bus.

FIG. 2 is a block diagram showing an internal configuration of a peripheral device control ASIC.

FIG. 3 is a timing chart of a peripheral device control ASIC in a write mode.

FIG. 4 is a time chart of a write cycle and a read cycle of the CPU.

[Explanation of symbols]

11 CPU 12 ASIC for peripheral device control 21 Address decoding unit 22 Edge detector 23 Counter section 24 Pulse width setting section 25 Peripheral device selection section 251 Count value comparison unit 13, 14, 15 peripheral devices

Claims (5)

[Claims] 1. A peripheral device control circuit which is configured to allow external input of predetermined data, an instruction signal and a clock signal and which is connected to a plurality of peripheral devices, wherein the predetermined data is decoded to generate a decode signal. A decoding unit that outputs, an edge detection unit that detects a rising or falling of the instruction signal and outputs a detection signal that is synchronized with the clock signal, and the decoding signal and the detection signal are input, and the detection signal is input. Based on the decoded signal when
A peripheral device control circuit comprising: a selection unit that selectively selects a peripheral device from the plurality of peripheral devices. 2. The peripheral device control circuit according to claim 1, further comprising: a counter unit that receives the detection signal and starts a count operation based on the clock signal when the detection signal is input; A storage unit that stores the storage unit; and a comparison unit that compares the count value of the counter unit with the value stored in the storage unit, and when the comparison unit determines that the values are the same, A peripheral device control circuit, which outputs a control signal for performing predetermined control on a peripheral device selected by a selection unit. 3. The peripheral device control circuit according to claim 2, wherein the storage unit stores a first value and a second value, and the comparison unit stores the count value and the first value. comparison,
Further, the count value and the second value are compared with each other by comparing the count value and the second value, and after the comparison section determines that the count value and the first value are the same.
The peripheral device control circuit, which outputs the control signal until it is determined that the value of the same is the same. 4. The peripheral device control circuit according to claim 2, wherein the control signal is a write enable signal or a read enable signal. 5. The peripheral device control circuit according to claim 1, wherein the peripheral device control circuit is operated by a signal faster than the clock signal, and the predetermined data and the instruction signal are sent to the peripheral device control circuit. An electronic circuit comprising: a processor for outputting; and a plurality of peripheral devices connected to the peripheral device control circuit.