JP2005043952A - Microcomputer system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a microcomputer system for preventing command data with wrong level from being input to a CPU even if the level of the command data read out from a program memory is varied. <P>SOLUTION: A level variation detection part 5 detects level variations and continuously outputs a level variation detection signal until the level variations of the command data have converged, when the level of the command data read out from a program memory 4 is varied. A wait signal generation part 6 to which the detection signal is input therein outputs a /WAIT signal to a memory controller 3 until the level variations of the command data have converged. The controller 3 to which the /WAIT signal input therein inserts a wait period into a /RD signal for a program memory 4 until the level variations of the command data has converged. Whereby, a CPU 2 reads the command data after the conversion of the level variations. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a microcomputer system, and more particularly to a microcomputer system that controls the read cycle time of a program memory that stores instructions.
[0002]
[Prior art]
Calculations in the microcomputer are executed by reading out the instructions stored in the program memory and inputting them to the CPU.
[0003]
At this time, the data read from the program memory fluctuates due to the influence of signal reflection between terminals, noise such as power supply noise and electromagnetic noise, and is input to the CPU as an instruction different from the original instruction. May be.
[0004]
In this way, when an instruction different from the instruction to be executed is input to the CPU, the microcomputer malfunctions, and in some cases, the microcomputer may enter a runaway state. For this reason, the microcomputer is provided with a runaway detection circuit such as a watchdog timer. When the runaway detection circuit detects a runaway state, it interrupts the CPU or resets the system, and the microcomputer is in a normal state. Measures are being taken to return to.
[0005]
However, such a countermeasure using the runaway detection circuit has a problem that it takes time until the runaway is detected and the microcomputer continues to malfunction until the runaway is detected.
[0006]
Therefore, it is desired to detect that an incorrect command is input to the CPU before the CPU executes the command. For this purpose, for example, a circuit has been proposed in which an identification code is stored in the program memory separately from the original data, and by using this identification code, an incorrect instruction is prevented from being input to the CPU (for example, , See Patent Document 1).
[0007]
[Patent Document 1]
JP-A-5-233339 (page 2-3, FIG. 1)
[0008]
[Problems to be solved by the invention]
However, what can be prevented by the conventional circuit using the above-described identification code is a malfunction in which an operation code read pulse is erroneously generated in an operand cycle and an operand in the instruction is erroneously read as an operation code.
[0009]
Therefore, if the operation code read pulse is correctly generated in the operation code cycle, even if the instruction data read from the program memory has a level fluctuation affected by power supply noise or the like, the data whose level fluctuation has occurred is directly sent to the CPU. It was input as incorrect data, and the malfunction of the microcomputer could not be prevented.
[0010]
SUMMARY OF THE INVENTION An object of the present invention is to provide a microcomputer system in which an incorrect level of instruction data is not input to a CPU even when the level of instruction data read from a program memory varies.
[0011]
[Means for Solving the Problems]
According to one aspect of the present invention, a CPU, a program memory that stores an instruction to be given to the CPU, a memory controller that generates a read signal that controls reading of the instruction from the program memory, and a read from the program memory A level fluctuation detection unit for detecting a signal level fluctuation of the data of the issued command, and a wait period in the read signal output from the memory controller based on the level fluctuation detection signal output from the level fluctuation detection unit A wait signal generating section for generating a wait signal for providing the signal, and when there is a signal level fluctuation in the data of the instruction read from the program memory, the program memory until the signal level of the data of the instruction is stabilized Continue reading the data of the command from That the microcomputer system is provided.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0013]
(First embodiment)
FIG. 1 is a block diagram showing a configuration of a microcomputer system according to the first embodiment of the present invention.
[0014]
The microcomputer system of the present embodiment has a CPU 2 and a memory controller 3 mounted on an MCU chip 1 which is one semiconductor integrated circuit chip, and a program memory 4 which is a semiconductor integrated circuit chip different from the MCU chip 1. is doing. Further, as other components, a level fluctuation detecting unit 5, a wait signal generating unit 6, and a clock generator 7 are provided.
[0015]
Among these, the memory controller 3 outputs a read (/ RD) signal that controls reading of data from the program memory 4, and has a wait (/ WAIT) terminal as an input terminal. When a wait (/ WAIT) signal is given from the outside, a desired wait period can be given to the / RD signal.
[0016]
Next, the operation of the microcomputer system of this embodiment will be described. First, an operation of reading data from the program memory 4 and reading it as an instruction to the CPU 2 will be described, and then operations of the level fluctuation detection unit 5 and the wait signal generation unit 6 will be described.
[0017]
The program memory 4 stores an instruction to be given to the CPU 2. When a read signal (/ RD signal) output from the memory controller 3 is given to the program memory 4, the instruction stored in the program memory 4 is Read as instruction data consisting of a plurality of bits.
[0018]
The / RD signal in the memory controller 3 is generated based on the reference / RD signal given from the CPU 2. In the present embodiment, reading of instruction data from the program memory 4 is started when the / RD signal output from the memory controller 3 falls to the L level, and reading is performed while the / RD signal is at the L level. It is an enable period, and the output of instruction data from the program memory 4 continues. However, the instruction data is read into the CPU 2 at the rise of the / RD signal, that is, at the end of the read enable period, and the signal level of the instruction data at that time is read into the CPU 2.
[0019]
In this way, reading of instruction data from the program memory 4 starts at the falling edge of the / RD signal output from the memory controller 3 to the L level. Generally, when a switching operation is performed, a transient phenomenon occurs, and the program memory 4 The command data read out from the program does not always settle down to a stable signal level.
[0020]
In particular, when the reflection due to impedance mismatch between signal terminals or the fluctuation of the power supply potential due to so-called simultaneous switching in which a large number of signals change at the same time, the fluctuation of the signal level is large, and the signal level is reversed in some cases Larger levels of fluctuations can occur. In addition, it may take some time for the amplitude of the fluctuation to stabilize to a certain level or less.
[0021]
Such a change in the output level accompanying the switching operation often results in a damped oscillation having periodicity due to the time constant of the wiring length of the signal and the impedance of the wiring, but at the timing of the rise of the / RD signal, If the level fluctuation is not reduced below a certain level, it is read into the CPU 2 as an incorrect level signal. That is, an incorrect command is given to the CPU 2.
[0022]
Therefore, in the microcomputer system of the present embodiment, the level fluctuation detection unit 5 and the wait signal generation unit 6 are provided, and even if the signal level of the instruction data output from the program memory 4 varies, an erroneous level is sent to the CPU 2. Is prevented from being read as a signal.
[0023]
Among these, the level fluctuation detection unit 5 receives the instruction data output from the program memory 4, and when the instruction data has a signal level fluctuation that is large enough to be recognized as an inversion of the signal level, It is a circuit that detects and outputs a level fluctuation detection signal.
[0024]
The wait signal generation unit 6 receives the level variation detection signal output from the level variation detection unit 5 and generates a / WAIT signal to be input to the WAIT terminal of the memory controller 3.
[0025]
While the level fluctuation detection unit 5 and the wait signal generation unit 6 have such a large signal level fluctuation that the signal level is erroneously recognized in the command data output from the program memory 4, the WAIT of the memory controller 3. A / WAIT signal is applied to the terminal, and a wait period is inserted into the / RD signal output from the memory controller 3.
[0026]
Thereafter, when the fluctuation in the signal level of the instruction data falls within a certain value, the instruction level fluctuation detection signal is not output. That is, at this point, it can be considered that the signal level of the data is stable. As a result, the / WAIT signal is also not output, the provision of the wait period ends, and the / RD signal rises. Therefore, the instruction data after the fluctuation of the signal level is stabilized is read into the CPU 2.
[0027]
The wait signal generator 6 also receives the system clock signal CK and the reference / RD signal that are generated by the clock generator 7 and supplied to the CPU 2, and the reception start timing of the level fluctuation detection signal is determined by these signals. Have decided.
[0028]
Usually, the L level period of the reference / RD signal is generated in units of one cycle of the system clock signal CK, but it is necessary to determine whether or not the / WAIT signal is output because of the cycle of the / RD signal. Since the second half of the year. Therefore, the second half of the period of the reference / RD signal is cut out by the system clock signal CK, and if there is an output of the level fluctuation detection signal during this period, it is accepted.
[0029]
When the level fluctuation detection signal is output beyond the output period of the reference / RD signal, the / WAIT signal is output while the level fluctuation detection signal is being output.
[0030]
The wait signal generator 6 also receives an external / WAIT signal, but this signal is used for weight control in normal operation and is not used here.
[0031]
FIG. 2 is a circuit diagram showing an example of the circuit of the level fluctuation detector 5, and FIG. 3 is a circuit diagram showing an example of the circuit of the wait signal generator 6.
[0032]
In FIG. 2, inputs D1, D2,..., Dn represent data signals of respective bits of n-bit instruction data. Dn are input to one end of each of the EX-NOR gates 511, 512,.
[0033]
On the other hand, the other ends of the EX-NOR gates 511, 512,..., 51n are connected to the signals dD1, dD2 via the delay circuits 521, 522,. ,..., DDn is input.
[0034]
The outputs of the EX-NOR gates 511, 512,..., 51n are input to an n-input AND gate 53, and the output of the AND gate 53 is a level fluctuation detection signal.
[0035]
If there is a change in signal level at the inputs D1, D2,..., Dn, the inputs D1, D2,..., Dn and the signals dD1, dD2,. When viewed at a certain time, a difference in signal level occurs. When the difference in signal level is large, the EX-NOR gates 511, 512,..., 51n recognize that the input signal levels do not match, and the output becomes L.
[0036]
When any of the outputs of the EX-NOR gates 511, 512,..., 51n becomes L, the output of the AND gate 53 to which these outputs are inputted, that is, the level fluctuation detection signal becomes L.
[0037]
On the other hand, when the signal level fluctuations of the inputs D1, D2,..., Dn converge, the inputs D1, D2,..., Dn and the signals dD1, dD2,. .., 51n becomes H. The signal level difference does not occur between the EX-NOR gates 511, 512,. When all the outputs of the EX-NOR gates 511, 512,..., 51n become H, the output of the AND gate 53, that is, the level fluctuation detection signal becomes H.
[0038]
That is, when a signal level fluctuation occurs in any of the inputs D1, D2,..., Dn, the level fluctuation detection signal becomes L, but the signal level fluctuations of the inputs D1, D2,. When all converge, the level fluctuation detection signal becomes H.
[0039]
The delay time given to the delay circuits 521, 522,..., 52n is, if the period of fluctuation of the signal level of the inputs D1, D2,. It may be half, that is, about T / 2.
[0040]
FIG. 3 is an example of a circuit of the wait signal generation unit 6 that receives the level variation detection signal output from the circuit of FIG. 2 and outputs a / WAIT signal.
[0041]
In the circuit of FIG. 3, the level fluctuation detection signal and the / RD signal are input to the OR gate 67, and the level fluctuation detection signal is valid only during the period when the / RD signal is L. The output of the OR gate 67 is input to one end of each of the OR gate 61 and the OR gate 62. The outputs of the OR gate 61 and the OR gate 62 are input to the AND gate 65, the output of the AND gate 65 is input to one end of the AND gate 66, and the output of the AND gate 66 is the / WAIT signal.
[0042]
Here, the output of the OR gate 63 is input to the other end of the OR gate 61, and the output of the inverter 64 is input to the other end of the OR gate 62. Among these, the OR gate 63 receives the reference / RD signal and the system clock CK, and the inverter 64 receives the reference / RD signal. In addition, the external / WAIT signal is input to the other end of the AND gate 66. Here, it is assumed that an H level is input to the external / WAIT signal.
[0043]
Next, the operation of this circuit will be described.
[0044]
The OR gate 63 is a circuit that cuts out the latter half of the L level period of the reference / RD signal, and outputs a signal for starting reception of the level fluctuation detection signal. That is, when both the reference / RD signal and the system clock CK are L, the output of the OR gate 63 becomes L, and the L input of the level variation detection signal is passed to the output of the OR gate 61.
[0045]
When the output of the OR gate 61 is L, the output of the AND gate 65 is also L, and then the output of the AND gate 66 is also L, that is, the / WAIT signal is L.
[0046]
Thereafter, even if the reference / RD signal rises, if the L input of the level fluctuation detection signal continues, the OR gate 62 replaces the OR gate 61 with the L input of the level fluctuation detection signal. Works to transmit to the output. That is, when the reference / RD signal becomes H, the output of the OR gate 63 becomes H and the output of the OR gate 61 becomes H. Instead, the output of the inverter 64 becomes L and the level It serves to pass the L input of the fluctuation detection signal to the output of the OR gate 62.
[0047]
When the output of the OR gate 62 is L, the output of the AND gate 65 is L, the output of the AND gate 66 is also L, and the / WAIT signal is also L.
[0048]
On the other hand, when the level fluctuation detection signal is H, the outputs of the OR gate 61 and the OR gate 62 are both H, and the output of the AND gate 65 is H. When the output of the AND gate 65 is H, the output of the AND gate 66, that is, the / WAIT signal is also H.
[0049]
FIG. 4 is a waveform diagram when the microcomputer system of the present embodiment is operated using the example of the circuit of the level fluctuation detection unit 5 and the example of the circuit of the wait signal generation unit 6 described above.
[0050]
When the reference / RD signal generated for one cycle of the system clock CK is given in the t1 cycle, the / RD signal from the memory controller 3 is also output. Then, the instruction data D1, D2,..., Dn are read from the program memory 4.
[0051]
Now, if there is a level fluctuation in D1, D2,..., Dn, the level fluctuation is also delayed by the delay time in dD1, dD2,.
[0052]
When the level fluctuation detection unit 5 detects a mismatch in signal level between D1, D2,..., Dn and the levels of dD1, dD2,..., DDn, the level fluctuation detection signal is set to L.
[0053]
When the level variation detection signal L is input to the wait signal generation unit 6, the wait signal generation unit 6 outputs L to the / WAIT signal from the latter half of the L level period of the reference / RD signal.
[0054]
Even if the reference / RD signal rises at the t2 cycle, if the level fluctuation detection signal remains L, the wait signal generation unit 6 continues to set the / WAIT signal to L. Then, the memory controller 3 inserts a wait period for one cycle of the system clock CK into the / RD signal, and delays the rise of the / RD signal.
[0055]
The insertion of the wait period into the / RD signal continues while the level fluctuation detection signal is L.
[0056]
If the level fluctuation detection signal changes to H in the middle of the t3 cycle, the / WAIT signal also rises to H, and the insertion of the wait period into the / RD signal is also completed in this cycle.
[0057]
At the rising edge of the system clock CK in the t4 cycle, the / RD signal also rises, and the levels of D1, D2,..., Dn at this time are read into the CPU 2 as instruction data.
[0058]
As described above, in the microcomputer system according to the present embodiment, when the signal level of the instruction data read from the program memory 4 varies, a wait period is inserted into the / RD signal output from the memory controller 3. After the change in the signal level of the instruction data has converged, the / RD signal is raised. As a result, it is possible to prevent the CPU 2 from reading instruction data having an incorrect signal level.
[0059]
(Second Embodiment)
FIG. 5 is a block diagram showing a configuration of a microcomputer system according to the second embodiment of the present invention.
[0060]
The functions of the blocks constituting the microcomputer system in the present embodiment are the same as the blocks of the microcomputer system in the first embodiment. Accordingly, in FIG. 5, blocks having the same functions as those in the block diagram shown in FIG. 1 are denoted by the same reference numerals, and detailed description thereof is omitted here.
[0061]
The microcomputer system of the present embodiment is different from the microcomputer system of the first embodiment in that all the blocks constituting the system are mounted on one semiconductor integrated circuit chip.
[0062]
That is, in FIG. 5, the CPU 2, the memory controller 3, and the program memory 4 are mounted on the MCU chip 11, and further, the level variation detection unit 5 and the wait signal generation unit 6 are mounted.
[0063]
Thus, since the microcomputer system of the present embodiment is made of one semiconductor integrated circuit chip, the mounting area of equipment on which the microcomputer system is mounted can be reduced.
[0064]
(Third embodiment)
FIG. 6 is a block diagram showing a configuration of a microcomputer system according to the third embodiment of the present invention.
[0065]
The configuration of the microcomputer system in the present embodiment is also the same as the configuration of the microcomputer system in the first embodiment. The functions of the blocks constituting the system are also the same as the blocks of the microcomputer system in the first embodiment.
[0066]
Therefore, in FIG. 6, blocks having the same functions as those in the block diagram shown in FIG. 1 are denoted by the same reference numerals, and detailed description thereof is omitted here.
[0067]
The microcomputer system in the present embodiment is different from the microcomputer system in the first embodiment in that there is no output of the reference / RD signal from the MCU chip 21, and the weight signal generation unit 26 has the reference / RD signal. The point is that the / WAIT signal is generated without using.
[0068]
Therefore, here, the description will focus on the circuit configuration and operation of the wait signal generation unit 26.
[0069]
FIG. 7 is an example of a circuit of the wait signal generation unit 26 in the present embodiment.
[0070]
In the circuit of FIG. 7, the CK and / RD signals are input to the OR gate 261, and a window signal is generated. The window signal and the level fluctuation detection signal are input to the OR gate 263, and a level fluctuation trigger signal is generated.
[0071]
The level fluctuation trigger signal is inverted in level by the inverter 264 and input to the clock terminal (CK) of the D flip-flop 265 with preset. The / window signal obtained by inverting the window signal by the inverter 262 is input to the preset terminal (/ PR) of the D flip-flop 265, and the input terminal (D) is fixed at the L level.
[0072]
The output terminal (Q) of the D flip-flop 265 is connected to the input terminal (D) of the D flip-flop 266 with a preset.
[0073]
CK is input to the clock terminal (CK) of the D flip-flop 266, and a signal obtained by inverting the level of the / RD signal by the inverter 267 is input to the preset terminal (/ PR).
[0074]
The output of the D flip-flop 266 and the output of the D flip-flop 265 described above are input to the AND gate 268, the output of the AND gate 268 is input to one end of the AND gate 269, and the output of the AND gate 269 is the / WAIT signal. It has become.
[0075]
In addition, the external / WAIT signal is input to the other end of the AND gate 269. Here, it is assumed that the H level is input to the external / WAIT signal.
[0076]
Next, the operation of this circuit will be described with reference to the operation waveform diagram of FIG.
[0077]
FIG. 8 is an operation waveform diagram showing how the wait signal generator 26 operates in the present embodiment.
[0078]
The window signal is the period H when the / RD signal is H, but when the / RD signal falls to L during the period t1, the same waveform as that of CK is output.
[0079]
Here, if the level fluctuation detection signal is L throughout the t1 period and the t2 period, the same waveform as that of CK is also output to the level fluctuation trigger signal during this period. This level fluctuation trigger signal is inverted by the inverter 264 and becomes CK of the D flip-flop 265.
[0080]
Since the D flip-flop 265 is preset by the / window signal that is an inverted signal of the window signal, the output of the D flip-flop 265 is H when the / window signal is L.
[0081]
When the / window signal changes to H in the period t1, the preset of the D flip-flop 265 is canceled, and the L level of the D input is read by the level fluctuation trigger signal inverted by the inverter 264, and the D flip-flop 265 The output changes to L.
[0082]
When the / window signal changes to L in the period t2, the D flip-flop 265 is preset again, and the output of the D flip-flop 265 changes to H. Thereafter, when the / window signal changes to H, the preset of the D flip-flop 265 is canceled, the L level of the D input is read by the level fluctuation trigger signal inverted by the inverter 264, and the output of the D flip-flop 265 is L To change.
[0083]
When the / window signal changes to L in the period t3, the D flip-flop 265 is preset again, and the output of the D flip-flop 265 changes to H. Thereafter, when the / window signal changes to H, the preset is canceled. However, since the level fluctuation detection signal has changed to H in the period t3, the level fluctuation trigger signal is also fixed to H, and its inverted signal is fixed to L. Therefore, even if the preset is canceled, the D input is not read, and the output of the D flip-flop 265 remains H.
[0084]
On the other hand, since the D flip-flop 266 is preset with the inverted signal of the / RD signal, the output of the D flip-flop 266 is preset to H while the / RD signal is H.
[0085]
When the / RD signal changes to L in the period t1, the preset is canceled.
[0086]
When CK rises during the period t2, the D flip-flop 266 reads L of the output of the D flip-flop 265 connected to the D terminal, and the output of the D flip-flop 266 changes to L.
[0087]
When CK rises in the period t3, the D flip-flop 266 reads L of the output of the D flip-flop 265 again, and the output of the D flip-flop 266 continues to be L.
[0088]
When CK rises in the period t4, the D flip-flop 266 reads H of the output of the D flip-flop 265, and the output of the D flip-flop 266 changes to H.
[0089]
Since the external / WAIT signal is H, the / WAIT signal becomes the AND output itself of the output of the D flip-flop 265 and the output of the D flip-flop 266 by the AND gate 268. Therefore, when the output of the D flip-flop 265 becomes L in the period t1, the / WAIT signal changes to L, and L continues until the output of the D flip-flop 266 becomes H in the period t4.
[0090]
When the / WAIT signal is L, a wait period is given to the / RD signal, and the / RD signal continues to be L. That is, the / RD signal continues to be L until the end of the t4 period when the / WAIT signal changes to H.
[0091]
As described above, in the microcomputer system according to the present embodiment, the wait signal generation unit 26 is based on the / RD signal, the level fluctuation detection signal, and the system clock CK even if the MCU chip 21 does not output the reference / RD signal. Can generate a / WAIT signal.
[0092]
【The invention's effect】
According to the microcomputer system of the present invention, it is possible to prevent an incorrect level of instruction data from being input to the CPU even if the instruction data read from the program memory varies in level. As a result, it is possible to prevent a malfunction that occurs when an erroneous command is input to the CPU.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a microcomputer system according to a first embodiment of the present invention.
FIG. 2 is a circuit diagram showing an example of a circuit of a level fluctuation detection unit according to the embodiment of the present invention.
FIG. 3 is a circuit diagram showing an example of a circuit of a wait signal generation unit according to the first and second embodiments of the present invention.
FIG. 4 is an operation waveform diagram of the microcomputer system according to the first embodiment of the present invention.
FIG. 5 is a block diagram showing a configuration of a microcomputer system according to a second embodiment of the present invention.
FIG. 6 is a block diagram showing a configuration of a microcomputer system according to a third embodiment of the present invention.
FIG. 7 is a circuit diagram showing an example of a circuit of a wait signal generation unit according to the third embodiment of the present invention.
FIG. 8 is an operation waveform diagram of a wait signal generation unit according to a third embodiment of the present invention.
[Explanation of symbols]
1, 11, 21 MCU chip
2 CPU
3 Memory controller
4 Program memory
5 Level fluctuation detector
6, 26 Weight signal generator
7 Clock generator
511, 512,..., 51n EX-NOR gate
521, 522, ..., 52n Delay circuit
53, 65, 66, 268, 269 AND gate
61, 62, 63, 67, 261, 263 OR gate
64, 262, 264, 267 Inverter
265, 266 D flip-flop

Claims (6)

CPU,
A program memory for storing instructions to be given to the CPU;
A memory controller that generates a read signal that controls reading of the instruction from the program memory;
A level fluctuation detecting unit for detecting a signal level fluctuation of the data of the instruction read from the program memory;
A wait signal generation unit that generates a wait signal that gives a wait period to the read signal output from the memory controller based on the level variation detection signal output from the level variation detection unit;
When there is a signal level variation in the data of the instruction read from the program memory, reading of the data of the instruction from the program memory is continued until the signal level of the data of the instruction is stabilized. Microcomputer system. 2. The microcomputer system according to claim 1, wherein the reading of the instruction data into the CPU is performed when an enable period of the read signal ends. The level fluctuation detection unit detects that there is a signal level fluctuation in the command data by detecting a level mismatch between the command data and data obtained by delaying the command data by a predetermined time. The microcomputer system according to claim 1. The microcomputer system according to claim 1, wherein the wait signal generation unit starts generating the wait signal after the read signal is output from the memory controller. 5. The microcomputer system according to claim 1, wherein the CPU and the memory controller are mounted on a single semiconductor integrated circuit chip. 5. The CPU according to claim 1, wherein the CPU, the memory controller, the program memory, the level fluctuation detection unit, and the wait signal generation unit are mounted on one semiconductor integrated circuit chip. 2. The microcomputer system according to claim 1.

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