JP4620492B2 - Bus interface circuit - Google Patents

Description

  The present invention relates to a bus interface circuit, and more particularly to a bus interface circuit used in a microcomputer.

  In recent years, microcomputers (hereinafter referred to as microcomputers) have increased in operating speed in order to improve the computing capability of a CPU that is a computing unit. In general, a microcomputer has a macro circuit in which various functions such as control of peripheral devices and storage of operation instructions are blocked. When the macro circuit does not need to operate at a high speed, the macro circuit is operated at a low speed in order to reduce power consumption. The macro circuit and the CPU are generally connected via a data bus. The CPU reads various data from the macro circuit via this data bus. The CPU outputs a read clock and reads data from the macro circuit based on the read clock. At this time, if the macro circuit is operating asynchronously and is operating with a macro clock that is not related to the read clock, the read clock and the macro clock change at the same time, and a meta stable that causes data interference occurs. To do. In order to prevent this meta-stable, a bus interface circuit having an asynchronous arbitration function is required. A conventional bus interface circuit 500 having a meta / stable prevention function is shown in FIG. The bus interface circuit shown in FIG. 5 is a circuit that outputs macro data as read data at the first fall of the read clock.

  However, even with the bus interface circuit 500 shown in FIG. 5, the reading of the macro data of the CPU depends on the relationship between the macro clock and the read clock. FIG. 6 shows a timing chart when data reading is completed with a small number of clocks in the bus interface circuit 500 shown in FIG. In the example shown in FIG. 6, the macro clock rises after the first fall of the read clock and before the second fall. Data D0 before the first fall of the read clock is determined as read data after the macro clock rises. Therefore, at the second fall of the read clock, the data D0 is determined as read data. Therefore, the CPU can read the data D0 at the fall of the second read clock.

  FIG. 7 shows a timing chart when a large number of clocks are required for reading data in the bus interface circuit 500 shown in FIG. In the example shown in FIG. 7, the macro clock rises before the first fall of the read clock. Data D1 at the first fall of the read clock. The data D1 is determined as read data after the next macro clock rises. Therefore, until the next macro clock rises, the CPU cannot read the data D1 as read data unless it continues to output the read clock. Therefore, a long time is required for the CPU to read the read data.

  In the conventional bus interface circuit 500, the number of macro clocks required at that time differs depending on the relationship between the macro clock and the read clock. In the conventional bus interface circuit 500, in order for the CPU to read the macro data, the data access time for one cycle of the macro clock is required at the maximum. In this case, it is conceivable to shorten the data access time by increasing the speed of the macro clock, but this is not a realistic method due to the recent trend of lower power consumption.

  Patent Document 1 discloses a bus interface circuit having an asynchronous arbitration function. According to this bus interface circuit, asynchronous arbitration can be performed while preventing meta-stable.

However, even the bus interface circuit disclosed in Patent Document 1 cannot perform multi-bit asynchronous arbitration. When performing asynchronous adjustment of multi-bit macro data, it is necessary to determine the read data using a single-bit control signal. When the multi-bit is handled in the circuit disclosed in Patent Document 1, the data of each bit is controlled by a clock using a different wiring. That is, the read data is determined by the multi-bit clock signal. In this case, if the synchronization timing is shifted by the bit, the read data and the macro data become different data. That is, there is a problem that the CPU cannot read correct macro data.
JP-A-5-313783

  Conventionally, when handling multi-bit data between a CPU and a macro circuit, a large number of read clocks are required for the CPU to capture data.

  A bus interface circuit according to the present invention holds a macro clock synchronization data holding unit that holds macro data based on a macro clock of a macro circuit, and holds the macro data based on a read clock used at the time of reading the macro data. A read clock synchronization data holding unit; a read period determination unit that outputs a read period signal based on the read clock; a macro clock detection unit that outputs a data hold signal based on the read period signal and the macro clock; and the data A meta stable avoiding unit that outputs a meta stable avoiding signal based on the holding signal and the read clock; and an output of the macro clock synchronization data holding unit based on the meta stable avoiding signal or the read clock Output of synchronous data holding unit And a read data selector for outputting the read data by selecting or Re.

  In the present invention, the meta / stable avoiding unit generates the meta / stable avoiding signal based on the relationship between the macro clock and the read clock. Further, based on the meta stable avoidance signal, from the macro clock synchronization data holding unit that outputs the macro data synchronized with the macro clock or from the read clock synchronization data holding unit that outputs the macro data synchronized with the read clock. A read data selector that selects and outputs one of the inputs. As a result, the CPU can capture correct macro data with a small number of read clocks.

  According to the present invention, a bus interface circuit that outputs correct macro data with a small number of read clocks can be realized.

  Embodiment 1

  FIG. 1 is a block diagram of the bus interface circuit 100 according to the first embodiment of the present invention. The bus interface circuit 100 according to the first embodiment will be described with reference to FIG. The bus interface according to the first embodiment includes a macro clock synchronization data holding unit 101, a read clock synchronization data holding unit 102, a read period determination unit 103, a macro clock detection unit 104, a meta / stable avoidance unit 105, and a read data selector 106. is doing.

  The macro clock synchronization data holding unit 101 is a block that holds and outputs macro data input based on a macro clock and a data holding signal from a macro clock detection unit 104 described later. The read clock synchronization data holding unit 102 is a block that holds and outputs macro data based on the read clock. The read period determination unit 103 is a block that outputs a read period signal indicating that the bus interface circuit 100 is in a data read period and a retry signal that requests the CPU to output a read clock from the input read clock. . The macro clock detection unit 104 is a block that detects the rising edge of the macro clock during the read period from the read period signal and the macro clock and outputs a data holding signal. The meta / stable avoiding unit 105 is a block that outputs a meta / stable avoiding signal when the macro clock detecting unit 104 detects the rising edge of the macro clock during the read period. The read data selector 106 is a block that selects a signal from the macro clock synchronization data holding unit 101 and a signal from the read clock synchronization data holding unit 102 based on the meta / stable avoidance signal and outputs read data.

  FIG. 2 shows a circuit diagram of the bus interface circuit 100 according to the first embodiment. The internal circuit will be described for each block in the description of the block diagram with reference to FIG.

  The macro clock synchronization data holding unit 101 has an input selector 201 and a slave register 202. The input selector 201 has a first input terminal Y, a second input terminal N, and a selection signal input terminal. Based on the data holding signal, the input selector 201 selects one of the first input terminal Y and the second input terminal N. A circuit that selects and outputs input data. The slave register 202 has an input terminal D, a clock input terminal C, and an output terminal Q, and is a circuit that outputs data of the input terminal D to the output terminal Q when the macro clock rises.

  Macro data is input to the second input terminal N of the input selector 201, and the first input terminal Y is connected to the output terminal Q of the slave register 202. Further, a data holding signal for selecting the first input and the second input is input from the macro clock detection unit to the selection signal input terminal of the input selector 201. The output of the input selector 201 is connected to the input terminal D of the slave register 202. The macro clock is input to the input terminal C of the slave register 202, and the output terminal Q is connected to the first input terminal Y of the input selector 201 and the first input terminal Y of the read data selector 106.

  The read clock synchronization data holding unit 102 has a slave register 203. The slave register 203 has an input terminal D, an input terminal C, and an output terminal Q, and is a circuit that outputs data of the input terminal D to the output terminal Q when the read clock falls. Macro data is input to the input terminal D, and a read clock is input to the input terminal C. The output terminal Q is connected to the second input terminal N of the selector.

  The read period determination unit 103 includes an inverter 204, a retry register 205, a read period register 206, and an OR circuit 207. The inverter 204 has an input terminal and an output terminal, and is a circuit that outputs an output obtained by inverting the input from the input terminal. The retry register 205 has an input terminal D, an input terminal C, and an output terminal Q, and is a circuit that outputs data of the input terminal D to the output terminal Q when the read clock rises. The read period register 206 has an input terminal D, an input terminal C, and an output terminal Q, and is a circuit that outputs data of the input terminal D to the output terminal Q when the read clock falls. The OR circuit 207 has a first input terminal, a second input terminal, and an output terminal. The OR circuit 207 outputs a Low level when both the input to the first input terminal and the second input terminal are at a Low level (for example, ground potential), and otherwise, a High level (for example, the ground level) (Power supply potential).

  The retry register 205 has an output terminal Q connected to an input terminal D via an inverter 204, and a read clock is input to the input terminal C. The retry register outputs a retry signal from the output terminal Q. The read period register 206 has an input terminal D connected to the output terminal Q of the retry register 205, and a read clock is input to the input terminal C. The first input terminal of the OR circuit 207 is connected to the output terminal Q of the retry register 205, and the second input terminal is connected to the output terminal Q of the read period register 206. The output terminal of the OR circuit 207 is the output of the read period determination unit 103, and a read period signal is output.

  The macro clock detection unit 104 has a clock detection register 208. The clock detection register 208 has an input terminal D, an input terminal C, an output terminal Q, and a reset terminal R, and is a circuit that outputs data of the input terminal D to the output terminal Q when the macro clock rises. Also, whenever a low level signal is input to the reset terminal, the output terminal outputs a low level. The input terminal D is connected to the power supply potential Vdd, and a macro clock is input to the input terminal C. The output terminal Q is an output of the macro clock detection unit 104, and a data holding signal is output.

  The meta stable avoiding unit 105 has a meta detection register 209. The meta detection register 209 has an input terminal D, an input terminal C, an output terminal Q, and a reset terminal R, and is a circuit that outputs data of the input terminal D to the output terminal Q when the read clock rises. Further, whenever a low level signal is input to the reset terminal, the output terminal outputs a low level. The output terminal Q of the macro clock detection unit 104 is connected to the input terminal D, and a read lock is input to the input terminal C. The output terminal Q is an output of the meta / stable avoiding unit 105, and outputs a meta / stable avoiding signal.

  The read data selector 106 has a first input terminal Y, a second input terminal N, an output terminal, and a selection signal input terminal. The output of the read clock synchronization data holding unit 101 is connected to the first input terminal Y of the selector, and the output of the macro clock data holding unit 102 is connected to the second input terminal N. Further, the output of the meta / stable avoiding unit 105 is connected to the selection signal input terminal. The output terminal of the read data selector 106 is the output of the bus interface circuit 100. Based on the meta / stable avoidance signal, either the output of the macro clock synchronization data holding unit 101 or the output of the read clock synchronization data holding unit 102 is selected. Select or to output read data.

  FIG. 3 shows a flowchart of the operation of the bus interface circuit 100 according to the first exemplary embodiment. The operation of the bus interface circuit 100 according to the first embodiment will be described with reference to FIG.

  First, a read clock is output from the CPU (301). The data read by the CPU is macro data output from the macro circuit at the first rise of the read clock. The CPU outputs a read clock only during a data reading operation.

  Next, based on the read clock, the read period determination unit 103 outputs a read period signal and a retry signal (302). In response to this read period signal, the bus interface circuit 100 performs a determination operation of read data to be output. The read period signal is stopped by the second fall of the read clock. As a result, the bus interface circuit 100 stops the read data determination operation. The CPU outputs the next clock in response to the retry signal. The retry signal stops at the rise of the second read clock. As a result, no further rise of the read clock is transmitted to the bus interface circuit 100.

  Next, the macro clock detection unit 104 determines whether or not the macro clock rises between the first rise of the read clock and the second rise (macro clock detection period) (303).

  When the macro clock rises during the macro clock detection period, the macro clock detection unit 104 outputs a data holding signal. The meta / stable avoiding unit 105 outputs a meta / stable avoiding signal based on the data holding signal and the read clock (304). In response to the meta / stable avoidance signal, the read data selector 106 outputs the signal from the macro clock synchronization data holding unit 101 as read data (305).

  In addition, when the macro clock does not rise during the macro clock detection period, the macro clock detection unit 104 does not output a data holding signal. Therefore, the meta / stable avoiding unit 105 does not output the meta / stable avoiding signal (306). As a result, the load data selector 106 outputs the signal from the read clock synchronization data holding unit 102 as read data (307).

  In general, a signal used in the microcomputer is designed so that the read clock is supplied to all the circuits of the microcomputer without delay while the read data is transmitted to the CPU with a delay. By designing in this way, when the CPU reads data at the second fall of the read clock, the read data determined reliably is transmitted to the CPU.

  By the above-described operation, the determined read data is transmitted to the CPU with a delay. The CPU reads the delayed read data at the second fall of the read clock (308).

  FIG. 4 shows a timing chart of the operation of the bus interface circuit 100 according to the first exemplary embodiment. Here, the operation of the bus interface circuit 100 according to the first embodiment can be divided into two cases, with and without the rise of the macro clock between the two rises of the read clock. Therefore, the timing chart shown in FIG. 4 will be described below in comparison with the above-described operation flowchart in two cases.

  Here, the macro data is a signal that changes when the macro clock rises. The macro data is D0 at the first rise of the read clock. However, the macro data at the second fall of the read clock (CPU data capture timing) is D1 different from D0. At this time, the bus interface circuit 100 is intended to transmit the macro data D0 as read data to the CPU.

  First, a case where the macro clock rises during the macro clock detection period will be described. This is an operation between timings T1 and T5 in the timing chart of FIG.

  The operation of the flowchart 301 is performed at timing T1. At timing T1, a read clock is transmitted from the CPU to the bus interface circuit 100. Based on this read clock, the operation of the flowchart 302 is performed at timing T1. At timing T1, based on the read clock, the read period signal of the read period determination unit 103 becomes High level. At this time, the retry signal of the read period determination unit 103 becomes High level.

  The read clock falls at timing T2. At this time, the read clock synchronization data holding unit 102 takes in and holds the macro data D0. At this time, the low level is input from the meta / stable avoiding unit 105 as the input selection signal of the read data selector 106. Therefore, the read data is the macro data D0 held by the read clock synchronization data holding unit 102.

  The operation of the flowchart 303 is performed at timing T3. Timing T3 is the rise timing of the macro clock. At this time, the data holding signal of the macro clock detection unit 104 becomes High level.

  Further, based on the rising edge of the macro clock at timing T3, the macro clock synchronization data holding unit 101 holds macro data D0 before timing T3. The macro clock synchronization data holding unit 101 holds the data taken in at the rising edge of the macro clock until the data holding signal is at a high level and the rising edge of the macro clock after taking in the macro data. .

  The operation of the flowchart 304 is performed at timing T4. At timing T4, the meta / stable avoidance signal of the meta / stable avoiding unit 105 becomes High level from the rise of the data holding signal and the read clock described above.

  By the operation of the meta / stable avoiding unit 105, the operation of the flowchart 305 is also performed at the timing T4. Since the meta stable avoidance signal is at a high level, the read data selector 106 outputs the macro data D0 of the macro clock synchronization data holding unit 101 as read data. Thereby, the macro data to be taken in by the CPU is determined.

  In addition, the retry signal becomes low level at timing T4. As a result, the CPU does not output any more rising edge of the read clock.

  The read data determined at timing T4 is transmitted to the CPU with a delay. The operation of the flowchart 308 is performed at timing T5, and the read data is captured by the CPU. That is, since the read data is transmitted to the CPU with a delay, even if the read data changes immediately after the timing T5, the read data captured by the CPU is the read data before the timing T5. Therefore, the CPU completes the data capture without causing meta-stable.

  Further, the read period signal becomes low level at timing T5. As a result, the bus interface circuit 100 stops the operation of selecting and confirming the read data.

  Next, a case where the macro clock does not rise during the macro clock detection period will be described. This is an operation between timings T6 and T9 in the timing chart of FIG.

  The macro data is D2 at the first rise of the read clock. The macro data at the second fall of the read clock (CPU data fetch timing) is also D2. At this time, the bus interface circuit 100 is intended to transmit the macro data D2 as read data to the CPU.

  The operation of the flowchart 301 is performed at timing T6. At timing T6, a read clock is transmitted from the CPU to the bus interface circuit 100. Based on this read clock, the operation of the flowchart 302 is performed at timing T6. At timing T6, based on the read clock, the read period signal of the read period determination unit 103 becomes High level. At this time, the retry signal of the read period determination unit 103 becomes High level.

  The read clock falls at timing T7. At this time, the read clock synchronization data holding unit 102 takes in and holds the macro data D0. At this time, the low level is input from the meta / stable avoiding unit 105 as the input selection signal of the read data selector 106. Therefore, the read data is the macro data D0 held by the read clock synchronization data holding unit 102.

  The operation of the flowchart 303 is performed between timings T6 and T8. However, since the macro clock does not rise during this period, the data holding signal of the macro clock detection unit 104 maintains the low level between the timings T6 and T8.

  Between the timings T6 and T8, since the macro clock does not rise, the macro data maintains D2. Therefore, the macro clock synchronization data holding unit 101 holds the macro data D2. Also. Although there is a fall of the read clock between the timings T6 and T8, since the macro data maintains D2, the read clock synchronization data holding unit 102 holds the macro data D2.

  The operation of the flowchart 306 is performed at timing T4. At timing T8, the meta / stable avoidance signal of the meta / stable avoiding unit 105 maintains the low level from the rise of the data holding signal and the read clock described above.

  By the operation of the meta / stable avoiding unit 105, the operation of the flowchart 305 is also performed at the timing T8. Since the meta stable avoidance signal is at the low level, the read data selector 106 outputs the macro data D2 of the read clock synchronization data holding unit 102 as read data.

  With the above operation, macro data to be captured by the CPU is determined. The read data determined at timing T8 is transmitted to the CPU with a delay. The operation of the flowchart 308 is performed at timing T9, and the read data is captured by the CPU. That is, since the read data is transmitted to the CPU with a delay, even if the read data changes immediately after the timing T9, the read data captured by the CPU is the read data before the timing T9. Therefore, the CPU completes the data capture without causing meta-stable.

  Further, at timing T9, the read period signal becomes low level. As a result, the bus interface circuit 100 stops the operation of selecting and confirming the read data.

  With the above-described operation, the bus interface circuit 100 can capture the macro data of the macro circuit into the CPU with the two-cycle read clock regardless of the relationship between the macro clock and the read clock. As a result, even if the speed difference between the macro clock and the read clock increases, a wasteful read clock is not required when the CPU takes in the macro data. That is, since the CPU can process the macro data without delay, the performance of the entire microcomputer is improved.

  Further, since the meta stable when the CPU captures macro data does not occur, the timing design between the CPU and the macro circuit becomes easy. This increases the degree of freedom in designing the macro circuit, and it is possible to reduce the speed of the macro clock that has conventionally been increased more than necessary in consideration of the performance of the entire system. That is, it is possible to reduce power consumption by reducing the macro clock speed.

  The bus interface circuit 100 according to the first embodiment receives multi-bit macro data, and uses a single-bit meta stable avoidance signal when the multi-bit data is determined as read data. That is, the bus interface circuit 100 can be said to be an asynchronous arbitration circuit that supports multi-bit data.

  According to the present invention, reading can be completed with a small number of read clocks, and a bus interface circuit having a meta-stable avoidance function compatible with multi-bits can be realized.

  Further, the present invention is not limited to the above embodiment, and can be modified as appropriate. The present invention only needs to have means for generating a meta / stable avoidance signal from the relationship between the macro clock and the read clock, and outputting any data of the plurality of data holding units. For example, it may be configured with logic reversed from the above embodiment.

1 is a block diagram of a bus interface circuit according to a first exemplary embodiment; 1 is a circuit diagram of a bus interface circuit according to a first exemplary embodiment; FIG. 3 is a diagram showing a flowchart of the operation of the bus interface circuit according to the first exemplary embodiment. FIG. 6 is a timing chart of the operation of the bus interface circuit according to the first exemplary embodiment. It is a figure which shows the circuit diagram of the conventional bus interface circuit. It is a figure which shows a timing chart in case macro data can be read with few read clocks in the conventional bus interface circuit. It is a figure which shows a timing chart in case many read clocks are required in order to read macro data in the conventional bus interface circuit.

Explanation of symbols

101 Macro clock synchronization data holding unit 102 Read clock synchronization data holding unit 103 Read period determining unit 104 Macro clock detecting unit 105 Meta / stable avoiding unit 106 Read data selector 201 Input selector 202 Slave register 203 Slave register 204 Inverter 205 Retry register 206 Read period register 207 OR circuit 208 Clock detection register 209 Meta detection register 501 Macro clock synchronization data holding unit 502 Read period control unit

Claims (5)

A macro clock synchronization data holding unit for holding macro data based on the macro clock of the macro circuit;
A read clock synchronization data holding unit that holds the macro data based on a read clock used during the macro data reading operation;
A read period determination unit that outputs a read period signal indicating a read period based on the read clock;
A macro clock detector that detects the presence or absence of a level change of the macro clock that changes the macro data and outputs a data holding signal in a period in which the read period signal indicates the read period ;
A meta / stable avoiding unit that outputs a meta / stable avoiding signal according to the read clock when the data holding signal indicates that the macro clock has changed in level ;
And read data selector for outputting macro data held on one of the macro clock synchronous data holding unit and the read clock synchronous data holding unit on the basis of the meta-stable avoidance signal as read data,
A bus interface circuit.   2. The bus interface circuit according to claim 1, wherein the macro data input at the time of the macro data reading operation and at the first switching of the read clock is output as the read data.   The meta / stable avoiding unit outputs a meta / stable avoiding signal when a macro clock is switched between a first switching and a third switching of the read clock. 3. A bus interface circuit according to 2.   4. The macro clock synchronization data holding unit can select one of data update and data maintenance when a macro clock is input based on the data holding signal. The bus interface circuit according to claim 1.   The operation of selecting one of the output of the macro clock synchronization data holding unit and the read clock synchronization data holding unit is not performed when the read period determination unit does not determine as the read period. Item 5. The bus interface circuit according to any one of Items 1 to 4.

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