JPH02115963A - Pre-charge time control circuit - Google Patents

Abstract

PURPOSE:To always secure pre-charge time even when a microprocessor is changed, to eliminate the fault of malfunction due to misprogramming, and to accelerate the operating speed of a work station, etc., by making the control of the pre-charge time into hardware. CONSTITUTION:After a specific input/output address decoder circuit 21 detects a specific input/output instruction, a minimum cycle time signal is outputted from a minimum cycle time signal generation circuit 22 during a period set at a pre-chage time setting circuit 20. A pre-charge time securing sense circuit 23 decodes the status and the address of the microprocessor, and generates a pre-charge signal when the minimum cycle time signal is turned on. An input/ output command A outputted from a microprocessor circuit is delayed by a standby request signal from a standby generation circuit 24, and an input/output command signal B is outputted from an OR circuit 26, thereby, prescribed pre- charge time can be secured.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a precharge time control circuit between commands in a general-purpose LSI. The present invention relates to a precharge time control circuit that ensures a precharge time control circuit.

[Conventional technology]

Conventionally, the precharge time (read/write recovery time) control circuit of this type of workstation, etc., inserts a jump instruction by a program and preloads when accessing continuous input/output (10) of a general-purpose LSI that requires a precharge time. It was designed to ensure charging time. Furthermore, in the case shown in FIG. 3, the input/output command A is generated by the command generation circuit 11 that decodes the status from the microprocessor using the system clock, but the general-purpose LSI 1, which requires precharge time, is accessed continuously. In this case, the program executes a jump instruction and extends the precharge time as time 12 in FIG. 4 to secure the precharge time.

[Problem to be solved by the invention]

Securing the precharge time in the conventional workstations mentioned above is controlled by jump instructions in the program, so the number of jump instructions to be inserted must be considered each time the microcomputer is changed, and the number of jump instructions to be inserted must be considered every time the microcomputer is changed. This method has disadvantages in that failures due to insufficient precharge time are likely to occur, and the operation speed of workstations and the like is slowed down due to unnecessary jump commands.

[Means to solve the problem]

The precharge time control circuit of the present invention is used in a device that controls access to an LSI in which the minimum cycle time for issuing an input/output instruction from a microprocessor is defined by the precharge time. specific input/output address decoding means for decoding and detecting;
Minimum cycle time signal generation means for generating a minimum cycle time specified time signal at the time of detection, precharge time securing sense means for determining the necessity of securing precharge time for a general-purpose LSI, and securing the precharge time are required. It has a command delay generating means for delaying LSI access by an input/output command when it is determined that the input/output command is executed, and a waiting generating means for requesting a predetermined waiting time from the microprocessor, and the specified minimum cycle time is determined by the request from the microprocessor. It is configured to be variable depending on the command.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, and FIG. 2 is a timing chart diagram of the embodiment shown in FIG.

This embodiment includes a precharge time setting circuit 20 that can set a predetermined minimum cycle time by a microprocessor, and a specific input/output address decoder that decodes and detects the input/output address of the LSI set in the precharge time setting circuit 2. Circuit 21 and precharge time setting circuit 20
A minimum cycle time signal generation circuit 22 that outputs a minimum cycle time signal having information that the time set in
A precharge time securing sense circuit 23 outputs a precharge signal when there is a request for input/output access when the minimum cycle time is valid, and a wait circuit 23 outputs a wait (WAIT) request signal to the microprocessor when the precharge signal is valid. Consisting of a request generation circuit 24, a command delay generation circuit 25 that outputs a signal requesting delay of input/output access when the precharge signal is valid, and an input/output access signal synthesis circuit (OR circuit) 26 that generates an input/output command signal. be done.

Next, the operation timing of this embodiment will be explained using FIG. 2.

The specific input/output address decoding circuit 21 decodes the status and address during period 30 and detects a specific input/output command. During the period set by the post-detection precharge time setting circuit 20, the minimum cycle time signal is output from the minimum cycle time signal generation circuit 22. The precharge time securing sense circuit 23 decodes the status and address of the microprocessor during the period 31 and selects a specific IO.
When the minimum cycle time signal is on when an instruction is detected, a precharge signal is generated. When the precharge signal is valid, the command delay request signal 32 and the wait request signal 33
and generate. The input/output command output from the microprocessor circuit is delayed by this wait request signal, and the output of the OR circuit 26, that is, the input/output command signal becomes as shown in the IO command signal B in FIG. On the other hand, when this circuit does not operate, the IO command signal is as the input/output command signal A shown in FIG.

Therefore, while the precharge time is time 50 when this circuit is not operating, it is extended to time 51 when it is operating, thereby ensuring a predetermined precharge time.

〔Effect of the invention〕

As explained above, by implementing precharge time control in hardware, the present invention ensures the precharge time even if the microprocessor is changed, eliminates troubles caused by malfunctions caused by program errors, and makes it easier for workstations, etc. This has the effect of increasing the operating speed.

. . . Command delay generation circuit, 26 . . . Input/output access signal synthesis circuit, 11 . . . Command generation circuit.

Claims (1)

[Claims] A specific input/output address decoding means for decoding and detecting an input/output instruction to a specific LSI in a device for controlling access to an LSI in which the minimum cycle time for issuing an input/output instruction from a microprocessor is defined by a precharge time. a minimum cycle time signal generating means for generating a minimum cycle time specified time signal at the time of detection; a precharge time securing sense means for determining the necessity of securing a precharge time for a general-purpose LSI; and a means for securing a precharge time for the general-purpose LSI; It has a command delay generating means for delaying LSI access by an input/output command when it is determined that the input/output command is the same, and a waiting generating means for requesting a predetermined waiting time from the microprocessor. A precharge time control circuit characterized in that the precharge time control circuit is variable according to a command from the precharge time control circuit.