JP2001084142A - Microprocessor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To attain a debug work in a real time by performing access from a bus master other than a microprocessor to a bus exclusive for data access without temporarily stopping the microprocessor. SOLUTION: This microprocessor is provided with a Harvard bus architecture and a bus line mechanism, and it is judged that an instruction in a pipe line stage in which data access is performed and a preceding pipe line stage is not any instruction for preventing data access by a pipe line controller 2, and it is predicted that a bus 5 is not used for the following instructions, and the bus 5 is related during that period.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprocessor (MPU) for accessing a bus dedicated to data access only by a load instruction or a store instruction for data transfer, and is particularly used for a debug support device. Microprocessor.

[0002]

2. Description of the Related Art Conventionally, as this type of MPU, for example, one employing a Harvard architecture as shown in FIG. 3 is known. In FIG. 3, the MPU 10
1 accesses the data memory 103 only through a data transfer load (Load) instruction or a store (Store) instruction via a data access dedicated bus 102, and accesses an instruction memory 105 via an instruction fetch dedicated bus 104. I do. Further, the MPU 101 adopts a five-stage pipeline structure of an instruction fetch (F) stage, a decode (D) stage, an execution (E) stage, a memory access (M) stage, and a write back (W) stage. Access to the data access bus 102 is performed at the M stage.

In such a system, the MPU 10
DMAC (direct memory access controller), DSU (debug support unit) that can take the right to use the bus 102 exclusively for data access other than 1
When the bus master such as obtains the right to use the bus 102 dedicated to data access, the MPU 101
A bus request is issued to the MPU 101
Bus 102 is released, the bus master acquires the right to use the bus 102, and the released bus 10
2 was used by the bus master. Thus, the bus 102
The operation of the MPU 101 has been temporarily stopped (stalled) in a state where the use right of the MPU 101 has been released to other than the MPU 101. For this reason, when the MPU 101 is used in the debug support device, the operation of the MPU 101 is stopped in a state where the bus 102 is released during the debugging work, so that the real-time debugging is impaired.

[0004]

As described above,
In a conventional microprocessor employing the Harvard architecture, the MPU is in a suspended state when the right to use a bus dedicated to data access is released to another bus master other than the MPU. For this reason, when a semiconductor device is debugged using this MPU, the MPU is temporarily stopped when a bus dedicated to data access is released during a debugging operation, which causes a problem that real-time debugging is impaired. I was

The present invention has been made in view of the above, and an object of the present invention is to allow a bus master other than a microprocessor to access a dedicated bus for data access without suspending the microprocessor. It is an object of the present invention to provide a microprocessor capable of real-time debugging.

[0006]

In order to achieve the above object, a first means for solving the problem is to provide a pipeline mechanism including a plurality of pipeline stages including a memory access stage for performing data access, In a microprocessor employing an architecture in which an access is made to a data memory via a bus dedicated to data access, and this access is performed only in the memory access stage and is not performed by an instruction other than a data transfer instruction, An instruction decoder that determines the data transfer instruction from the decoded instructions and generates a determination signal, and receives a determination signal generated by the instruction decoder, and performs data access from a stage where the data transfer instruction is decoded. Holds the judgment signal until the memory access stage and holds A pipeline controller that outputs a determination signal corresponding to each of the stages, and receives a determination signal output from the pipeline controller, and corresponds to a stage preceding the memory access stage from a stage where no determination signal is detected. A bus switching control circuit for outputting the bus switching signal until the discrimination signal output from the bus switching control circuit is detected, and receiving the switching signal output from the bus switching control circuit, the switching signal is output. And a bus switching circuit for releasing the right to use the bus.

[0007] The second means is the first means,
The bus switching signal, the discrimination signal output corresponding to the stage preceding the memory access stage after detecting that each discrimination signal output corresponding to the stage is not the data transfer instruction, the The signal is output to the bus switching circuit until a data transfer instruction is detected.

[0008] The third means is the second means,
The bus switching circuit receives a switching signal output from the bus switching control circuit, and releases the right to use the bus while the signal is being output.

[0009]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing a configuration of a microprocessor according to an embodiment of the present invention, and FIG. 2 is a diagram showing operation timings of the microprocessor shown in FIG.
In FIG. 1, the microprocessor of this embodiment employs the Harvard architecture described above, processes instructions by five pipeline stages as described above, and stores an instruction decoder 1, a pipeline controller 2, a bus switch. It comprises a control circuit 3 and a bus switching circuit 4.

In the D stage, the instruction decoder 1
In response to the instruction code given from the pipeline controller 2, the instruction is decoded, and it is determined from the decoding result that the instruction is a load instruction or a store instruction (data transfer instruction), and a load / store instruction determination signal is generated to generate a load / store instruction determination signal. This is given to the line controller 2.

The pipeline controller 2 controls the operation of the pipeline in the instruction processing, and outputs a load / store instruction discrimination signal supplied from the instruction decoder 1 to a D / D.
It is held corresponding to each pipeline stage of the stage (signal A), the E stage (signal B), and the M stage (signal C). The held load / store instruction determination signals (signal A, signal B, and signal C) are given to the bus switching control circuit 3.

The bus switching control circuit 3 receives a load / store instruction discrimination signal for each of the D / E / M pipeline stages given from the pipeline controller 2 and switches the buses from these signals A, B and C. This is a circuit that generates a signal (signal D). The bus switching signal (signal D) is such that the load / store instruction determination signals (signal A, signal B, signal C) of each of the D stage, E stage, and M stage are not load instructions or store instructions (for example, low level). ), And outputs a high-level bus switching signal, for example. After detection, the MPU (not shown) does not use the bus 5 for a period of two clocks. On the other hand, MPU
To return the right to use the bus 5 to E,
When there is a load instruction or a store instruction in the stage, that is, in the E stage, it is detected that the load / store instruction discrimination signal (signal B) is at a high level.
If it is a load / store instruction, load / storage to the next M stage
Since there is a re instruction, the bus 5 is set to M for data access.
The bus 5 must be returned to the MPU because it is used by the PU.

The bus switching control circuit 3 performs such control by, for example, as shown in FIG. 1, an AND gate 31 which receives inverted signals of signals A, B and C as inputs.
And the output of the AND gate 31 as a set (S) input,
An RS flip-flop 32 having a signal B as a reset (R) input, and a D flip-flop 33 having an output (Q) of the RS flip-flop 32 as an input (D) and an output (Q) as a bus switching signal are provided. ing.

The bus switching circuit 4 connects the bus 5 dedicated to data access to the MPU or the DPU in accordance with a bus switching signal (signal D) given from the bus switching control circuit 3.
When a high-level bus control switching signal is given from the bus switching control circuit 3, the bus 5 and the external bus master 6 are connected.

In such a configuration, as shown in the operation timing chart of FIG. 2, for example, instruction 5 (load instruction or store instruction) to instruction 4 (instruction other than load instruction or store instruction), instruction 3 (load instruction or store instruction). When the pipeline processing is performed in the order of the instruction other than the store instruction, the instruction 2 (the instruction other than the load instruction or the store instruction), and the instruction 1 (the load instruction or the store instruction), the instruction 5 is decoded and the load instruction or the instruction is decoded. When it is determined that the instruction is a store instruction, the determination signal is held as a signal A, a signal B, and a signal C by the pipeline controller 2 corresponding to the D stage, the E stage, and the M stage. The access to the bus 5 by the instruction 5 is completed, and the bus switching control circuit 3
, It is detected that the discrimination signal (signal A, signal B, signal C) of each of the D, E, M stages is not a load instruction or a store instruction (low level). After the detection, the MPU does not use the bus 5 for a period of two clocks. Therefore, a high-level bus switching signal (signal D) is output from the bus switching control circuit 3 to the bus switching circuit 4, and the bus 5 is switched. The external bus master 6 and the bus 5 are connected via the circuit 4, and the right to use the bus 5 is released to the external bus master 6 during this period.

After such a state, when the discrimination signal corresponding to the instruction 1 comes to the E stage, the MPU uses the bus 5 to execute the instruction 1 in the next M stage. Is returned to the MPU. That is, M
When the discrimination signal (signal B) goes high in the E stage preceding the stage, it is detected at the falling edge of the clock (signal X), whereby the bus switching signal (signal D) goes low and the bus 5 is switched. The bus 5 and the MPU are connected via the bus switching circuit 4.

As described above, in the above embodiment, D
After discriminating the Load instruction or the store instruction in the stage, by flowing this information together in the pipeline, it is determined that there is no load instruction or the store instruction in the D stage and the E stage, and the subsequent two instructions are the load instruction and the store instruction. It is expected that the MPU will not access the bus 5 exclusively for data access by the current M-stage instruction and the two instructions before the M-stage, that is, two instructions. Bus 5 is released to the external bus master 6, and since the released bus 5 has at least one bus cycle, the external bus master 6 other than the MPU does not temporarily stop the MPU in this empty cycle.
Can be used to read / write the memory. Therefore, even when a debugging operation is performed using this MPU, the debugging operation can be performed in real time.

[0019]

As described above, according to the present invention, the load instruction or the store instruction is predicted in the pipeline stage before data access, thereby enabling the MP instruction.
It is possible to detect the timing at which U does not occupy the bus dedicated to data access. Therefore, the bus dedicated to data access is connected to the MPU without suspending the MPU.
It can be released to bus masters other than U. Thus, a debugging operation can be performed in real time using this MPU.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a microprocessor according to an embodiment of the present invention.

FIG. 2 is a diagram showing operation timings of the microprocessor shown in FIG.

FIG. 3 shows a conventional M employing a Harvard architecture.
It is a figure showing the system configuration of PU.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Instruction decoder 2 Pipeline controller 3 Bus switching control circuit 4 Bus switching circuit 5 Bus dedicated to data access 6 External bus master 31 AND gate 32, 33 flip-flop

Claims (3)

[Claims] 1. A data processing system comprising a pipeline mechanism including a plurality of pipeline stages including a memory access stage for performing data access, and performing access with a data memory via a bus dedicated to data access. An instruction decoder for determining a data transfer instruction from decoded instructions and generating a determination signal in a microprocessor employing an architecture that is performed only in a memory access stage and is not performed by an instruction other than a data transfer instruction. Receiving the determination signal generated by the instruction decoder, holding the determination signal from a stage where the data transfer instruction is decoded to a memory access stage where data access is performed; Pipeline controller that outputs a discrimination signal in response Roller, receiving a determination signal output from the pipeline controller, detecting that each determination signal output corresponding to the stage is not the data transfer instruction, and corresponding to a stage preceding the memory access stage. A bus switching control circuit that detects that the discrimination signal output as the data transfer instruction is to output the bus switching signal; and receives the switching signal output from the bus switching control circuit, A bus switching circuit for switching a use right of the microprocessor. 2. The bus switching signal is output in response to a stage preceding a memory access stage after detecting that each discrimination signal output corresponding to the stage is not the data transfer instruction. 2. The microprocessor according to claim 1, wherein the determination signal is output to the bus switching circuit until the determination signal indicates that the instruction is the data transfer instruction. 3. The bus switching circuit receives a switching signal output from the bus switching control circuit, and releases the right to use the bus while the signal is being output. 2. The microprocessor according to 2.