JP2004348719A - Microcomputer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a microcomputer capable of detecting a runaway state of communication between a CPU and an external processing part when the CPU executes a large processing quantity of memory access to the external processing part having a memory function to avoid the runaway of the CPU. <P>SOLUTION: This microcomputer is provided with a runaway detection control device 12 for monitoring communication between the external processing part formed outside the microcomputer 1 and a memory access control device 11. The control device 12 outputs a pseudo acknowledge signal DK instead of a normal acknowledge signal DK23 to the control device 11 when the CPU 10 accesses to the external processing device in a handshake method and when it is detected that the communication between the external processing part and the CPU 10 is brought into a runaway state. Upon receiving the pseudo acknowledge signal DK through the control device 11, the CPU 10 changes over a memory access method to the external processing part to a fixed weight mode. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a microcomputer, and particularly detects a runaway state of communication between a central processing unit and an external processing unit when a memory is accessed from a central processing unit to an external processing unit having a memory function in a handshake mode. And a microcomputer for avoiding runaway of the central processing unit.

Hereinafter, a conventional microcomputer will be described with reference to FIG. 13 (for example, Patent Document 1). FIG. 13 is a schematic diagram of a main part of a conventional microcomputer. In FIG. 13, the microcomputer 1 includes a central processing unit (hereinafter, CPU) 10 and a memory access control device 11. A processing unit A13, a processing unit B14, a processing unit C15, and a processing unit D16 having a memory function are provided outside the microcomputer 1.
The CPU 10 and the memory access control device 11 communicate with the address signal AD, the data signal DT, the acknowledge signal DK, the chip select signal CS0 for the processing unit A, the chip select signal CS1 for the processing unit B, the chip select signal CS2 for the processing unit C, It is connected via the chip select signal CS3 for the processing section D.

Further, the memory access control device 11 and the processing unit A13 communicate with each other via the processing unit A address signal A0, the processing unit A data signal D0, the processing unit A chip select signal CS0, and the processing unit A acknowledge signal DK0. The memory access control device 11 and the processing unit B14 are connected to each other. The processing unit B address signal A1, the processing unit B data signal D1, the processing unit B chip select signal CS1, and the processing unit B acknowledge signal DK1 Connected through.
The memory access control device 11 and the processing unit C15 are connected via an address signal A2 for the processing unit C, a data signal D2 for the processing unit C, and a chip select signal CS2 for the processing unit C. The device 11 and the processing unit D16 are connected via the processing unit D address signal A3, the processing unit D data signal D3, and the processing unit D chip select signal CS3.

  In FIG. 13, a memory access method from the CPU 10 to the processing unit A13 and the processing unit B14 is a handshake mode. The handshake mode is a mode in which the memory access is terminated by returning an acknowledgment signal from the processing unit to the CPU 10 via the memory access control device 11 after the start of the memory access. On the other hand, the memory access method from the CPU 10 to the processing unit C15 and the processing unit D16 is a fixed wait mode in which the memory access is performed in a set wait cycle from the start to the end of the memory access.

  In FIG. 13, memory access from the CPU 10 to the processing units A13, B14, C15, and D16 is exclusively controlled by the CPU 10. That is, the CPU 10 cannot access the memory of the next processing unit unless the memory access to one processing unit is completed.

The operation of the conventional microcomputer 1 configured as described above will be described. First, memory access from the CPU 10 to the processing unit A13 will be described. When the CPU 10 accesses the processing unit A13 in the memory in the handshake mode and retrieves information stored in the processing unit A13, the CPU 10 performs a memory access control on the chip selection signal CS0 for the processing unit A and the address signal AD indicating an address value to be accessed. Output to the device 11 to request memory access to the processing unit A13. Upon receiving these signals, the memory access control device 11 outputs a chip select signal CS0 for the processing unit A and an address signal A0 for the processing unit A to the processing unit A13. At this point, memory access to the processing unit A13 is started. Then, when a series of processes to the processing unit A13 is completed, the processing unit A13 returns an acknowledge signal DK to the CPU 10 via the memory access control device 11. Then, the memory access control device 11 negates the chip select signal CS0 for the processing unit A, thereby ending the memory access.
Similarly, the CPU 10 accesses the memory of the processing unit B14 in the handshake mode, and reads out the information stored in the processing unit B14.

Next, memory access from the CPU 10 to the processing unit 15C will be described. When the CPU 10 accesses the memory in the processing unit C15 in the fixed wait mode and retrieves the information stored in the processing unit C15, the CPU 10 stores the chip select signal CS2 for the processing unit C and the address signal AD indicating the address value to be accessed in the memory. The data is output to the access control device 11 to request a memory access to the processing unit C15. When receiving these signals, the memory access control device 11 outputs the chip select signal CS2 for the processing unit C and the address signal A2 for the processing unit C to the processing unit C15. At this point, memory access to the processing unit C15 is started. Then, when a series of processing to the processing section C15 is completed in the set wait cycle, the memory access control device 11 negates the chip select signal CS2 for the processing section C, thereby ending the memory access.
Similarly, the CPU 10 also accesses the memory of the processing unit D16 in the fixed wait mode, and retrieves information stored in the processing unit D16.
JP-A-4-217035

  In the conventional microcomputer as described above, when the CPU accesses the external processing unit having the memory function in the handshake mode, when the memory access with a large amount of processing is performed, the external processing unit occupies the memory access processing. In some cases, the acknowledge signal is not returned from the processing unit to the CPU. If this acknowledgment signal is not returned to the CPU, the memory access does not end, and the processing unit cannot accept a memory access interruption instruction from the CPU. As a result, there is a problem that the memory access processing is delayed and the CPU eventually runs away.

  SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems. When the CPU accesses a large amount of memory to an external processing unit having a memory function, communication between the CPU and the external processing unit is performed. An object of the present invention is to provide a microcomputer that detects a runaway state and avoids runaway of the CPU.

  A microcomputer according to claim 1 of the present invention includes: a central processing unit; and a memory access control unit that controls when the central processing unit accesses a memory to an external processing unit having a memory function. , A counter is built in, a time is counted using the counter, a watchdog timer that generates a pulse signal when a predetermined time is counted, and a memory access from the central processing unit to the external processing unit. A runaway detection circuit that detects that the program has not been completed normally and outputs a runaway detection signal, and that the memory access from the central processing unit to the external processing unit has been completed based on the runaway detection signal. Signal generation means for generating a pseudo acknowledge signal shown in FIG. Wherein the runaway detection circuit generates a pulse signal from the central processing unit when the watchdog timer generates a pulse signal between the start of memory access to the external processing unit and the end of the memory access. And outputting the runaway detection signal.

  A microcomputer according to a second aspect of the present invention is the microcomputer according to the first aspect, wherein the central processing unit exclusively accesses memory to the plurality of external processing units, and the runaway detection control device includes the central processing unit. In the memory access from the arithmetic processing unit to the external processing unit, an external processing unit in which the memory access with the central processing unit did not end normally is detected.

A microcomputer according to a third aspect of the present invention is the microcomputer according to the first aspect, wherein the runaway detection control device does not normally end a memory access from the central processing unit to the external processing unit. Is detected, the central processing unit switches the memory access method for the external processing unit from the handshake mode to the fixed wait mode.
Thus, even if the communication between the central processing unit and the external processing unit goes out of control, the memory access is ended, and the central processing unit goes out of control and the system can be prevented from being stopped.

A microcomputer according to a fourth aspect of the present invention is the microcomputer according to the second aspect, wherein the runaway detection control device does not normally end memory access from the central processing unit to the external processing unit. A reset circuit that initializes the runaway detection circuit that has detected the error, and releases the memory space of the external processing unit where the memory access with the central processing unit did not end normally.
As a result, the memory space of the external processing unit in which the communication with the central processing unit has gone out of control can be released to be in a state of waiting for the next memory access.

A microcomputer according to a fifth aspect of the present invention, comprising: a central processing unit; and a memory access control unit for controlling when the central processing unit accesses a memory to an external processing unit having a memory function. , A counter is built in, a time is counted using the counter, a watchdog timer that generates a pulse signal when a predetermined time is counted, and a memory access from the central processing unit to the external processing unit. And a runaway detection control circuit that outputs a runaway detection signal by detecting that runaway has not been completed normally. The runaway detection circuit includes a memory from the central processing unit to the external processing unit. The watchdog timer generates a pulse signal between the start of access and the end of the memory access. Output the runaway detection signal to the interrupt processing unit of the central processing unit when the runaway detection signal is input, the interrupt processing unit limits memory access to the external processing unit. .
Thus, even if the communication between the central processing unit and the external processing unit is in a runaway state, it is possible to prevent the central processing unit from going out of control and stopping the system.

  A microcomputer according to claim 6 of the present invention includes a central processing unit, and a memory access control unit that performs control when the central processing unit exclusively accesses memory to a plurality of external processing units having a memory function. In the microcomputer provided with, in the memory access from the central processing unit to the external processing unit, the runaway notification from the external processing unit in which the memory access with the central processing unit did not end normally and the runaway state occurred. And notifies the central processing unit of the information of the external processing unit in the runaway state via the external processing unit different from the external processing unit in the runaway state and the memory access control device. A runaway notification device is provided.

  8. A microcomputer according to claim 7, comprising: a central processing unit; and a memory access control unit for controlling when the central processing unit accesses a memory to an external processing unit having a memory function. , A counter is built-in, a time is counted using the counter, and when a predetermined time is counted, a watchdog timer that generates a pulse signal, and the central processing unit is connected to an external device based on the pulse signal. A runaway avoidance control device having signal generation means for generating a pseudo acknowledgment signal indicating that the memory access to the processing unit has been completed, wherein the signal generation means sets the watchdog timer in advance after the memory access is started. The pseudo-acknowledge signal is counted by the central processing unit when the counted predetermined time is counted. And outputs.

A microcomputer according to claim 1 of the present invention includes: a central processing unit; and a memory access control unit that controls when the central processing unit accesses a memory to an external processing unit having a memory function. , A counter is built in, a time is counted using the counter, a watchdog timer that generates a pulse signal when a predetermined time is counted, and a memory access from the central processing unit to the external processing unit. A runaway detection circuit that detects that the program has not been completed normally and outputs a runaway detection signal, and that the memory access from the central processing unit to the external processing unit has been completed based on the runaway detection signal. Signal generation means for generating a pseudo acknowledge signal shown in FIG. Wherein the runaway detection circuit generates a pulse signal from the central processing unit when the watchdog timer generates a pulse signal between the start of memory access to the external processing unit and the end of the memory access. And outputting the runaway detection signal.
Thus, even if the communication between the central processing unit and the external processing unit goes out of control, the central processing unit goes out of control and the system can be prevented from stopping.

A microcomputer according to a second aspect of the present invention is the microcomputer according to the first aspect, wherein the central processing unit exclusively accesses memory to the plurality of external processing units, and the runaway detection control device includes the central processing unit. In the memory access from the arithmetic processing unit to the external processing unit, an external processing unit in which the memory access with the central processing unit did not end normally is detected.
As a result, even when the communication between the central processing unit and the external processing unit goes out of control, the memory access to the external processing unit in the runaway state is stopped, the central processing unit goes out of control, and the system stops. Can be avoided.

A microcomputer according to a third aspect of the present invention is the microcomputer according to the first aspect, wherein the runaway detection control device does not normally end a memory access from the central processing unit to the external processing unit. Is detected, the central processing unit switches the memory access method for the external processing unit from the handshake mode to the fixed wait mode.
Thus, even if the communication between the central processing unit and the external processing unit goes out of control, the memory access is ended, and the central processing unit goes out of control and the system can be prevented from being stopped.

A microcomputer according to a fourth aspect of the present invention is the microcomputer according to the second aspect, wherein the runaway detection control device does not normally end memory access from the central processing unit to the external processing unit. A reset circuit that initializes the runaway detection circuit that has detected the error, and releases the memory space of the external processing unit where the memory access with the central processing unit did not end normally.
As a result, the memory space of the external processing unit in which the communication with the central processing unit has gone out of control can be released to be in a state of waiting for the next memory access.

A microcomputer according to a fifth aspect of the present invention, comprising: a central processing unit; and a memory access control unit for controlling when the central processing unit accesses a memory to an external processing unit having a memory function. , A counter is built in, a time is counted using the counter, a watchdog timer that generates a pulse signal when a predetermined time is counted, and a memory access from the central processing unit to the external processing unit. And a runaway detection control circuit that outputs a runaway detection signal by detecting that runaway has not been completed normally. The runaway detection circuit includes a memory from the central processing unit to the external processing unit. The watchdog timer generates a pulse signal between the start of access and the end of the memory access. Output the runaway detection signal to the interrupt processing unit of the central processing unit when the runaway detection signal is input, the interrupt processing unit limits memory access to the external processing unit. .
Thus, even if the communication between the central processing unit and the external processing unit is in a runaway state, it is possible to prevent the central processing unit from going out of control and stopping the system.

A microcomputer according to claim 6 of the present invention includes a central processing unit, and a memory access control unit that performs control when the central processing unit exclusively accesses memory to a plurality of external processing units having a memory function. In the microcomputer provided with, in the memory access from the central processing unit to the external processing unit, the runaway notification from the external processing unit in which the memory access with the central processing unit did not end normally and the runaway state occurred. And notifies the central processing unit of the information of the external processing unit in the runaway state via the external processing unit different from the external processing unit in the runaway state and the memory access control device. A runaway notification device is provided.
As a result, even when the communication between the central processing unit and the external processing unit goes out of control, the memory access to the external processing unit in the runaway state is stopped, the central processing unit goes out of control, and the system stops. Can be avoided.

8. A microcomputer according to claim 7, comprising: a central processing unit; and a memory access control unit for controlling when the central processing unit accesses a memory to an external processing unit having a memory function. , A counter is built-in, a time is counted using the counter, and when a predetermined time is counted, a watchdog timer that generates a pulse signal, and the central processing unit is connected to an external device based on the pulse signal. A runaway avoidance control device having signal generation means for generating a pseudo acknowledgment signal indicating that the memory access to the processing unit has been completed, wherein the signal generation means sets the watchdog timer in advance after the memory access is started. The pseudo-acknowledge signal is counted by the central processing unit when the counted predetermined time is counted. And outputs.
As a result, even if the communication between the central processing unit and the external memory goes out of control, access to the external processing unit in the runaway state is stopped, and the central processing unit goes out of control and the system stops. There is an effect that it can be avoided.

  Hereinafter, a microcomputer according to an embodiment of the present invention will be described with reference to the drawings.

(Embodiment 1)
FIG. 1 is a block diagram showing a configuration of the microcomputer according to the first embodiment. 1, the same reference numerals as those in FIG. 13 denote the same or corresponding parts. The microcomputer according to the first embodiment includes a runaway detection control device 12. Runaway detection control device 12 detects a runaway state of communication between CPU 10 and processing unit A13 or processing unit B14.

  In FIG. 1, the runaway detection control device 12 and the memory access control device 11 include a processing unit A address signal A0, a processing unit A data signal D0, a processing unit A chip select signal CS0, a processing unit A and a processing unit B. Are connected via an acknowledge signal DK23, an acknowledge signal DK, an address signal A1 for the processing section B, a data signal D1 for the processing section B, and a chip select signal CS1 for the processing section B.

  The runaway detection control device 12 and the processing unit A13 are connected via the processing unit A address signal A0, the processing unit A data signal D0, and the processing unit A chip select signal CS0. The device 12 and the processing unit B14 are connected via the processing unit B address signal A1, the processing unit B data signal D1, and the processing unit B chip select signal CS1.

  Further, the processing unit A13 and the memory access control device 11 are connected via an acknowledgment signal DK0 for the processing unit A, and the processing unit B14 and the memory access control device 11 are connected via an acknowledgment signal DK1 for the processing unit B.

  Hereinafter, runaway detection control device 12 will be described in detail with reference to FIG. FIG. 2 is a block diagram illustrating a configuration of the runaway detection control device 12. 2, the same reference numerals as those in FIGS. 1 and 13 indicate the same or corresponding parts. Runaway detection control device 12 includes selector 121, NOR circuit 122, AND circuit 123, runaway detection circuit 124 for processing unit A, runaway detection circuit 125 for processing unit B, and Watchdog Timer (WDT). ) 126 and a general-purpose input / output port (GIO) 127.

  The WDT 126 has a built-in counter, and asserts and outputs an overflow signal a when the count result of the counter reaches a set value. The GIO 127 outputs a signal b indicating whether or not the runaway detection control device 12 is turned on. The processing unit A runaway detection circuit 124 detects whether the processing unit A13 has runaway and outputs a runaway signal c for the processing unit A. The processing unit B runaway detection circuit 125 detects whether the processing unit B14 has runaway and outputs a runaway detection signal d for the processing unit B. The NOR circuit 122 generates a runaway detection signal e indicating that the processing unit A13 or the processing unit B14 has runaway from the runaway signal c for the processing unit A and the runaway signal d for the processing unit B. The AND circuit 123 generates a pseudo acknowledge signal f from the normal acknowledge signal DK23 and the runaway detection signal e. The selector 121 selects one of the normal acknowledgment signal DK23 and the pseudo acknowledgment signal f from the memory access control device 11, and outputs the selected acknowledgment signal f to the memory access control device 11 as an acknowledge signal DK.

  In the microcomputer according to the first embodiment configured as described above, the memory access method from the CPU 10 to the processing unit A13 and the processing unit B14 is the handshake mode, and the CPU 10 is connected to the processing unit C15. The memory access method to the processing unit D16 is a fixed wait mode. Further, each memory access from the CPU 10 to the processing unit A13, the processing unit B14, the processing unit C15, and the processing unit D16 is exclusively controlled by the CPU 10.

Hereinafter, the operation of the microcomputer according to the first embodiment will be described. Since the memory access from the CPU 10 to the processing unit C15 and the processing unit D16 is the same as in the conventional example, the description is omitted, and only the memory access from the CPU 10 to the processing unit A13 and the processing unit B14 will be described with reference to FIG. explain.
FIG. 3 is a timing chart for explaining the operation of the microcomputer according to the first embodiment, and shows a timing chart when CPU 10 performs memory access to processing unit A13. In FIG. 3, t0 is a memory access start time from the CPU 10 to the processing unit A13, that is, a time when the chip select signal CS0 for the processing unit A is asserted, t1 is a time when the overflow signal a is asserted, and t2 is a pseudo acknowledge signal. The time when f is asserted, and t3 indicates the end time of the memory access from the CPU 10 to the processing unit A13.

  First, an operation when the CPU 10 accesses the processing unit A13 with a memory will be described. At the time t0, the CPU 10 outputs the chip select signal CS0 for the processing unit A and the address signal AD indicating the address value to be accessed to the memory access control device 11 at the time t0 to access the memory to the processing unit A13. Request access. At the time of memory access, runaway detection control device 12 is always turned on by output signal b of GIO 127. When the memory access control device 11 receives the processing unit A chip select signal CS0 and the address signal AD, the memory access control device 11 transmits the processing unit A chip select signal CS0 and the processing unit A address signal A0 via the runaway detection control device 12. To the processing unit A13. At this point, memory access to the processing unit A13 starts.

  When the memory access is started, the processing unit A runaway detection circuit 124 monitors the chip select signal CS0 and the overflow signal a from the WDT 126, and detects whether the processing unit A13 is in a runaway state. The WDT 126 starts counting when the power of the system is turned on, and asserts the overflow signal a after a lapse of a sufficiently long time as compared with the normal memory access time, that is, at the timing of t1 shown in FIG. When the processing unit A 13 detects that the overflow signal a is asserted before the memory access is completed, that is, before the chip selection signal CS0 for the processing unit A is negated, the processing unit A 13 Then, the runaway detection signal c is asserted in the cycle t2 following t1. One cycle corresponds to one cycle of the system clock.

  Next, the NOR circuit 122 inputs the runaway detection signal c indicating the runaway state of the processing unit A13, and outputs the runaway detection signal e asserted at the timing of t2. Then, based on the runaway detection signal e, the AND circuit 123 also asserts the pseudo acknowledge signal f at the timing of t2 and outputs the same to the selector 121. The selector 121 uses the signal b as a selector signal, and selects and outputs the pseudo acknowledge signal f to the memory access control device 11 while the runaway detection control device 12 is in the ON state. The memory access control device 11 outputs the pseudo acknowledge signal f to the CPU 10 and negates the chip select signal CS0 for the processing unit A in the next cycle t3. Thus, the memory access from the CPU 10 to the processing unit A13 ends. When recognizing that the memory access to the processing unit A13 has been completed, the CPU 10 automatically switches the memory access method to the processing unit A13 in the handshake mode to the fixed wait mode.

  Further, when the CPU 10 accesses the memory of the processing unit B14, the processing unit B runaway detection circuit 125 detects the runaway of the processing unit B14 from the chip select signal CS1 for the processing unit B and the overflow signal a as described above. . When runaway detection circuit 125 for processing section B asserts and outputs runaway detection signal d, NOR circuit 122 outputs runaway detection signal e asserted at the same timing as runaway detection signal d, and AND circuit 123 detects runaway detection. The pseudo acknowledgment signal f asserted at the same timing as the signal e is output. Subsequent operations are the same as those at the time of memory access from the CPU 10 to the processing unit A13, and thus description thereof is omitted.

  As described above, runaway detection control device 12 detects runaway state of communication between CPU 10 and processing unit A13 by processing unit A runaway detection circuit 124, and detects runaway state of communication between CPU 10 and processing unit B14 by processing unit B runaway. By detecting with the detection circuit 125, it can be specified which of the processing unit A13 and the processing unit B14 has runaway.

  As described above, the microcomputer according to the first embodiment communicates between the external processing units (the processing units A13 and B14) having a memory function and the memory access control device 11 outside the microcomputer 1. Is provided. The runaway detection control device 12 outputs the normal acknowledge signal DK23 when detecting that the CPU 10 is in a runaway state when communication between the CPU 10 and the external processing unit is in the memory access state by the handshake method with the external processing unit. Instead, the pseudo acknowledge signal DK is returned to the CPU 10 via the memory access control device 11. The CPU 10 recognizes that the memory access has been completed by the pseudo acknowledge signal DK, and switches the memory access method with the external processing unit from the handshake mode to the fixed wait mode. As a result, even if a memory access with a large amount of processing is performed and the communication between the CPU 10 and the external processing unit goes out of control, this memory access is forcibly terminated, the CPU 10 goes out of control and the system stops. Can be avoided.

(Embodiment 2)
Next, a microcomputer according to a second embodiment of the present invention will be described with reference to FIGS.
FIG. 4 is a diagram showing a configuration of a runaway detection control device 12a of the microcomputer 1 according to the second embodiment. 4, the same reference numerals as those in FIGS. 1, 2, and 13 indicate the same or corresponding parts. Runaway detection control device 12a includes a reset circuit 128. The reset circuit 128 outputs a reset signal g to the processing unit A runaway detection circuit 124 and the processing unit B runaway detection circuit 125 based on the overflow signal a from the WDT 126, initializes these circuits, and resets the reset signal g Is output to the processing units A13 and B14 to release the memory space of these processing units.

  The operation of the microcomputer configured as described above will be described with reference to FIG. FIG. 5 is a timing chart for explaining the operation of the microcomputer according to the second embodiment, and shows a timing chart when CPU 10 accesses memory of processing unit A13. In FIG. 5, t4 is the time when the overflow signal a of the WDT 126 is negated, and t5 is output from the reset circuit 128 to the processing unit A13, the processing unit B14, the processing unit A runaway detection circuit 124, and the processing unit B runaway detection circuit 125. The time when the reset signal g is asserted, the time t6 is the time when the processing unit A runaway detection circuit 124 and the processing unit B runaway detection circuit 125 are initialized, and the memory spaces of the processing units A13 and B14 are released. Time.

  Hereinafter, an operation when the CPU 10 accesses the processing unit A13 with a memory will be described. It is assumed that runaway detection control device 12a is turned on by output signal b of GIO 127. The operation from time t0 to t3 is the same as in the first embodiment, and a description thereof will be omitted.

  At time t4, after asserting the overflow signal a, the WDT 126 negates the overflow signal a when the count result of the built-in counter reaches the set value. When the overflow signal a is negated, the reset circuit 128a asserts the reset signal g in the next cycle t5, and the processing unit A13, the processing unit B14, the processing unit A runaway detection circuit 124, and the processing unit B runaway detection circuit 125.

  Then, in the next cycle t6, the processing unit A runaway detection circuit 124 and the processing unit B runaway detection circuit 125 are initialized, and the memory spaces of the processing units A13 and B14 are released.

  As described above, in the microcomputer according to the second embodiment, when the communication between the CPU 10 and the external processing unit (the processing unit 13 and the processing unit 14) goes out of control, the memory access control device 11 sends a pseudo acknowledge signal to the CPU 10. By outputting f, the memory access between the CPU 10 and the external processing unit is terminated. Then, after the memory access ends, when the count result of the built-in counter of the WDT 126 reaches the set value, the reset circuit 128 connects the external processing unit (processing unit A13, processing unit B14) and the runaway detection circuit (processing unit A runaway detection circuit 124). The reset signal g is output to the processing unit B runaway detection circuit 125) to release the memory space of the external processing unit and initialize the runaway detection circuit. Thus, even if the communication between the CPU 10 and the external processing unit goes into a runaway state, the memory access is forcibly terminated, and the system can be prevented from going into a runaway state and stopping the system. In addition, the reset signal g initializes the runaway detection circuit, and releases the memory space of the external processing unit in which the communication with the CPU 10 has gone into a runaway state, and can be in a state of waiting for the next memory access. .

(Embodiment 3)
Next, a microcomputer according to a third embodiment of the present invention will be described with reference to FIGS.
FIG. 6 is a diagram showing a configuration of a runaway detection control device 12b of the microcomputer 1 according to the third embodiment. 6, the same reference numerals as those in FIGS. 1, 2, and 13 denote the same or corresponding parts. Runaway detection control device 12b includes a reset circuit 128a. The reset circuit 128a outputs a reset signal h to the processing unit A13 and the processing unit A runaway detection circuit 124 to release the memory space of the processing unit A13 and initialize the processing unit A runaway detection circuit 124. . In addition, the reset signal i is output to the processing unit B14 and the runaway detection circuit 125 for the processing unit B to release the memory space of the processing unit B14 and initialize the runaway detection circuit 125 for the processing unit B.

  FIG. 7 is a timing chart for explaining the operation of the microcomputer according to the third embodiment, and shows a timing chart when CPU 10 performs memory access to processing unit A13. In FIG. 7, t4 is the time when the WDT 126 negates the overflow signal a, t5 is the time when the reset signal h from the reset circuit 128a to the processing unit A13 and the processing unit A runaway detection circuit 124 is asserted, and t6 is the time when the processing unit A13 This is the time when the memory space is released and the processing unit A runaway detection circuit 124 is initialized.

  The operation of the runaway detection control device 12b of the microcomputer 1 configured as described above will be described. It is assumed that runaway detection control device 12b is turned on by output signal b of GIO 127.

  First, an operation when the CPU 10 accesses the processing unit A13 with a memory will be described. The operation from time t0 to t3 is the same as in the first embodiment, and a description thereof will be omitted.

  At time t4, the WDT 126 negates the overflow signal a when the count result of the built-in counter reaches the set value after asserting the overflow signal a. When the overflow signal a is negated, the reset circuit 128a asserts the reset signal h in the next cycle t5 and outputs it to the processing unit A13 and the processing unit A runaway detection circuit 124. Thus, in the next cycle t6, the memory space of the processing unit A13 is released, and the processing unit A runaway detection circuit 124 is initialized.

  When the CPU B accesses the processing section B14 in memory, when the processing section B runaway detection circuit 125 detects a runaway state of communication between the CPU 10 and the processing section B14, the WDT 126 negates the overflow signal a at time t4, and At t5, the reset circuit 128a asserts the reset signal i and outputs it to the processing unit B14 and the processing unit B runaway detection circuit 125. Thus, at time t6, the memory space of the processing unit B14 is released, and the processing unit B runaway detection circuit 125 is initialized.

  As described above, in the microcomputer according to the third embodiment, when the communication between the CPU 10 and the external processing units (the processing units A13 and B14) goes out of control, the memory access control device 11 outputs the pseudo acknowledge signal f to the CPU. To terminate the memory access. When the count result of the built-in counter of the WDT 126 reaches the set value after the end of the memory access, the reset circuit 128a resets the external processing unit in which the communication with the CPU 10 has runaway and the runaway detection circuit that has detected the runaway state. A signal is output, the memory space of the external processing unit is released, and the runaway detection circuit is initialized. Thus, even if the communication between the CPU 10 and the external processing unit is in a runaway state, this memory access is forcibly terminated, and it is possible to prevent the CPU 10 from going into a runaway state and stopping the system. The reset signal h or the reset signal i can initialize the runaway detection circuit that has detected the runaway, and can release the memory space of the runaway processing unit to be in a standby state for the next memory access.

(Embodiment 4)
Next, a microcomputer according to Embodiment 4 of the present invention will be described with reference to FIG.
FIG. 8 is a diagram showing a configuration of a microcomputer runaway detection control device 12c according to the fourth embodiment. 8, the same reference numerals as those in FIGS. 1, 2, and 13 denote the same or corresponding parts. Microcomputer 1 according to Embodiment 4 is characterized in that CPU 10 and runaway detection control device 12c are connected via runaway detection signal INT1 for processing unit A and runaway detection signal INT2 for processing unit B. .

The operation of the microcomputer 1 configured as described above will be described.
First, an operation when the CPU 10 accesses the processing unit A13 with a memory will be described. The CPU 10 requests the memory access control device 11 to access the processing unit A13 by outputting the chip select signal CS0 for the processing unit A and the address signal AD indicating the address value to be accessed. When receiving the processing section A chip select signal CS0 and the address signal AD, the memory access control device 11 outputs the processing section A chip select signal CS0 and the processing section A address signal to the processing section A13. At this point, memory access to the processing unit A13 starts.

When the asserted overflow signal a is input from the WDT 126 before the memory access from the CPU 10 to the processing unit A13 is completed, the processing unit A runaway detection circuit 124 outputs the runaway detection signal INT1 for the processing unit A in the next cycle. Is output directly to the interrupt terminal 1 of the interrupt processing unit. When receiving the runaway detection signal INT1 for the processing unit A, the interrupt processing unit restricts memory access to the processing unit A13.
Similarly, when the processing unit B runaway detection circuit 125 detects a runaway state of communication between the CPU 10 and the processing unit B14 in the memory access from the CPU 10 to the processing unit B14, the processing unit B runaway detection circuit 125 The runaway detection signal INT2 is directly output to the interrupt terminal 2 of the interrupt processing unit of the CPU 10.

  When the runaway detection signal INT1 for the processing unit A is input, the CPU 10 switches the memory access method with the processing unit A13 from the handshake mode to the fixed wait mode, and when the runaway detection signal INT2 for the processing unit B is input, The memory access method with the unit B14 is switched from the handshake mode to the fixed wait mode. Thus, even if the communication between the CPU 10 and the processing unit A13 or the processing unit B14 goes out of control, the CPU 10 can be prevented from going out of control.

  As described above, the microcomputer according to the fourth embodiment provides a runaway detection circuit (processing unit A runaway detection) when CPU 10 and external processing units (processing unit A13, processing unit B14) are accessing by the handshake method. When the circuit 124 and the processing unit B runaway detection circuit 125 detect a runaway state in communication between the CPU 10 and the external processing unit, the runaway detection circuit outputs a runaway detection signal (runaway detection signal INT1 for the processing unit A, runaway signal for the processing unit B). The detection signal INT2) is directly input to the interrupt terminals (interrupt terminals 1 and 2) of the interrupt processing unit of the CPU 10. Then, the CPU 10 switches the memory access method with the external processing unit from the handshake mode to the fixed wait mode based on the runaway detection signal. Thus, even if the communication between the CPU 10 and the external processing unit goes into a runaway state, the memory access is terminated, the CPU 10 goes into a runaway state, and the system is quickly prevented from being stopped. Can be achieved.

(Embodiment 5)
Next, a microcomputer according to a fifth embodiment of the present invention will be described with reference to FIGS.
FIG. 9 is a block diagram showing a configuration of a microcomputer according to the fifth embodiment. 9, the same reference numerals as those in FIG. 13 indicate the same or corresponding parts. The microcomputer 1 according to the fifth embodiment includes a runaway notification device 17. In FIG. 9, when the processing unit A13 runs away, the runaway notification device 17 inputs a runaway notification signal INF1 from the processing unit A13. For example, the processing unit A13 includes a count therein, and outputs a runaway notification signal INF1 to the runaway notification device 17 when the memory access is not completed even after a sufficiently long time has elapsed compared to the normal memory access time. . When runaway notification device 17 receives runaway notification signal INF1 from processing unit A13, runaway notification device 17 notifies CPU 10 via processing unit B14 and memory access control device 11 that processing unit A13 has runaway. When the processing unit B14 runs away, the runaway notification device 17 receives the runaway notification signal INF2 from the processing unit B14, and the processing unit B14 runs away to the CPU 10 via the processing unit A13 and the memory access control device 11. Notify that.

  The operation of the microcomputer 1 configured as described above will be described. First, an operation when the CPU 10 accesses the processing unit A13 with a memory will be described. When accessing the processing section A13, the CPU 10 outputs a chip select signal CS0 for the processing section A and an address signal AD indicating an address value to be accessed to the memory access control device 11 to request access to the processing section A13. . Upon receiving these signals, the memory access control device 11 outputs the processing unit A chip select signal CS0 and the processing unit A address signal A0 to the processing unit A13. At this point, memory access to the processing unit A13 starts.

After the start of the memory access from the CPU 10 to the processing unit A13, if the memory access does not end even after the normal memory access time has elapsed, the runaway notification device 17 inputs the runaway notification signal INF1 from the processing unit A13. When the runaway notification signal INF1 is input, the runaway notification device 17 notifies the CPU 10 via the other processing unit B14 and the memory access control device 11 that are operating normally that the processing unit A13 is in a runaway state. That is, runaway notification device 17 outputs runaway notification signal INF2 to processing unit B14, and runaway notification signal INF2 is input to CPU 10 via processing unit B14 and memory access control device 11. As described above, runaway notification device 17 requests a restriction on memory access. The CPU 10 that has been notified that the processing unit A13 is in the runaway state stops the memory access to the processing unit A13 in the runaway state, thereby returning the system from the runaway state.
When the communication between the CPU 10 and the processing unit B14 becomes a runaway state, the runaway notification device 17 inputs the runaway notification signal INF2 from the processing unit B14, and the CPU 10 via the processing unit A13 and the memory access control device 11. That the processing unit B14 is in a runaway state. That is, runaway notification device 17 outputs runaway notification signal INF1 to processing unit A13, and runaway notification signal INF1 is input to CPU 10 via processing unit A13 and memory access control device 11.

  As described above, the microcomputer according to the fifth embodiment includes runaway notifying device 17, and when a certain external processing unit (for example, processing unit A13) runs away, runaway notifying device 17 switches to another external processing unit (for example, The CPU 10 is notified via the processing unit B14) and the memory access control device 11 that the processing unit is in a runaway state. Thus, even when the communication between the CPU 10 and the external processing units (the processing units A13 and B14) is in a runaway state, it is possible to prevent the CPU 10 from going out of control and stopping the system.

(Embodiment 6)
Next, a microcomputer according to Embodiment 6 of the present invention will be described with reference to FIGS.
FIG. 10 is a block diagram showing a configuration of a microcomputer according to the sixth embodiment. The same reference numerals as those in FIG. 13 denote the same or corresponding parts. The microcomputer according to the sixth embodiment includes a runaway avoidance control device 18. The runaway avoidance control device 18 monitors the runaway state of communication between the CPU 10 and the processing units A13 and B14 via the memory access control device 11 and performs runaway avoidance.

  FIG. 11 is a diagram showing a detailed configuration of the runaway avoidance control device 18. As shown in FIG. 11, the runaway avoidance control device 18 includes a WDT 180, a NOR circuit 181, and an AND circuit 182. WDT 180 generates a pulse signal when the count result of the built-in counter reaches a set value. When the CPU 10 makes memory access to the processing unit A13, a pulse signal j for the processing unit A is generated, and when the CPU 10 makes memory access to the processing unit B14, a pulse signal k for the processing unit B is generated. The NOR circuit 181 receives the pulse signal j for the processing unit A or the pulse signal k for the processing unit B, and outputs a pseudo acknowledge signal 1. The AND circuit 182 receives the pseudo acknowledge signal 1 and the normal acknowledge signal DK23, and generates an acknowledge signal DK to be output to the CPU 10.

  The operation of the microcomputer thus configured according to the sixth embodiment will be described with reference to FIG. FIG. 12 is a timing chart for explaining the operation of the microcomputer according to the sixth embodiment, and shows a timing chart at the time of memory access from CPU 10 to processing unit A13. 12, t0 is the time when the chip select signal CS0 for the processing unit A is asserted, t7 is the time when the WDT 180 generates a pulse signal, and the time when the pseudo acknowledge signal 1 is asserted, and t8 is the time when the CPU 10 This is the time when the memory access to the unit A13 ends.

  When a memory is accessed to the processing unit A13, the CPU 10 outputs a chip select signal CS0 for the processing unit A and an address signal AD indicating an address value to be accessed to the memory access control device 11 at time t0, and sends the signal to the processing unit A13. Request for memory access. When receiving these signals, the memory access control device 11 outputs the processing unit A chip select signal CS0 and the processing unit A address signal A0 to the processing unit A13.

  At this point, memory access to the processing unit A13 is started. The WDT 180 counts up the time from when the chip select signal CS0 for the processing unit A is asserted by the built-in asynchronous counter, and when the count result exceeds the set value, the pulse signal for the processing unit A at timing t7. Generate j. Then, the NOR circuit 181 generates the pseudo-acknowledge signal 1 at the timing of t7, and the AND circuit 182 outputs the pseudo-acknowledge signal 1 to the CPU 10 as the acknowledge signal DK, whereby the memory access is forcibly terminated at the timing of t8. .

  Similarly, when the CPU 10 accesses the memory of the processing unit B14, the WDT 180 counts up the time from when the chip select signal CS1 for the processing unit B is asserted by the built-in asynchronous counter, and the count result exceeds the set value. At this time, the pulse signal k for the processing section B is generated at the timing of t7. Then, the NOR circuit 181 generates the pseudo acknowledgment signal 1 and the AND circuit 182 outputs the pseudo acknowledgment signal 1 to the CPU 10 as the acknowledgment signal DK, whereby the memory access is forcibly terminated at the timing of t8.

  As described above, the microcomputer according to the sixth embodiment includes the runaway avoidance control device 18 that connects the memory access control device 11 and the external processing units (the processing units A13 and B14). Then, when a predetermined time has elapsed since the memory access started by the runaway avoidance control device 18, a pseudo acknowledge signal 1 is generated, and this pseudo acknowledge signal is input to the CPU 10 as the acknowledge signal DK via the memory access control device 11. . Then, the CPU 10 recognizes that the memory access has been completed based on the pseudo acknowledge signal DK, and terminates the memory access. This makes it possible to forcibly terminate the memory access between the CPU 10 and the external processing unit after a lapse of a predetermined time from the start of the memory access, thereby avoiding runaway of the system.

  The present invention is suitable for a system in which a microcomputer accesses a large amount of memory from an external memory.

FIG. 1 is a configuration diagram of a microcomputer according to Embodiment 1 of the present invention. FIG. 2 is a detailed configuration diagram of a microcomputer runaway detection control device according to the first embodiment. FIG. 5 is a timing chart for explaining the operation of the microcomputer runaway detection control device according to the first embodiment. FIG. 6 is a configuration diagram of a microcomputer according to a second embodiment of the present invention. FIG. 9 is a timing chart for explaining an operation of the microcomputer runaway detection control device according to the second embodiment. FIG. 9 is a configuration diagram of a microcomputer according to Embodiment 3 of the present invention. FIG. 11 is a timing chart for explaining the operation of the microcomputer runaway detection control device according to the third embodiment. FIG. 14 is a configuration diagram of a microcomputer according to Embodiment 4 of the present invention. FIG. 13 is a configuration diagram of a microcomputer according to Embodiment 5 of the present invention. FIG. 13 is a configuration diagram of a microcomputer according to Embodiment 6 of the present invention. FIG. 16 is a detailed configuration diagram of a microcomputer runaway avoidance control device according to the sixth embodiment. FIG. 16 is a timing chart for explaining the operation of the microcomputer runaway avoidance control device according to the sixth embodiment. FIG. 11 is a configuration diagram of a conventional microcomputer.

Explanation of reference numerals

1 microcomputer 10 central processing unit (CPU)
11 Memory access control device 12, 12a, 12b, 12c Runaway detection control device 13 Processing unit A
14 Processing part B
15 Processing unit C
16 Processing unit D
17 Runaway notification device 18 Runaway avoidance control device AD, A0 to A3 Address signal DT Data signal CS0 to CS3 Chip select signal DK, DK2, DK3, DK23 Acknowledge signal D0 to D3 Data signal A1, A2 Address signal
INT1, INT2 Runaway detection interrupt signal INF1, INF2 Runaway notification signal a Overflow signal b Runaway detection controller ON signal c Runaway detection signal for processing unit A d Runaway detection signal for processing unit B e Runaway detection for processing unit A and processing unit B Signal f Pseudo acknowledge signal g Reset signal h Reset signal for processing unit A i Reset signal for processing unit B j Pulse signal for processing unit k Pulse signal for processing unit l Pseudo acknowledgment signal (pulse signal)
121 selector 122 NOR circuit 123 AND circuit 124 runaway detection circuit of processing unit A 125 runaway detection circuit of processing unit B 126, 180 Watchdog timer (WDT)
127 General-purpose port (GIO)
128, 128a Reset generation device 181 NOR circuit 182 AND circuit

Claims (7)

A microcomputer including a central processing unit and a memory access control unit that performs control when the central processing unit accesses a memory to an external processing unit having a memory function;
A watchdog timer incorporating a counter, counting time using the counter, and generating a pulse signal when counting a predetermined time;
A runaway detection circuit that detects that the memory access from the central processing unit to the external processing unit has not been normally completed and outputs a runaway detection signal;
A signal generation unit that generates a pseudo acknowledge signal indicating that the memory access from the central processing unit to the external processing unit has been completed based on the runaway detection signal, and outputs the pseudo acknowledgment signal to the central processing unit;
A runaway detection control device having
The runaway detection circuit performs the runaway when the watchdog timer generates a pulse signal during a period from the start of memory access from the central processing unit to the external processing unit to the end of the memory access. Output detection signal,
A microcomputer characterized by the above-mentioned. The microcomputer according to claim 1,
The central processing unit exclusively accesses the plurality of external processing units with a memory,
The runaway detection control device detects, in the memory access from the central processing unit to the external processing unit, an external processing unit in which the memory access with the central processing unit did not end normally.
A microcomputer characterized by the above-mentioned. The microcomputer according to claim 1,
If the runaway detection control device detects that the memory access from the central processing unit to the external processing unit has not been normally completed, the central processing unit determines a memory access method to the external processing unit. Switch from handshake mode to fixed weight mode,
A microcomputer characterized by the above-mentioned. The microcomputer according to claim 2,
The runaway detection control device initializes the runaway detection circuit which has detected that the memory access from the central processing unit to the external processing unit has not been normally completed, and stores the memory with the central processing unit. A reset circuit for releasing the memory space of the external processing unit in which the access has not been normally completed;
A microcomputer characterized by the above-mentioned. A microcomputer including a central processing unit and a memory access control unit that performs control when the central processing unit accesses a memory to an external processing unit having a memory function;
A watchdog timer incorporating a counter, counting time using the counter, and generating a pulse signal when counting a predetermined time;
A runaway detection circuit that detects that the memory access from the central processing unit to the external processing unit has not been normally completed and outputs a runaway detection signal;
A runaway detection control device having
The runaway detection circuit performs the runaway when the watchdog timer generates a pulse signal during a period from the start of memory access from the central processing unit to the external processing unit to the end of the memory access. Outputting the detection signal to the interrupt processing unit of the central processing unit,
The interrupt processing unit, when the runaway detection signal is input, restricts memory access to the external processing unit;
A microcomputer. A microcomputer including a central processing unit and a memory access control device that performs control when the central processing unit exclusively accesses a plurality of external processing units having a memory function;
In the memory access from the central processing unit to the external processing unit, a runaway notification is received from the external processing unit in which the memory access with the central processing unit did not end normally and went into a runaway state. A runaway notifying device that notifies the central processing unit of information on the runaway state of the external processing unit via the external processing unit and the memory access control device different from the external processing unit.
A microcomputer characterized by the above-mentioned. A microcomputer including a central processing unit and a memory access control unit that performs control when the central processing unit accesses a memory to an external processing unit having a memory function;
A watchdog timer incorporating a counter, counting time using the counter, and generating a pulse signal when counting a predetermined time;
Signal generation means for generating a pseudo acknowledge signal indicating that the memory access from the central processing unit to the external processing unit has been completed based on the pulse signal,
A runaway avoidance control device having
The signal generating means outputs the pseudo acknowledgment signal to the central processing unit when the watchdog timer has counted a predetermined time after the start of the memory access,
A microcomputer characterized by the above-mentioned.

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