JPH0444125A - Microprocessor - Google Patents

Abstract

PURPOSE:To obtain a microprocessor suited to the tracing operations by outputting a branching origine address and a branching destination address in the idle cycles set after the execution of a branching instruction with no superposition caused between those addresses and an instruction fetch. CONSTITUTION:When a pipeline hazard occurs due to a bus error, etc., a normal microprocessor 22 having an n-stage pipeline structure outputs a branching side address and a branched side address through an address bus and a data bus respectively in the same idle bus cycle set before the execution of the next instruction after the branch of the branched side address of a register PC (program counter) of an instruction decoding stage DEC out of the PCS (program counter stack) registers 10 at every stage set for a retry to reset a normal operation and the branching side address of a tracing PC stack register 10 which stacks continuously the branching side address until an instruction stored in the branched side address is executed. Thus the branching side address or the branched side address can be easily traced.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a microprocessor having a multi-stage pipeline structure and suitable for tracing an execution flow program.

BACKGROUND OF THE INVENTION In recent years, increasing the speed of information processing has become an important issue, and pipeline processing has been implemented. As a conventional tracing device for tracing a device using such a microprocessor, there is a method of recording addresses of branch processing. For example, when a branch instruction is executed, the branch source address and the subsequently executed branch destination address are stored in the trace memory, and whether the recorded address is the address that stores the branch instruction or not. The branch instruction information is also stored in the least significant bit of the contents of the trace memory, and when other instructions that do not change the flow of the program are executed, their addresses are not recorded. The operation is shown in the timing chart of FIG. FIG. 3 is a block diagram showing the configuration of this conventional device, in which 1 is a trace memory for recording each address, 2 is a trace memory address counter, 3 is a trace address, 4 is a trace controller, and 5 is a counter. clock signal (output only for branch instructions), 6
7 is a write permission signal, 7 is branch instruction information (1 if the recorded address is a branch source address, otherwise 0), 8 is an instruction code bus, and 9 is an address bus.

A conventional trace device made up of these components adds 0 to the lowest bit of the contents of the trace memory for the address to which the branch instruction was given, and its upper bits indicate the branch source address at that time. shall be indicated. Furthermore, for the branch destination address, 1 is added to the least significant bit of the contents of the trace memory, indicating that the instruction was executed following the previous branch instruction, and the upper bit indicates the branch destination address at that time. I take it as a thing.

Problem to be Solved by the Invention In such a conventional configuration, when a microprocessor has an n-stage pipeline structure, a problem arises in that the branch destination address lags the branch source address by a minimum of n-1 cycles. In other words, undefined data is output to the empty bus cycle during this period, and the execution of the branch destination instruction that is executed following the execution cycle of the branch instruction is delayed for a certain cycle (
(depending on the addressing mode, etc.) is executed after the elapsed time.

In such a case, it is possible to extract only the branch source address or branch destination address from the information on the bus and trace it by controlling the timing signal (write enable signal 6) to capture the branch destination address into the trace memory. , microprocessors with an n-stage pipeline structure have complex addressing modes, so it is extremely difficult to trace only the branch source address and branch destination address. . Another problem was that the configuration of the tracing device was complicated.

The present invention solves the above problem, and provides a microprocessor having an n-stage pipeline structure that can easily trace a branch source address or a branch destination address and simplify the configuration of a tracing device. With the goal.

Means for Solving the Problems In order to achieve the above object, the present invention provides a microprocessor having a multi-stage pipeline configuration, which includes a program counter stack register corresponding to each of the pipelines, and each register having a program counter stack register corresponding to each pipeline. In a microprocessor that stores the executed addresses of lines in a stacked manner, a branch instruction detection device that detects that the microprocessor has executed a branch instruction and outputs a branch detection signal is installed inside the microprocessor. means for generating a branch trace enable signal, a trace program counter stack register for stacking and storing a branch source address according to the branch detection signal, and a trace program counter stack register for stacking and storing a branch source address according to the branch detection signal; a first selection means that selects a branch destination address in a register, switches it with an operand address, and outputs it to an address bus; and selects a branch source address in the trace program counter stack register under the control of the branch trace enable signal. and a second switching means for switching with the execution data and outputting it to the data bus, and the branch source address and the branch destination address are output in an empty cycle after execution of the branch instruction so as not to overlap with the instruction fetch. A microprocessor shall be used.

Effect of the Invention The present invention has the above-described configuration, so that when a normal microprocessor having an n-stage pipeline structure generates a pipeline hazard due to a bus error or the like, each stage is provided for the purpose of retrying to return to normal operation. Among the PC8 (program counter stack) registers, the PC (program counter) of the register of the instruction decoding stage DEC, that is, the branch destination address and the branch source address are stacked until the instruction stored at the branch destination address is executed. The branch source address of the trace PC stack register/star is output from the address bus and the branch source address from the data bus during an empty bus cycle from the branch to the next instruction execution in the same cycle. Ru.

Embodiment Hereinafter, a microprocessor according to an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a program address tracing device according to an embodiment of the present invention.

In the figure, 10 is a PC3 (program counter stack), 11 is an address bus, 12 is a data bus, 13 is a branch destination address bus, 14 is a branch source address bus, 15
is an OA (operand address) bus, 16 is an EX (execution) data bus, and ]7 to 21 are selectors.

The mutual relationship and operation of each of the above components will be explained for a four-stage pipeline (FIG. 1). Note that even if this becomes multi-stage with four or more stages, the basic operation remains the same, only the number of stages increases.

When tracing a branch instruction, when the microprocessor receives a branch trace request signal, the microprocessor receives signals from the branch trace enable signal generation means and the branch instruction detection means, and the microprocessor traces the cycle in which execution of the branch instruction has been determined. D of PC3IO in the next cycle ■ of ■
The contents of the EC register, ie, the branch destination address, are selected by the selector 5ELI and output to the branch destination address bus 13, and then output to the address bus 11 via the selector 5EL3.

Similarly, the content of the trace register of the PC 810, that is, the branch source address, is selected by the selector 5EL2, and output to the branch source address bus 14 in the same cycle V.
4 to the data bus 12.

The data on each of these buses is written to the branch source and branch destination trace memories provided outside the microprocessor (not shown) in the cycle (2) following the cycle (2) in which the execution of the branch instruction has been determined.

In this manner, when tracing only branch instructions, the microprocessor executes the above-mentioned special bus cycle. During a normal bus cycle, 5EL3 selects the OA bus, and 5EL4 or 5EL5 selects the EX data bus.

Each operation of the pipeline stage for a cycle and the state of the bus and the state of the PC 8 at that time (FIG. 2) will be explained.

Figure 2 is a timing diagram showing the processing state at each pipeline stage from execution of branch instruction B until execution of branch destination instruction T, and the flow of the corresponding states of each PCS register and each bus. The branch source address RPC is output to each bus.

Branch destination address TPC, branch instruction B or branch destination instruction T
, and the state of the branch source address RPC or branch destination address TPC at that time in each register in the PC8.

Each register in the PC 8 always pushes an address in which an instruction to be executed in each stage is stored, starting half a cycle before the cycle in which the instruction is executed in the corresponding stage.

When tracing only branch instructions, branch instruction B
After executing (cycle 2), the contents of the DEC register and trace register in the PC 8 are output to the address bus and data bus, respectively, in the next empty bus cycle 2.

The operation of the trace register at this time is that when branch instruction B is executed, it boots the branch source address B and PC, and does not pop until the next branch destination instruction is executed, and only after this is executed. Bush the branch destination address TPC.

As described above, according to the microprocessor according to the embodiment of the present invention, the microprocessor having a four-stage pipeline configuration is provided with a program counter stack register corresponding to each of the pipelines, and each register is connected to the corresponding pipeline. In a microprocessor that stores executed addresses in a stacked manner, the microprocessor includes branch instruction detection means for detecting that the microprocessor has executed a branch instruction and outputting a branch detection signal. , a branch trace permission signal generating means for generating a branch trace permission signal, a trace program counter stack register for stacking and storing branch source addresses according to the branch detection signal, and four program counters under the control of the permission signal. a first selection means for selecting a branch destination address in a program counter stack register for the DEC corresponding to the pipeline stage DEC in the stack register PC8, switching it with an operand address and outputting it to the address bus; and second switching means for selecting the branch source address in the trace program counter stack register under control of the permission signal, switching it with execution data and outputting it to the data bus, wherein the branch source address and the branch destination address are By using a microprocessor that outputs data in a free cycle after executing a branch instruction so as not to overlap with an instruction fetch, even a microprocessor with a four-stage pipeline configuration can be used while utilizing the existing PC8. , the branch source address and the branch destination address can be easily obtained, and a microprocessor suitable for tracing can be obtained.

Incidentally, in the embodiment, the branch source address and the branch destination address are output in cycle V, but it goes without saying that it is clear from the timing chart that they may be output in other empty cycles (2) or (2).

Effects of the Invention As is clear from the embodiments described above, the present invention provides a microprocessor having a multi-stage pipeline configuration, which includes a program counter stack register corresponding to each of the pipelines, and each register having a program counter stack register corresponding to each of the pipelines. In a microprocessor that stores executed addresses in a stacked manner, the microprocessor includes branch instruction detection means for detecting that the microprocessor has executed a branch instruction and outputting a branch detection signal. , a branch trace enable signal generating means for generating a branch trace enable signal; a trace program counter stack register for stacking and storing branch source addresses according to the branch detection signal; a first selection means for selecting a branch destination address, switching it with an operand address, and outputting it to an address bus; and selecting a branch source address in the trace program counter stack register under the control of the branch trace enable signal. , a second switching means for switching with the execution data and outputting it to the data bus, and the branch source address and the branch destination address are outputted in an empty cycle after execution of the branch instruction so as not to overlap with an instruction fetch. By creating a microprocessor with
A branch source address and a branch destination address can be easily obtained, and a microprocessor suitable for tracing can be obtained.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a microprocessor according to an embodiment of the present invention, FIG. 2 is a timing chart showing the operation of the microprocessor according to the present invention, and FIG. 3 is a block diagram showing the configuration of a conventional tracing device. , FIG. 4 is a timing chart showing the operation of a conventional tracing device. 10...Program counter stack register, 11...Address bus, 12...Data bus, 13...Branch destination address bus, 14
...Branch source address bus, 15...Operand address, 16...Execution address, 1
7.19...Selector (first selection means), 1
8, 20. 21... Selector (second selection means), 22... Microprocessor.

Claims (1)

[Claims] A microprocessor having a multi-stage pipeline configuration, comprising a program counter stack register corresponding to each of the pipelines, and each register storing a stack of addresses executed by the corresponding pipeline. In the microprocessor, branch instruction detection means detects execution of a branch instruction by the microprocessor and outputs a branch detection signal, and branch trace permission signal generation means generates a branch trace permission signal; A tracing program counter stack register stores a branch source address in a stacked manner according to the branch detection signal, and a branch destination address in the program counter stack register is selected under the control of the enable signal and is switched to an operand address to be transferred to an address bus. and a second switching means that selects a branch source address in the trace program counter stack register under the control of the branch trace permission signal, switches it with execution data, and outputs it to the data bus. and the branch source address and the branch destination address are output in an empty cycle after execution of a branch instruction so as not to overlap with an instruction fetch.