JPH06110686A - Register interference preventing device - Google Patents

Abstract

PURPOSE:To interrupt the backward program execution in case of a reference interference at a pipeline processing and to prevent the register interference by re-execution by occupying one CPU with plural register files and permitting the plural register files to parallely process plural tasks. CONSTITUTION:Address information outputted from a bus 1 address generation section 5 and from a bus 3 address generation section 7 is inputted to a register file 10 and to an address comparison section 11 as well. A register file selection number outputted by a register file selection section 17 is also inputted to the address comparison section 11. Only when the address information and the register file number coincide, an address output delay signal 16 is inputted to the bus 1 address generation section 5, preventing the register interference.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a register interference avoiding apparatus for avoiding register interference by interrupting and re-executing backward program execution when register interference occurs in pipeline processing.

[0002]

2. Description of the Related Art In pipeline processing, a write operation of a currently executed instruction to a register and a read operation of an instruction to be executed next may occur at the same timing. In addition, if the program to be executed next is executed by referring to the operation result (register value) that is currently being executed, the register that is currently being executed and the next If the register read by the instruction to be executed in the same register is the same register (has the same register address), the value of the read data is written because the data writing and reading are performed to the same register at the same timing. There was a case where it did not match the value of the data.

Conventionally, the following means have been considered as means for avoiding such a phenomenon called register interference.

(1) When the register being written by the instruction currently being executed and the register being read by the instruction to be executed next match (register addresses are the same), the read operation of the register for the instruction to be executed next is interrupted. Then, after the instruction currently being executed writes data to the register, a means for re-reading the register by the instruction to be executed next at a different timing.

(2) When the register being written by the instruction currently being executed and the register being read by the instruction to be executed next match (the register address is the same), the instruction to be executed next reads data from the register. Rather, a means to secure the read timing by reading the data directly from the data write path to the register by the instruction currently being executed.

These means compare the register address written by the instruction currently being executed with the register address read by the instruction to be executed next, judge whether they match, and avoid register interference. It was that.

[0007]

However, as described above, in the case of having a plurality of register files, the register written by the instruction currently being executed and the register read by the instruction to be executed next match (register address is Even if the same), the register file may be different, and in this case, the conventional register interference avoiding operation is unnecessary. The present invention provides a register interference avoidance device that solves such conventional problems.

[0008]

In order to solve the above problems, the present invention (1) determines whether the register files are the same and whether the register interference causes register interference. Furthermore, (2) a flag indicating the switching timing of the register file is provided,
It is determined from this flag and the register address whether register interference will occur. It is equipped with means.

[0009]

With the above configuration, in a plurality of register file configurations, register interference avoidance by re-execution is executed only when there is true register interference, so that a system with high execution efficiency can be realized.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a register interference avoidance apparatus for judging register interference according to the register file number and the register number of the present invention. FIG. 2 is a register file configuration diagram of the register interference avoidance apparatus of the present invention. Figure 3,
FIG. 4 is a diagram showing a register file number and execution timing of the register interference avoiding apparatus for judging register interference according to the register number of the present invention.

In FIG. 1, a bus 1 address generator 5 for generating and outputting address data to be sent to the bus 1 and a bus 2 for generating and outputting address data to be sent to the bus 2.
The address generation unit 6, the bus 3 address generation unit 7 that generates and outputs address data to be sent to the bus 3, and the address information generated and output by the bus 3 address generation unit 7 are temporarily latched, and the bus 3 address generation unit 7 The address generation unit 9 is composed of the address latch unit 8 that outputs the address information latched on the bus 4 at a timing different from the bus 3 drive timing. In the present invention, information for selecting one register (a plurality of registers constitutes the register file 10) is defined as "address data". Therefore, in the present invention, the so-called register number is also 1 of the address data.
Suppose Each address data output from the address generation unit 9 according to the pipeline timing is the bus 1
Register file 10 and address comparison unit 1 through
Input to 1.

The role of each bus is as follows. Bus 1: Used when the data required for the operation is stored in the address indicated by the data stored in the register (the data to be operated is not directly stored in the register to be read).

Bus 2: Used when data required for calculation is directly stored in a register (or memory, memory is not shown) (first calculation data).

Bus 3: Used when data required for calculation is directly stored in the register (second calculation data).

Bus 4: Used when the operation result is directly stored in the register. In the case of the same instruction, the same address information on the bus 3 and the address information on the bus 4 are used (the same as the address of the second operation data on the bus 3). The following two instructions are defined as the pipeline operation of the instructions using these buses.

(Instruction 1) Timing 1: Bus 1 is used to read the contents of the register.

Timing 2: Bus 2 is used to read the contents of the register (memory). The contents of the register are read using the bus 3.

Timing 3: Bus 4 is used to write data to the register (here, timings 1 to 3 indicate the passage of time in the pipeline.) (Instruction 2) Timing 1: Buses 1 to 4 Not used .

Timing 2: Bus 2 is used to read the contents of the register. Timing 3: Bus 4 is used to write data to the register.

In the pipeline operation, the timing 2 of the previously executed instruction and the timing 1 of the later executed instruction, and the timing 3 of the previously executed instruction and the timing 2 of the later executed instruction overlap each other. The first instruction executed in FIG. 3 is: timing 1: bus 1 is used, Read3-2 (reading register number 2 of register file 3) timing 2: bus 2, read 3-3 (register file 3 Read register number 3), bus 3
And read 3-1 (read register number 1 of register file 3) timing 3: use bus 4 and execute Write 3-1 (read register number 1 of register file 3) (1 cycle in the figure) Is the same as 1 timing).

FIG. 2 shows the structure of the register file, and the registers operated by the above-mentioned instruction of FIG. 3 are: Read3-2 (reading the register number 2 of the register file 3 of FIG. 3) = (19 of FIG. 2) Register 2) Read3-3 (read register number 3 of register file 3 of FIG. 3) = (register 3 of 20 of FIG. 2) Read3-1 (read register number 1 of register file 3 of FIG. 3) = (figure 18 register 1 of 2) Write 3-1 corresponds to register 1 of 18 of FIG. 2 like Read 3-1.

The second instruction to be executed in FIG. 3 is: timing 1: bus 1 is used; Read1-1 (read of register number 1 of register file 1).

Timing 2: Bus 2 is used and Read
1-1 (reading register number 1 of register file 1) Bus 3 is used and Read 1-2 (register file 1
Readout of the register number 2 of the above) Timing 3: It is executed by Write1-2 (readout of the register number 2 of the register file 1) using the bus 4.

FIG. 3 which is the second to be executed in FIG.
The registers operated by the instruction are: Read1-1 (read register number 1 of register file 1 of FIG. 3) = (register 1 of 21 of FIG. 2) Read1-2 (register number 3 of register file 3 of FIG. 3) Read) = (Register 2 of 22 in FIG. 2) Write1-2 corresponds to Register 2 of 22 in FIG. 2 like Read1-2. In FIG. 3, the register 1 of the register file 3 of the first instruction is likely to cause register interference (Write 3 of 23 in FIG. 3).
1, register 18 of FIG. 2) and register 1 of register file 1 of the second instruction (Read 1-1 of 24 of FIG. 3, FIG. 2)
It is necessary to judge whether there is register interference between the register 21) and the register 21). This is because it is possible that the second instruction is executed using the value of the register at the timing 23 after the writing operation (= timing 23) to the register by the first instruction execution. This is because the timing of reading the first instruction precedes the writing of the first instruction to the register, so that the result of the first instruction may not be reflected in the second instruction. However, at timing 24 and timing 23, it is impossible to determine the register interference temporally. Since the Write 3-1 at the timing 23 and the Read 3-1 at the timing 25 use the same address, the register interference is determined at the timing 24 and the timing 25. Therefore, the bus 1 and the bus 3 are the targets of the address comparison. Therefore, in FIG. 1, the bus 1 and the bus 3 are input to the comparator 12 of the address comparison unit 11, the address data values generated and output by the bus 1 address generation unit 5 and the bus 3 address generation unit 7 are compared, and the address data is If they match, "1" is output to the AND circuit 160. On the other hand, in order to manage the register file numbers of the registers used in each pipeline, the register file selection unit 17 assigns the register file numbers for the bus types (four types in the case of this embodiment) according to the pipeline operation status. It is sent to the register file 10 and the register file is selected.

Further, in order to determine whether register interference has occurred between the bus 1 and the bus 3, the register file number 14 corresponding to the bus 1 and the register file number 15 corresponding to the bus 3 are sent to the comparator 13 as well. The file numbers are compared, and if the register file number data match, "1" is output to the AND circuit 160. The AND circuit 160 outputs the address output delay signal 16 to the bus 1 address generator 5 only when the address data and the register file number match, that is, when the outputs of the comparators 12 and 13 are "1". In response to this, the address generation unit 5 shifts the address output timing to the bus 1 backward, and operates so as not to cause register interference. In FIG. 3, at timing 24, the register 1 of the register file number 1 is read, and at timing 2
In 5, the register 1 of the register file number 3 is read. In this case, since the register numbers match but the register file numbers do not match, register interference does not occur and the reading of the register 1 at the timing 24 is performed as it is. In FIG. 4, the register 1 of the register file number 3 is read at the timing 26, and the register 1 of the register file number 3 is also read at the timing 27. In this case, since both the register number and the register file number match, register interference occurs and the reading of register 1 at timing 26 is performed at timing 28 with a delay of one cycle. If there is a single register file, the register interference shown in FIG. 4 frequently occurs and it is necessary to avoid it. If the tasks are configured to be processed in parallel, register interference cannot be determined only by comparing the register numbers as shown in FIG. 3, and the register file numbers are compared, so that only when the register file interference is true. By performing the register interference avoiding operation (delaying the register shown in FIG. 4 for one cycle), the disturbance of the pipeline can be minimized.

FIG. 5 is a diagram showing a configuration of a register interference avoidance device provided with a flag indicating the switching timing of the register file of the present invention, and FIGS. 6 and 7 are flags showing the switching timing of the register file of the present invention. It is a figure showing the execution timing of the register interference avoidance device provided with. In FIG. 5, a bus 1 address generation unit 5 that generates and outputs address data to be sent to the bus 1, a bus 2 address generation unit 6 that generates and outputs address data to be sent to the bus 2, and an address data that is sent to the bus 3 are generated. The output bus 3 address generation unit 7 and the address information generated and output by the bus 3 address generation unit 7 are temporarily latched and latched in the bus 4 at a timing different from the bus 3 drive timing of the bus 3 address generation unit 7. The address generation unit 9 is composed of the address latch unit 8 that outputs address information. In the present invention, information for selecting one register (a plurality of registers constitutes the register file 10) is defined as "address data". Therefore, in the present invention, the so-called register number is also one of the address data. Each address data output from the address generation unit 9 according to the pipeline timing is input to the register file 10 and the address comparison unit 31 via the buses 1 to 4. The role of each bus is used when reading the register when the data required for the operation is stored in the address indicated by the data stored in the bus 1: register. The data to be calculated is not directly stored in the read register.

Bus 2: Used when data required for calculation is directly stored in a register (or memory, memory is not shown) (first calculation data).

Bus 3: Used when data required for calculation is directly stored in the register (second calculation data).

Bus 4: Used when the operation result is directly stored in the register. In the case of the same instruction, the same address information on the bus 3 and the address information on the bus 4 are used (the same as the address of the second operation data on the bus 3). Is. The following two instructions are defined as the pipeline operation of the instructions using these buses.

(Instruction 1) Timing 1: Bus 1 is used to read the contents of the register.

Timing 2: Bus 2 is used to read the contents of the register (memory). The contents of the register are read using the bus 3.

Timing 3: The bus 4 is used to write data in the register (timings 1 to 3 show the passage of time in the pipeline).

(Instruction 2) Timing 1: Buses 1 to 4 not used.

Timing 2: Bus 2 is used to read the contents of the register. The contents of the register are read using the bus 3.

Timing 3: Write data to the register using the bus 4. In the pipeline operation, the timing 2 of the instruction executed first and the timing 1 of the instruction executed later, and the timing 3 of the instruction executed first and the timing 2 of the instruction executed later overlap in timing. The first instruction executed in FIG. 6 is: Timing 1: Bus 1 is used, Read 3-2 (read register number 2 of register file 3) Timing 2: Bus 2 is used, Read 3-3 (register file Read register number 3 of 3), bus 3
And read 3-1 (read register number 1 of register file 3) timing 3: use bus 4 and execute Write 3-1 (read register number 1 of register file 3) (1 cycle in the figure) Is the same as 1 timing).

The structure of the register file is shown in FIG. 2 and each register operated by the instruction of FIG. 6 is: Read3-2 (read of register number 2 of register file 3 of FIG. 6) = (register 19 of FIG. 2) 2) Read3-3 (read register number 3 of register file 3 of FIG. 6) = (register 3 of 20 of FIG. 2) Read3-1 (read register number 1 of register file 3 of FIG. 6) = (FIG. 2) 18 of 1) Write 3-1 corresponds to the register 1 of 18 of FIG. 2 like Read 3-1.

The second instruction to be executed in FIG. 6 is: timing 1: bus 1 is used; Read 1-1 (reading register number 1 of register file 1) timing 2: bus 2 is used, Read1-1 (read register number 1 of register file 1), bus 3
And read 1-2 (read register number 2 of register file 1) timing 3: use bus 4 and execute write 1-2 (read register number 2 of register file 1).

In FIG. 2, the registers operated by the second instruction executed in FIG. 6 are: Read1-1 (read register number 1 in register file 1 in FIG. 6) = (register 21 in FIG. 2) 1) Read1-2 (reading the register number 3 of the register file 3 in FIG. 6) = (register 2 at 22 in FIG. 2) Write1-2 corresponds to register 2 at 22 in FIG. 2 like Read1-2. In FIG. 6, register 1 of the register file 3 of the first instruction is likely to cause register interference (Write 3 of 32 in FIG. 6).
1, register 18 of FIG. 2) and register 1 of register file 1 of the second instruction (Read 1-1 of 33 of FIG. 6, FIG. 2)
It is necessary to judge whether there is register interference between the register 21) and the register 21). This is because it is possible that the second instruction is executed by using the value of the register at the timing 32 after performing the write operation (= timing 32) to the register by executing the first instruction. This is because the timing of reading the first instruction is earlier than the timing of writing the first instruction to the register, and thus the result of the first instruction may not be reflected in the second instruction. However, at timing 33 and timing 32, it is impossible to determine the register interference temporally. Write 3-1 at timing 32 and R at timing 34
Since the ead 3-1 uses the same address, the register interference is determined at the timing 33 and the timing 34. Therefore, the bus 1 and the bus 3 are the targets of the address comparison. Therefore, in FIG. 5, the buses 1 and 3 are input to the comparator 12 of the address comparator 11, and the bus 1 address generator 5 and the bus 3 address generator 7 generate and
The output address data values are compared, and if the address data match, “1” is output to the AND circuit 160.
On the other hand, if the register file numbers are different, register interference does not occur even if the register names match. Therefore, at the switching timing of the register file, the register file number is always different before and after the switching, so that the register interference does not occur. Since register interference does not occur even if the register numbers are the same, the register file selector 30 outputs the register file switching signal 30 that becomes “0” at the timing of switching the register files and “1” at the timing of not switching the register files. It is input to the AND circuit 160 of the address comparison unit 31. The AND circuit 160 outputs the address output delay signal 16 to the bus 1 address generation unit 5 only when the address data match and it is not the timing of register file switching, and the bus 1 address generation unit 5 receives this and outputs it to the bus 1. The address output timing of is shifted backward so that register interference does not occur. 6, at timing 33, register 1 of register file number 1 is read, and at timing 34, register file number 3 is read.
Register 1 is being read. In this case, the register numbers match but the register file numbers do not match.
No register interference has occurred, and the reading of the register 1 at the timing 33 is performed as it is. In FIG. 7, the register 1 of the register file number 3 is read at the timing 35, and the register 1 of the register file number 3 is also read at the timing 36. In this case, since both the register number and the register file number match, register interference has occurred and timing 3
The reading of the register 1 at 5 is performed at timing 37 with a delay of one cycle. In the case of a single register file, the register interference shown in FIG. 7 frequently occurs, and it is necessary to avoid it. When the tasks are configured to be processed in parallel, register interference cannot be determined only by comparing the register numbers as shown in FIG. 6, and by comparing the register file numbers, the true register file interference occurs. Only by performing the register interference avoiding operation (the reading of the register shown in FIG. 7 is delayed by one cycle), the disturbance of the pipeline can be suppressed to the minimum.

[0040]

According to the configuration of the present invention, register interference avoidance by re-execution is executed only when there is a true register interference in a plurality of register file configurations.
It is possible to realize a system with high execution efficiency, which minimizes the disturbance of the pipeline.

[Brief description of drawings]

FIG. 1 is a block diagram of a register interference avoidance device for judging register interference based on a register file number and a register number according to the present invention.

FIG. 2 is a register file configuration diagram of a register interference avoidance device of the present invention.

FIG. 3 is a timing chart of execution of a register interference avoidance device for judging register interference based on a register file number and a register number of the present invention.

FIG. 4 is a timing chart of execution of a register interference avoidance device for judging register interference based on a register file number and a register number of the present invention.

FIG. 5 is a block diagram of a register interference avoidance device provided with a flag indicating a register file switching timing according to the present invention.

FIG. 6 is an execution timing chart of a register interference avoidance device provided with a flag indicating a switching timing of a register file of the present invention.

FIG. 7 is an execution timing chart of the register interference avoidance device provided with a flag indicating the switching timing of the register file of the present invention.

[Explanation of symbols]

 1-4 bus 5-8 bus output address generation unit 9 address generation unit 10 register file 11 address comparison unit 12, 13 comparator 14, 15 register file number 160 AND circuit 16 address output delay signal 17 register file selection unit 18-22 Register 29 Register file selection unit 30 Register file switching signal 31 Address comparison unit

Claims (2)

[Claims] 1. A single CPU is occupied by a plurality of register files, a plurality of tasks are concurrently processed by the plurality of register files, and instructions are executed by pipeline processing, and an instruction currently being executed. There is pipeline processing timing at which the reading from the register by the instruction to be executed next is already completed at the timing of writing to the register, and the register written by the currently executing instruction and the instruction to be executed next. If the register being read has the same register name and the register files being used are the same, the reading from the register by the instruction to be executed next is interrupted, and the instruction currently being executed is After writing in
The first means for re-executing the next instruction, the register written by the currently executing instruction and the register read by the next instruction to be executed have the same register name, but the register file used is the same. If not, the register interference avoiding device further comprises second means for executing reading from the register according to the instruction to be executed next. 2. A CPU is occupied by a plurality of register files, the plurality of register files are configured to perform a plurality of tasks in parallel, and one register file is selected from the plurality of register files. Then, a flag indicating the switching timing of the register file when occupying one CPU is provided, the instruction is executed by pipeline processing, and the instruction is executed next when the instruction currently being executed is written to the register. When there is a pipeline processing timing in which the reading from the register by the instruction is already completed, and the register written by the currently executing instruction and the register read by the next executed instruction have the same register name,
The flag indicating the switching timing of the register file is referred to as to whether the reading from the register by the instruction to be executed next is interrupted or continuously executed, and if the switching timing of the register file is set, the instruction execution is continued. Register interference avoidance, comprising: first means and means for re-executing the next instruction to be executed after the currently executing instruction writes a register unless it is the timing of switching the register file. apparatus.