JPS58181155A - Storage device of state history - Google Patents

Abstract

PURPOSE:To use effectively a state history storage circuit, by providing two specific bit patterns in a micro instruction word and registering again the address of the micro instruction word to the state history storage circuit when one of these patterns is detected. CONSTITUTION:A micro (mu) instruction word stored in a mu instruction word memory 12 is provided with the first and the second specific patterns. The mu instruction word in the memory 12 is read out by the address designated by a mu instruction word read address circuit 11. In this case, when specific patterns are not detected by a pattern detecting circuit 13, the address designated by the circuit 11 is transferred to the position, which is designated by an address register 30, of a state history recording circuit 20. When the first specific pattern is detected by the circuit 13, contents of the register 30 are saved in an address buffer 22; and when the second specific pattern is detected, contents of the buffer 22 are stored again in the register 30 through a selecting circuit 33, and the address of the mu instruction word is registered in the circuit 20.

Description

DETAILED DESCRIPTION OF THE INVENTION (Description of the Technical Field) The present invention relates to a state history storage device for operation tracing that stores the history of internal states of an information processing device point by point.

(Description of Prior Art) Conventionally, this type of state history storage device, as shown in FIG. 1, includes an instruction execution control circuit 10, a state history storage circuit 20, an internal state information register 32, an address register 30,
It is established from the address counter 31. various timings,
For example, for each firmware step, the instruction execution control circuit 1
The contents output from 0 to the internal state information register 32 and stored are output to the state history storage circuit 20. At this time, the specified write address of the state history storage circuit 20 is given by the address register 30, and each time the contents of the internal state information register 32 are stored in the state history storage circuit 20, the contents of the address register 30 are stored in the counter. 31 is incremented by 1 and is set to point to the next address stored immediately before. Therefore, the internal state information is stored in the state history storage circuit 20 sequentially from the lowest address to the highest address. By storing internal state information in this manner, when a fault occurs, the internal state information stored inside the state history storage circuit 20 is retrieved and used for troubleshooting. However, since the storage capacity of the state history storage circuit 20 is limited, after storing the internal state information up to the highest address of the state history storage circuit 20, the address register 30 again stores the lowest address of the state history storage circuit 20. specify. Furthermore, when the state information is stored at the lowest address, the address register 30 specifies the next address by the action of the counter 31, so the internal state information stored in the state history storage circuit 20 is The data will be rewritten sequentially starting from the lowest address. Therefore, in operation tracing where internal state information is stored in the state history storage circuit 20 one by one for each instruction step in firmware, a step loop in the same firmware is executed many times by waiting for the next instruction. If so, all step information regarding that firmware is stored. Therefore, since such redundant information is included when a failure occurs, there is a drawback that useful information may be lost.

(Detailed Description of the Invention) The object of the present invention is to provide a state history storage circuit, an address register, an address counter, an address buffer, a micro-instruction word memory, a micro-instruction word read address circuit, a selection circuit, and a pattern detection circuit. It is an object of the present invention to provide a state history storage device which is equipped with a direction path, eliminates the above-mentioned drawbacks, and is configured to effectively utilize a state history storage circuit.

(Description of structure and operation of the invention) The state history storage device according to the present invention is for use in an information processing device controlled by a microinstruction word, and includes a state history storage circuit, an address register, an address counter, and an address register. a buffer, a microinstruction word memory, a microinstruction word read address circuit, a selection circuit,
This configuration includes a pattern detection circuit. The state history storage circuit stores and registers the internal state information of the information processing device one by one. The address register specifies at which address in the state history storage circuit internal state information is to be stored, using address information expressed as serial information. The address counter increments the contents of the address register by one. The address buffer is
It is used to temporarily save the contents of the address register.

The micro-instruction word memory stores micro-instruction words. The microinstruction word read address circuit is for reading microinstruction words from the microinstruction word memory. The selection circuit selects either the address buffer output or the address counter output. The pattern detection circuit detects first and second specific patterns from the microinstructions stored in the microinstruction memory. When the first specific pattern is detected from the microinstruction word, the contents of the address counter are directly saved in the address buffer, and when the second specific pattern is detected, the contents of the address counter are stored again in the address register. As a result, state history information is registered in the state history storage circuit.

(Description of Embodiment) As an embodiment of the state history storage device according to the present invention, a microinstruction word address history storage device will be described with reference to the drawings.

FIG. 2 is a block diagram of a state history storage device for microinstruction word addresses according to the present invention. In FIG. 2, a state history storage device 1Fi micro-instruction word memory 12. Microinstruction word read address circuit 11, pattern detection circuit 1
3. state history storage circuit 20, address register 3G,
Address counter 31, address buffer 22. This configuration also includes a selection circuit 33. Micro-instruction word memo January 2 stores micro-instruction words.

Microinstruction word read address circuit 11Fi Instructs an address for reading a microinstruction word from inside the microinstruction word memory 12. The specific bit pattern is included in the microinstruction word read from the address specified by the microinstruction read address circuit 11, and the pattern detection circuit 13 detects this specific bit pattern. The state history storage circuit 20 stores the addresses designated by the microinstruction word read address circuit 11 one by one. Address register 3oFi specifies the address to be stored in the state history storage circuit 20. Each time the contents of the microinstruction read address circuit 11 are stored in the state history storage circuit 20, the address counter 31 increments the contents of the address register 30 by one.

The first specific bit pattern detected by the address buffer 22Fi pattern detection circuit 13 is used to save the contents of the address register 30. The selection circuit 33 selects the contents of the address counter 11 or the address buffer 2.
Select one of the contents of 2 and enter the address register 30.
The write address of the state history storage circuit 20 is transferred to the state history storage circuit 20.

FIG. 3 shows an example of the structure of a microinstruction word used in the state history storage device 1 of FIG. 2. The first or second specific bit pattern is detected by the pattern detection circuit 13. The first specific bit pattern specifies that the write address of the state history storage circuit 20 is transferred from the address register 30 to the address buffer 22 and stored therein.

The second specific bit pattern is the address buffer 22 (D
The contents are designated to be transferred to the address register 3° via the selection circuit 11 and stored therein. Although these first or second specific bit patterns are placed at the lowest level of the microinstruction word, they may be defined within the function definition field or within other fields.

FIG. 4 is a timing diagram showing the operation timing relationship of the state history storage device 1 shown in FIG.

In FIG. 4, Sl is the output of the microinstruction word read address circuit 11, Sl is the microinstruction word read out from the microinstruction word memory 12, and 83#'i is the signal detected by the pattern detection circuit 13. 53-1 is a signal applied to the address buffer 22, and 53-2 is a signal applied to the selection circuit 33. Further, 84 indicates the output of the address register 30, and S5 indicates the contents of the address buffer 22. In FIG. 4, the microinstruction word C stored at address C is stored in the address buffer 22.
Assume that a first specific bit pattern for transferring the contents of the hair address register 30 is included. Also,
Assume that the microinstruction word e stored at address E includes a second specific bit pattern for transferring the contents of address buffer 22 to address register 30.

Furthermore, the microinstruction word d stored at address D is
The execution sequence of a microinstruction word specifies a wait for synchronization with an external circuit that operates asynchronously, and after executing this microinstruction, the microinstruction word e is further executed by a conditional branch.

It branches to either f. Other address A.

B, C, E, FK stored microinstruction word a.

bl cl elf specifies an operation that does not wait for synchronization for an external circuit that is operating asynchronously with the execution sequence of the microinstruction word.

FIG. 5 is a book showing the storage status of microinstructions in the timing diagram shown in FIG. 4.

The detailed operation will be described below with reference to FIG. 5, based on the block diagram of the embodiment shown in FIG. 2, the microinstructions shown in FIG. 3, and the timing diagram shown in FIG. 4. The microinstruction M& stored in the p microinstruction memory 12 is read by the microinstruction address A specified by the microinstruction read address circuit 11.

It is not possible to input this microinstruction word a to the pattern detection circuit 13 and detect the fourth λ or the second specific bit pattern. Therefore, when a microinstruction address is stored in the state history storage circuit 20, the address A specified by the microinstruction read address circuit 11 is transferred and stored at the address position specified by the address register 30. The address information stored in address register 30 is incremented by one via address counter 31. Since the microinstruction word a is not an instruction to wait for a dangerous external circuit in synchronization with the microinstruction word, the microinstruction read address circuit 11 reads the next microinstruction word address specified by the microinstruction word a. Specify B. This address exists within the microinstruction word memory 12. In the next execution step, the microinstruction word is read from the microinstruction word memory 12. Pattern detection circuit 1 for microinstruction
Since the first or second specific bit pattern to be detected in step 3 does not exist, the state history storage circuit 20 transfers the address B to the address position designated by the address register 30 and stores it therein. Furthermore, since the microinstruction Hb is not an instruction for waiting with an external circuit that operates asynchronously with the microinstruction word execution sequence, the microinstruction word read address circuit 11 uses the next microinstruction word specified by the microinstruction word Specify the microinstruction word address C. This address exists within the microinstruction word memory 12. In the next execution step, microinstruction word C is read from microinstruction word memory 12. This microinstruction word C includes a specific bit pattern to be detected by the pattern detection circuit 13. Therefore, the state history storage circuit 2 newly specified by the address register 30
1 address C is transferred to the internal address of 0 and stored. At this time, since the address register 30 does not take in information from the address buffer 22, the address specified by the address counter 31 becomes the write address, and the microinstruction word address C is transferred and stored in the state history storage device 20. . Similarly, microinstruction word address D is set as the next address of microinstruction word + 3.
is designated by the microinstruction word read address circuit 11. The micro-instruction word d read from the micro-instruction word memory 12 waits with an external circuit asynchronous to the micro-instruction word execution sequence. This microinstruction @
At step d, one step, which is the unit of execution of a microinstruction word, is waited for. However, since the state history storage circuit 20 stores the delayed microinstruction word address,
The same microinstruction word address D for two steps is transferred and stored in the state history storage circuit 20.

Next, if the waiting with the asynchronous external circuit is completed by the execution of this microinstruction word d, but the conditional branch is not established, the microinstruction word e specified by the next microinstruction word address E is executed. The microinstruction word memory 12 is read out. Since this microinstruction word e includes the 1t-th or second specific bit pattern to be detected by the pattern detection circuit 13, the address register 30
The contents of the address buffer 22 are replaced with the contents of the address buffer 22.

From timing t1 to timing t1, the macro instruction word address is stored in the state history storage circuit 2 in this way.
However, the conditional branch is established when the microinstruction d is executed at timing t1 and the waiting with the asynchronous external circuit is completed, so the control branches to the microinstruction address F. go. The operation timing after this is the same as the operation timing described above. As explained above, in the state history storage circuit 20, microinstructions of 15 steps from timing to to timing t14 are sent out and executed. Also, tie ink 1. ~tl, timing t6~t7. A loop of the same microinstruction word is executed at each of the three timings when the timing tlOxtll is satisfied. However, in spite of this, the microinstruction word address A is stored in the state history storage circuit 20.

B and C are stored three times each, microinstruction word address D is stored twice, and microinstruction word address F and G are stored once each, including the number of loops. Since the loop consists of three steps C, D, and E in the microinstruction word address, the storage status of the state history storage circuit 20 does not seem to have changed much, but the microinstruction word loop is It is certain that the four methods are effective when the number of steps is larger.

(Detailed Description of the Invention) In the present invention, as explained above, the microinstruction word is provided with first and second specific bit patterns unique to the microinstruction word, and when one of the specific patterns is detected, the state history The micro-instruction word address in the storage device is configured to be incremented and returned to the previous address to restart execution of the instruction, thereby reducing redundancy when a loop due to waiting occurs. This has the advantage that the number of addresses can be kept to a minimum, and the number of steps of a looped microinstruction word can also be stored at the same time.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an example of a state history memory 133... selection circuit storage device configured according to the prior art, FIG. 2 is a block diagram of an embodiment of the state history storage device according to the present invention, and FIG. 4 is a diagram showing an example of the structure of a microinstruction executed in the embodiment of FIG. 2, and FIG. FIG. 5 is a diagram showing an example of the closing timing, and is related to FIGS. 1 to 4, and is a diagram showing an example of the structure of contents stored in the state history storage device of the embodiment shown in FIG. 2. It is. 1... State history storage device j 10... Instruction execution control circuit 12... Micro instruction word memory 11, contention, micro instruction word read address circuit 13...
-Pattern detection circuit 20...Fist status history storage circuit 22@...Address buffer 30...Address register 31@...Address counter 32...Internal status information register holder Patent applicant NEC Corporation Agent Patent attorney Inoro Jusai illustration 1

Claims (1)

[Claims] A state history storage device for use in an information processing device controlled by a microinstruction word includes a state history storage circuit for storing and registering internal state information of the information processing device one by one; an address register for specifying at which address the internal state information is to be stored using serial information; and an address counter for incrementing the contents of the address register by 1;
an address buffer for temporarily saving the contents of the fmm child address counter; a microinstruction word memory for storing the microinstruction word; and a microinstruction word memory for reading the microinstruction word from the microinstruction word memory. an instruction word read address circuit; a selection circuit for selecting either the output of the address buffer or the output of the address counter; a pattern detection circuit for detecting a specific pattern of the micro-instruction word; when the first specific pattern is detected from the microinstruction word, the content of the address register is directly saved to the address buffer; A state history characterized in that when a specific pattern is detected, the address of the microinstruction word is registered in the state history storage circuit by re-storing the contents of the address buffer into the address register via the selection circuit. Storage device.