JPS58181156A - Storage device of state history - Google Patents

Abstract

PURPOSE:To use effectively a state history storage circuit, by selecting address contents to be stored in the state history storage circuit in accordance with detection of two specific patterns provided in a micro instruction word. CONSTITUTION:A micro (mu) instruction word is read out from a mu instruction word memory 12 in accordance with an address from a mu instruction word read address circuit 11. Internal status information designated by the memory 12 is stored successively in a state history storage circuit 20. In this case, when the first specific pattern included in the mu instruction word is detected by a pattern detecting circuit 13, contents of an address register 30 which designates the address of the circuit 20, where state information should be stored, with parallel information are saved in an address buffer 22 after they are increased in an address counter 31 by one. When the second specific pattern of the mu instruction word is detected by the circuit 13, contents of the buffer 22 are stored again in the register 30. A selecting circuit 33 selects contents of the counter 31 or the buffer 22 in accordance with the first and the second pattern detected by the circuit 13 and stores them in the register 30.

Description

DETAILED DESCRIPTION OF THE INVENTION (Description of Technical Field) The present invention relates to a state history storage device that stores state history point by point in order to trace operations in an information processing device.

(Description of Prior Art) The configuration of a conventional state history storage device is shown in FIG. In FIG. 1, the interior of the state history storage device 1 consists of an instruction execution control circuit 10, a state history storage circuit 20, an internal state information register 32, an address register 30, and an address counter 31. The address register 30 specifies the address of the state history storage circuit 20, and the address counter 31 increments the address by 1 and supplies it to the address register 30.

Contents output from the instruction execution control circuit 10 for each step such as a firmware step are once stored in the internal state information register 32 and then output to the state history storage circuit 20. At this time, the write address of the state history storage circuit 20 is given by the address register 30, and each time the contents of the internal state register 32 are transferred to the state history storage circuit 20 and stored in the state history storage circuit 20. Then, the contents of the address register 30 are incremented by one by the address counter 31. Therefore, the address register 30 is set to indicate the next write address, and the internal state information is stored in the state history storage circuit 20 sequentially from the lower address to the higher address. Since the internal state information is stored in this manner, when a failure occurs, the internal state information stored inside the state history storage circuit 20 is increased and used as a countermeasure for failure handling. However, since the storage capacity of the state history storage circuit 20 is limited, after storing the internal state information up to the highest address of the state history storage circuit 20, the address register 30 again stores the lowest address of the state history storage circuit 20. specify. Further, when the status information is stored at the lowest address, the address register 30 specifies the next address using the address counter 31. Therefore, the internal state information stored in the state history storage circuit 20 is sequentially rewritten starting from the lowest address. Therefore, in an operation trace in which internal state information is stored in the state history storage circuit 20 one by one for each instruction step in the firmware, the step loop in the same 77-Aware is repeated many times by waiting for the next instruction. If the firmware step is being executed, step information regarding that firmware step is stored in the state history storage circuit 20. When a failure occurs, since the state history storage circuit 20 is filled with such redundant information, there is a drawback that valid state information is lost.

(Detailed Description of the Invention) The object of the present invention is to provide a state history storage circuit, an address register, an address counter, an address buffer, a micro-instruction word memory, a micro-instruction word read address circuit, a 2-selection circuit, and a pattern detection circuit. It is an object of the present invention to provide a state history storage device which is equipped with a circuit, eliminates the above-mentioned drawbacks, and is configured to effectively utilize the state history storage circuit.

(Description of structure and operation of the invention) The state history storage device according to the present invention is for use in an information processing device controlled by a microinstruction word, and includes a state history storage circuit, an address register, an address counter, and an address register. a buffer, a micro-instruction word memory, a micro-instruction word read address circuit, and a 1 selection circuit;
This configuration includes a pattern detection circuit. The state history storage circuit stores and registers the internal state information of the information processing device one by one. The address register specifies at which address in the state history storage circuit internal state information is to be stored, using address information expressed as parallel information. The address counter increments the contents of the address register by one. The address buffer temporarily saves the contents of the address counter. The micro-instruction word memory stores micro-instruction words.

The microinstruction word read address circuit is for reading microinstruction words from the microinstruction word memory.

The selection circuit selects only the value obtained by incrementing the contents of the address register by 1, and selects either the output of the address buffer or the output of the address counter. The pattern detection circuit detects first and second information from the microinstruction word stored in the microinstruction word memory.
This is to detect a constant turn. When the first specific pattern is detected from the microinstruction word, the contents of the address register are incremented by 1, then saved to the address buffer, and the second specific pattern is detected. Then, the contents of the address buffer are stored in the address register again. As a result, the state history information is stored and registered in the state history storage circuit.

(Explanation of Examples) Next, the present invention will be explained in detail with reference to the drawings.

A block diagram of one embodiment of a state history storage device according to the present invention is shown in FIG. In FIG. 2, a microinstruction word address state history storage device IFi state history storage circuit 20 and an address register 30.

An address counter 31, an address buffer 22 and a 2 selection circuit 33, a microinstruction word memory 12, and a microinstruction word read address circuit 11.

The pattern detection circuit 13 is configured to include a pattern detection circuit 13. The state history storage circuit 20 includes the microinstruction word memory 12
The address specified by is stored one by one. The address register 30 is the state history storage circuit 20
Indicates the write address. Each time the contents of the microinstruction @read address circuit 11 are transferred to the address counter 31 and the state history storage circuit 20 and stored, the address register 3
Increment the contents of 0 by 1. The address buffer 22 is
In accordance with the first-straddling second specific bit pattern detected by the pattern detection circuit 13,
The contents of 0 are incremented by 1 by the address counter 31 and saved. The selection circuit 33 selects either the contents of the address counter 31 or the contents of the address buffer 22 according to the first or second specific bit pattern detected by the pattern detection circuit 13, and stores the selected contents in the address register 30. This is a gate for storing the write address of the state history storage circuit 20. Micro-instruction word memory This is a memory for storing 12 micro-instruction words. The micro-instruction word read address circuit 11 specifies an address for reading a micro-instruction word from the micro-instruction word memory 12. The pattern detection circuit 13 detects the first or second specific bit pattern contained in the microinstruction word read from the microinstruction word memory 12 according to the address specified by the microinstruction word read address circuit 11. .

In the state history storage device shown in FIG.
Micro-instruction words as shown in the figure are stored in the micro-instruction word memory 12. As explained above, FIG. 3 is a block diagram showing an example of a microinstruction word, and the microinstruction word is made up of a function definition field, a synchronization field, a constant field, a next address field, and a specific bit. The first or second specific bit pattern is detected by the pattern detection circuit 13. The first specific bit pattern specifies that the write address of the state history storage circuit 20 is transferred to the address buffer 22 and stored therein. The second specific bit pattern is the address buffer 22
The contents of the address register 30 are designated to be transferred to the address register 30 via the selection circuit 33 and stored therein. Although these first or second specific bit patterns are placed at the lowest position of the microinstruction word, they may be placed in the function definition field or in any other field.

FIG. 4 is a diagram showing the timing relationship of operations in the state history storage device shown in FIG. 2. In Figure 4, 51
fl Microinstruction word read address circuit 11 output, S
2 is a microinstruction word read out from the microinstruction word memory 12, S3 is a signal detected by the nosit turn detection circuit 13, and 53-1 is the address buffer 22.
A signal 83-2 is a signal applied to the selection circuit 33. Further, S4 indicates the output of the address register 30 and the contents of the S5U address buffer 22. In FIG. 4, it is assumed that the microinstruction word C stored at address C includes a first specific bit pattern for transferring the contents of the address register 30 to the address buffer 22. Further, the microinstruction word e stored at address E is stored in the address buffer 22.
Assume that a second specific bit pattern is stored for transferring the contents of address register 30 to address register 30. The microinstruction word d stored at address D specifies a wait for synchronization with an external circuit that operates asynchronously with the execution sequence of the microinstruction word. Microinstruction @@ by branch with
, i. Others, address A,
Micro instruction words a, b, c stored in B, C, E, F
, e, and f specify an operation that does not wait for synchronization with an external circuit that is operating asynchronously with the execution sequence of the microinstruction word.

FIG. 5 shows the storage status of micro-instructions stored in the state history storage device, and corresponds to the embodiment of FIG. 2, the micro-instructions of FIG. 3, and the fourth timing diagram. . Below, with reference to Figures 2 to 4,
The operation of the state history storage device will now be described with reference to the figures. Here, the state history storage device is based on the embodiment shown in FIG. 2, and it goes without saying that the microinstructions shown in FIG. 3 are executed at the timing shown in FIG. 4.

A microinstruction @a stored in the microinstruction memory 12 corresponding to the microinstruction address A designated by the microinstruction read address circuit 11
is read out. Even if this microinstruction word a is input to the pattern detection circuit 13, the pattern detection circuit 13 cannot detect the first and second specific bit patterns. Therefore, the address A specified by the microinstruction@read address circuit 11 is transferred and stored at the internal address of the state history storage circuit 20 specified by the address register 30. The contents of this address register 30 are then incremented by one by the address counter 31. Since the microinstruction word a is not an instruction to wait for an external circuit that is not synchronized with the microinstruction execution sequence, the microinstruction read address circuit 11 reads the next microinstruction word specified by the microinstruction color. Address B is designated inside the microinstruction word memory 12. In the next execution step, the microinstruction word is read from the microinstruction word memory 12. In the microinstruction @b, there is no first or #- or second specific bit pattern to be detected by the pattern detection circuit 13.

Therefore, the address B is transferred and stored at the internal address of the state history storage circuit 20 designated by the address register 30. Furthermore, microinstruction 5bti
Since this is not an instruction that waits between the microinstruction word execution sequence and an external circuit that operates asynchronously, the microinstruction read address circuit 11 reads the microinstruction @b.
The next micro-instruction address C specified by is designated inside the micro-instruction memory 12. In the next execution step, the microinstruction word C is stored in the microinstruction word memory 12.
is read out. The microinstruction word C has a first or second specific bit pattern to be detected by the pattern detection circuit 13. Therefore, the address C is transferred and stored at the address inside the state history storage circuit 20 newly designated by the address register 30. At this time, since the address register 30 does not take in information from the address buffer 22, the address specified by the address counter 31 becomes the write address υ, and the microinstruction word address C is stored in the state history storage circuit 20. Similarly, the microinstruction word address D is instructed to the microinstruction read address circuit 11 as the next address of the microinstruction word C. The micro-instruction word d read from the micro-instruction word memory performs a wait between the micro-instruction word execution sequence and an asynchronous external circuit. This microinstruction word d waits for one step, which is the execution unit of the microinstruction word. However, since the state history storage circuit 20 stores microinstruction word addresses one by one, the same microinstruction word address D of two steps is transferred and stored in the state history storage circuit 20. Next, if the waiting with the asynchronous external circuit is completed by executing this microinstruction word d, but the conditional branch is not established, the next microinstruction word address E
The microinstruction word e designated by is read out from the microinstruction word memory 12. Since this microinstruction @e includes a first-straddle second specific bit pattern to be detected by the pattern detection circuit 13, it instructs to fetch the contents of the address buffer 22 via the address register 30. be done.

Therefore, the contents of the address register 30 are replaced with the contents of the address buffer 22. The microinstruction word address is stored in the state history storage circuit 20 in this way from timing 1 to timing t1m, but when the microinstruction word d is executed at timing t12 and the waiting with the asynchronous external circuit is completed. Since a conditional branch is established in , the program branches to microinstruction word address F. Thereafter, the execution timing is the same as described above.

As explained above, in the state history storage circuit 20, the microinstruction word is sent out and executed during the period of 15 steps from timing to to timing t14.
Timing 1. ~ts, timing t6~t9. A microinstruction word loop of the same format is executed at each of the three timings established from the timing tto -tlm. However, in spite of this, the state history storage circuit 20 stores the microinstruction address A, B, and C three times each, the microinstruction address D twice, and the microinstruction address F.
, G are stored once each, including the number of loops.

Since the loop consists of three steps C, D, and E using microinstruction word addresses, the state history storage circuit 2
0 storage situation #-1: Although it does not seem to have changed much, it is certain that Kenpo is effective if the micro-instruction word loop is established with a larger number of steps.

(Detailed Description of the Invention) In the present invention, as explained above, each microinstruction word has first and second specific bit patterns, and when one of the specific patterns is detected, one state history is detected. Since the structure is such that it is possible to restart the execution of the instruction by returning the address of the microinstruction word in the storage device to the state before it was incremented, redundant addresses can be saved when a loop due to waiting K occurs. The number of steps of the looped microinstruction word can be stored at the same time in the state history storage device.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of a state history storage device constructed according to the prior art. FIG. 2 is a block diagram of one embodiment of a state history storage device according to the present invention. FIG. 3 is a diagram showing an example of the structure of a microinstruction word executed in the embodiment of FIG. 2. FIG. 4 shows that the state history storage device according to the embodiment of FIG.
FIG. 3 is a diagram illustrating an example of the timing of execution by a microinstruction word having the configuration shown in the figure. FIG. 5 is a diagram showing an example of the structure of contents stored in the state history storage device of the embodiment shown in FIG. 2, relating to FIGS. 1 to 4. FIG. 1.Φ.State history storage device 10@...Instruction execution control circuit 12...Microinstruction word memory 11...Microinstruction word read address circuit 13...
・Pattern detection circuit 20...Status history storage circuit 22...Address buffer 30...Address register 31Φ・Koma address counter 32...Internal status information register 33...Selection circuit Patent applicant) NEC Co., Ltd. Type 1 company agent Patent attorney Inoro Hisashi 1st figure 2nd figure 2nd figure Monen〒■11 ears■enemy]

Claims (1)

[Claims] A state history storage device for use in an information processing device controlled by a microinstruction word includes a state history storage circuit for storing and registering internal state information of the information processing device one by one; an address register for specifying at which address the internal state information is to be stored using parallel information; and an address counter for incrementing the contents of the address register by 1;
an address buffer for temporarily saving the contents of the address counter; a microinstruction word memory for storing the microinstruction word; and a microinstruction word memory for reading out the microinstruction word from the microinstruction word memory. a micro-instruction word read address circuit, and selecting either the contents of the address buffer or the contents of the address counter;
a selection circuit for supplying only contents incremented by 1 from the contents of the address register to the address register; and a selection circuit for supplying first and second specific patterns from the microinstructions stored in the microinstruction word memory. a pattern detection circuit for detecting the pattern, and when the first specific pattern is detected from the microinstruction word, the content of the AT1/S register is incremented by 1 and then saved in the address buffer; A state history storage device characterized in that when the second specific pattern is detected, the address of the microinstruction word is registered in the state history storage circuit by re-storing the contents of the address buffer into the address register. .