JPS5852261B2 - Program processing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a program processing method in, for example, a small electronic computer.

In general, small electronic calculators, especially electronic desktop calculators (hereinafter referred to as calculators), usually perform a series of calculations using a fixed program installed in advance. For this reason, so-called programmable calculators, in which predetermined programs can be written as needed, are being put into practical use.

However, calculators generally do not have a large storage capacity, and calculators with programs are no exception.

Therefore, the program storage area of a programmable calculator must be used efficiently.

However, in conventional programmable calculators, the functions are clearly differentiated between a so-called main routine that executes a series of operations and a so-called subroutine that executes, for example, basic operations, and a subroutine is a part of the main routine. Since subroutines are used only as part of routines, it was not possible to use subroutines as if they were main routines.

That is, although it is possible to call and use a subroutine from a main routine, it is not possible to call a main routine from a subroutine.

For this reason, the subroutine cannot be used as if it were a main routine, and the write area for the main routine decreases by the amount of writing of the subroutine, resulting in various drawbacks such as inability to use the program storage area efficiently.

The present invention has been made in view of the above points, and it does not require fixed functions of main routines and subroutines in each written program, but allows the program to be used even when the main routine and subroutines are changed. It is an object of the present invention to provide a program processing method that is flexible and extremely efficient in using program storage areas.

An embodiment of the present invention will be described below with reference to the drawings.

As shown in FIG.
The program designated by the control section is the main routine, and the program designated by another program is the subroutine.

Furthermore, when each of the programs Prl to PrN becomes a subroutine due to the designation of another program, the designation of the subroutine is stored.

Then, when the processing of a unit program is finished, it is determined whether or not it is used as a subroutine. If it is used as a subroutine, the program jumps back to the main routine, and if it is not a subroutine, the program performs the operation of the main routine. The operation is terminated as if it had been executed, and the details will be explained below.

In FIG. 2, reference numeral 1 denotes a program memory, which stores a plurality of programs without distinguishing between main and sub programs as described above.

This program memory 1 is addressed by an address counter 2, and the contents of the program at the designated address are transferred to a buffer register 5 via AND circuits 3 and 4.
, 6.

The AND circuits 3 and 4 are gate-controlled by a flip-flop 7, and the output of the flip-flop 7 is applied to the AND circuit 3 via an inverter 8, and the output of the flip-flop 7 is applied directly to the AND circuit 4. It will be done.

Thus, the output of the buffer register 5 is sent to a code conversion circuit 9 that converts the subroutine designation code 5ubN into a program designation code PrN, and is also sent to the decoder 10.
sent to.

The output of the code converting circuit 9 is sent to the matching circuit 11 together with the output of the buffer alexisco, and the output of this matching circuit 11 is applied to one input terminal of the AND circuit 12 as a gate signal.

A clock pulse φe is applied to the other input terminal of the AND circuit 12, and the output of the AND circuit 12 is sent to the flip-flop 7 as a reset signal.

Further, the decoder 10 is operated by an execution instruction output from a control section (not shown) and decodes a subroutine designation code Sub, an end code END, etc. included in the contents of the program given from the buffer register 5. If the code is input, it will be sent to output line 10a.
1” signal, output line 10 if END code is input
Outputs a "1" signal to b.

The signal output from the decoder 10 to the output line 10a is sent to a flip-flop 13 which operates in synchronization with the clock pulse φe, and the output of this flip-flop 13 is applied to the set terminals S of the flip-flops I and 14.

The output of the flip-flop 7 is applied to one input terminal of the AND circuit 16 via the OR circuit 15 together with the execution instruction ◆.

A clock pulse φe is applied to the other input terminal of the AND circuit 16, and the output of the AND circuit 16 is sent to the address counter 2 as a count-up signal.

On the other hand, the output of the flip-flop 14 is applied directly to an AND circuit 17 and also to an AND circuit 18 via an impark 19.

Further, the AND circuits 17 and 18 are supplied with a signal output from the decoder 10 to the output line 10b, and the AND circuit 18
The output is sent to the control section as a program end signal.

The output of the AND circuit 17 is applied to the reset terminal H of the flip-flop 14 via a flip-flop 20 operating in synchronization with the clock pulse φe, and is also sent to the address counter 2 as a write command signal via an OR circuit 21.

In response to this write command signal, the address counter 2 writes the contents of the address given from the address memory 22 via the AND circuit 23.

Further, the contents of the address counter 2 are transferred to the address memory 22 via an AND circuit 24 gate-controlled by the output of the flip-flop 13.

Further, the output of the flip-flop 13 is output from the OR circuit 2.
1 and is also applied to the AND circuit 23 via the inverter 25.

Next, the operation of the present invention configured as described above will be explained with reference to the flowchart shown in FIG.

Now, the above execution command is passed through the OR circuit 15 to the AND circuit 16.
When the clock pulse φe is applied to the address counter 2, its gate is opened and the clock pulse φe is sent to the address counter 2, and its contents are sequentially counted up.

As the counter 2 counts up, the contents of the program are sequentially read out from the program memory 1 and stored in the buffer register 5 via the AND circuit 3.

Therefore, a desired program can be designated by sending the contents read into the buffer register 5 to the control section and comparing it with the designated program number.

Now, for example, as shown in FIG.
1 is designated as the main program, the contents of the address counter 2 are sequentially counted up according to the execution command given to the AND circuit 16 via the OR circuit 15, and the contents of the program are sequentially output from the program memory 1 to execute a predetermined program. processing is executed.

Therefore, during the execution of program Prl, at a certain step, another program, for example Pr2, changes to subprogram 5ub2.
, this 5ub2 designation code is first stored in the buffer register 6 via the AND circuit 3.

The 5ub2 designation code stored in the buffer register 5 is sent to the code conversion circuit 9, converted into a program Pr2 designation code, and sent to the decoder 1o.

This decoder 10 operates according to the above execution command and outputs a "1" signal to the output line 10a when the sub code is input.

The signal output to this output line 10a is read into the flip-flop 13 in synchronization with the next clock pulse φe,
(2) The output of the flip-flop 13 delayed by one period sets the flip-flop 7, and at the same time, the flip-flop 14 (S) is set as shown in step A of FIG.

Then, by setting the flip-flop 7, the gate of the AND circuit 4 is opened, and the inverter 8 is opened.
The output of becomes "0" and the gate of the AND circuit 3 is closed.

Further, the output of the flip-flop 13 is applied to an AND circuit 24 to open the AND circuit 24 and transfer the contents of the address counter 2 to the address memory 22.

At this time, the contents of the address counter 2 are advanced by "1" from the address that specified the subroutine 5ub2.

In other words, when 5ub2 is applied to the decoder 10, the above execution command is applied to the AND circuit 16 via the OR circuit 15, "1" is output to the signal line 10b, and the clock pulse is read into the flip-flop 13. φe is applied to the address counter 2 and is counted up.

Therefore, the address memory 22 via the AND circuit 24
The contents of the address transferred to is stored as the jump-back address to the main routine when the subroutine ends.

Furthermore, the output of the flip-flop 13 is output from the OR circuit 21
The address counter 2 is instructed to read the contents of the address memory 22 via the flip-flop 1.
Since the output of 3 is applied to the AND circuit 23 via the inverter 25 and its output is inhibited, the address counter 2 reads '0', and as a result, the address counter 2 is cleared.

This state is steps B and C shown in FIG.

Therefore, when the flip-flop 7 is set,
The output is applied to an AND circuit 16 via an OR circuit 15 to open its gate.

Therefore, the clock pulse φe is applied to the address counter 2 via the AND circuit 16, and its contents are sequentially counted up.

Therefore, the contents of the program in the program memory 1 are sequentially read out from the first address and set in the buffer register 6 via the AND circuit 4.

Since the matching circuit 11 cannot match until the Pr2 code is read into the buffer register 6, the flip-flop 7 is not reset and the address counter 2 continues counting up.

Then, when the Pr2 code is read from the program memory 1 to the buffer register 6, in step D, the Pr2 code output from the code conversion circuit 9 and the output of the buffer register 6 match with respect to the content 5ub2 held in the buffer register 5. , a "1" signal is output from the matching circuit 11.

That is, detection of the head address in the program Pr2 shown in step E is performed.

The output of the minus number circuit 9 is output from the AND circuit 12 in synchronization with the clock pulse φe, and resets the flip-flop 7.

When flip-flop 7 is reset, AND circuit 1
Gate 6 is closed, and the count-up operation of address counter 2 is stopped.

In addition, by resetting the flip-flop 7, the output of the inverter 8 becomes "1" and the gate of the AND circuit 3 is opened. will be sent to.

This completes the designation of the subroutine for the program Pr2, and the contents of the program Pr2 are then read out from the program memory 1 in accordance with the execution command given to the OR circuit 15, and its processing is executed.

When the processing for the program Pr2 is completed, the END code is read from the program memory 1 to the buffer register 5.

When this END code is read to the buffer register 5, the decoder 10 outputs a "1" signal to the output line 10b.

At this point, it is determined whether the program Pr2 whose processing has ended has been used as a subroutine, that is, whether the flip-flop 14(S) shown in step F in FIG. 3 is set.

As a result of this determination, if the flip-flop 14 is not set, a termination signal is output from the AND circuit 18 and all processing is completed, but at this point, since the flip-flop 14 (S) is set, A 1'' signal is output from the AND circuit 17, and the process of transferring the contents of the address memory 22 to the address counter 2 shown in step G is performed.

That is, the output of the AND circuit 17 is sent as a write command to the address counter 2 via the OR circuit 21, and the output of the flip-flop 13, which is at "O" at this point, is sent as a write command to the address counter 2 via the OR circuit 21.
The output becomes "1" and is applied to the AND circuit 23 via the inverter 25, so the contents of the address memory 22 are transferred to the address counter 2 via the AND circuit 23.

Further, the output of the AND circuit 17 is the clock pulse φ
e is read into the flip-flop 20 in synchronization with
4 is reset (cleared).

Therefore, the address sent from the address memory 22 to the address counter 2 indicates the next address of the subroutine 5ub2 designated code storage address of the main program Prl, as described above, and the main program Prl is subsequently executed from this address. be done.

When the processing for the main program Prl is completed, the END code is read from the program memory 1 to the buffer register 5, and as a result, the decoder 10 outputs a "■" signal to the output line 10b.

At this time, it is determined whether the program Prl whose processing has been completed has been used as a subroutine, that is, whether the flip-flop 14 (S) is set as shown in step (2).

Since the program Prl is used as the main program, the flip-flop 14 (S) is not set and the gate of the AND circuit 18 is open.

Therefore, the signal outputted from the decoder 10 to the output line 10b is outputted as an end signal from the AND circuit 18 and sent to the control section.

In addition, if the program Prl is used as a subroutine, the step G shown in steps J and K is
, H, and a jump back to another program is performed.

Although the above embodiment shows a case where only one independent program is used as a subroutine, the present invention is not limited to this, and for example, it may be used as a subroutine corresponding to each independent program. Of course, it is also possible to provide a storage section for storing whether or not the jumpback address is set, and to use a stack memory as the address memory for storing the jumpback address so as to sequentially move to the next level. It goes without saying that various modifications can be made without departing from the scope.

As described above, according to the present invention, the functions of the main routine and subroutine are not fixed in the written program, and a program specified by another program is made to operate as a subroutine. Other programs can be specified arbitrarily, giving flexibility to the program, and since each program is written as an independent program, there is no increase in the complexity of program write or read operations. It is possible to provide a program processing method that can use the program storage area extremely efficiently.

[Brief explanation of drawings]

Figure 1 is a diagram for explaining the basic operation of the present invention, Figure 2 is a diagram for explaining the basic operation of the present invention.
The figure shows a constituent country showing an embodiment of the present invention, and FIG. 3 is a flowchart for explaining the operation of the embodiment. 1...Program memory, 2...Address counter, 5, 6...Buffer register,
7,13゜14.20...Flip-flop,
9... Code conversion circuit, 10... Decoder, 11... Matching circuit, 22... Address memory.

Claims (1)

[Claims] 1. Program storage means for storing a plurality of independent programs, addressing means for specifying addresses of programs stored in the program storage means, and contents of the programs sequentially designated and read by the addressing means. a detection storage means for detecting and storing that the independent program is used as a subroutine, and a return function when the detection storage means detects that the independent program is used as a subroutine; return address storage means for storing an address to be returned to, and each time the processing of one independent program is completed, it is determined based on the storage contents of the detection storage means whether the program has been used as a subroutine of another independent program. determining means for determining, when the determining means determines that the independent program is not used as a subroutine of another independent program, terminating the execution by terminating the independent program;
and when it is determined that the independent program is used as a subroutine of another independent program,
A program processing method comprising: means for transferring an address stored in the address storage means to the address specifying means.