JP2819753B2 - Pipeline microprocessor - Google Patents

Description

Description: FIELD OF THE INVENTION The present invention relates to pipeline microprocessors,
In particular, the present invention relates to a pipelined microprocessor that determines a program counter value when an asynchronous exception input signal occurs.

[Conventional technology]

In a conventional pipeline microprocessor, a data write cycle to an external memory (hereinafter, referred to as a memory write cycle) may be performed during an instruction execution period after the instruction, and at that time, during instruction decoding,
After the instruction is decoded, the pipeline microprocessor has only the program counter corresponding to the three states during the execution of the instruction, so that the pipeline microprocessor executes the program counter of the instruction executed between the instruction execution and the actual memory write cycle. Does not hold a value.

FIG. 4 is a block diagram around a program counter of a pipeline microprocessor showing an example of the prior art, and FIG. 5 is a timing chart for explaining the state of the program counter shown in FIG.

As shown in FIG. 4, such a pipeline microprocessor shows hardware associated with a program counter having a bus error input for receiving information that a failure has occurred for an external write bus cycle. Further, as shown in FIG. 5, the timing indicates the state of each program counter in the pipeline microprocessor.

First, the instruction decode unit 1 shown in FIG. 4 is an instruction to be decoded is assumed that a memory operand, outputs the operand address of the instruction I ₁ shown in FIG. 5 the operand addressing bus 24 Then, the operand address strobe 25 is activated to write the operand address into the address buffer 15 of the access control unit 2. This timing is shown in FIG.

Next, when the instruction decoding is completed, the decoded program counter store strobe 30 is activated, and the contents of the decoding-in-progress / program counter 9 are written in the decoded program counter 34. Then
Activate the next program counter store strobe 28, add the value of the program counter 9 being decoded and the instruction length designation 29 by the program counter adder 10, and write the added value to the program counter 9 being decoded. .

Here, since the decoding of the instruction has been completed, the instruction decoding unit 1 notifies the instruction execution unit 3 using the instruction designation information 23 to that effect. When the instruction execution unit 3 receives the instruction designation information 23, the instruction execution unit 3
Activate the counter value store strobe 37 and write the contents of the decoded program counter 34 to the running program counter 35. This timing is the fifth
This is the part in the figure. The data of the running program counter 35 is sent to the instruction execution unit 3 via the running program counter read bus 36.

Next, the instruction execution unit 3 writes the operand write data 27 to the write data buffer 16 of the access control unit 2 based on the instruction designation information 23. This timing is shown in FIG.

Here, the address bus 17 from the access control unit 2 and the data bus 18 correspond, and the write bus
A cycle takes place. Accordingly, the instruction execution unit 3 shifts to the next instruction execution operation and executes the program counter 35 during execution.
Value will indicate the next instruction I ₂ of the instruction I ₁ having a write operand. This timing is shown in FIG.

Next, if the bus error signal 19 to the write bus cycle of the command I ₁ is input, the instruction execution unit 3 after executing instructions I _2, but transitions to the bus error processing , the execution of this instruction because it is performed prior to the operand write operation, the value of the program counter of the instruction I ₁ a bus error occurs is lost. This timing is shown in FIG. Therefore, the program counter value at the time of bus error input occurs, as shown in the timing in Fig. 5, the I ₂ rather than I _1.

[Problems to be solved by the invention]

The conventional pipeline microprocessor described above performs further subsequent instruction execution after the execution of an instruction until the end of the corresponding external memory write cycle after the execution of the instruction having the memory write operand and the program counter value of the instruction. It may be done or finished. Therefore, if there is an asynchronous input indicating the external exception factor corresponding to the memory write operand bus cycle, the program counter value of the instruction that executed the memory write cycle cannot be held, and the There is a disadvantage of losing.

An object of the present invention is to provide a pipelined microprocessor capable of accurately retaining a program counter value of an instruction that has executed such a memory write cycle.

[Means for solving the problem]

The pipeline microprocessor of the present invention includes a mechanism for transferring and holding a sequence number key of a number of bits capable of representing a numerical value including the number of stages of each instruction pipeline to a unit that controls each pipeline stage; An instruction decoding unit having a mechanism for sequentially generating keys and pre-calculating a program counter value, and a program for holding the keys generated by the instruction decoding unit and the program counter values in a corresponding manner
A counter associative memory file and a key corresponding to an instruction designating a bus cycle in which the asynchronous signal is received when an asynchronous signal input from the outside occurs during the external bus cycle in the unit that controls the external bus cycle And a bus that has the asynchronous input.
A mechanism for reading a cycle key from the microprogram and a mechanism for reading the program counter value from the program counter associative storage file using the key specified by the microprogram as a search index.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a pipeline diagram showing a first embodiment of the present invention.
FIG. 2 is a block diagram around a program counter which is a main part of the microprocessor.

As shown in FIG. 1, this embodiment is similar to the prior art,
A bus error occurring during a write bus cycle will be described. The configuration of the present embodiment comprises an instruction decode unit 1 having a mechanism for sequentially generating an order number key and pre-calculating a program counter value, and receiving and writing an operand address from the instruction decode unit 1. Controlled by an access control unit 2 having registers 13 and 14 for storing an access key and a key at the time of a bus error, an address buffer 15 and a write data buffer 16, and a strobe from the instruction decode unit 1. Instruction execution unit 3
And a program counter file key unit 5 and a program counter file data unit 6 for storing a key generated by the instruction decode unit 1 and a program counter value in association with each other. And 4. The microprocessor according to the present embodiment includes a decoding key register 7 for holding a sequential count key (number) of an instruction being decoded and a decoding program counter 9 for holding a program counter value of the instruction being decoded. A key incrementer 8 for generating a key of an instruction to be decoded next for each instruction decode, a program counter adder 10 for calculating the program counter value, and the sequential count generated by the instruction decode unit 1. Mechanisms 23-25 and 28-30 for transferring keys to the unit responsible for each pipeline stage, and decoded programs
The counter key register 11 and the program being executed
A counter key register 12 for instructing a bus cycle that has received the asynchronous signal when an externally input asynchronous signal occurs during the external bus cycle in a unit that controls the external bus cycle While holding the key corresponding to the instruction, and reading out the key of the bus cycle in which the asynchronous input has been made from the microprogram, the program / counter associative storage file 4 uses the key designated by the microprogram as a search index, and The counter value is read.

FIG. 2 is a timing chart for explaining the state of the program counter shown in FIG.

As shown in FIG. 2, the operation timing of the program counter will be described in the following circuit operation.

First, the instruction decode unit 1 decodes an instruction I _1, operand outputs the operand address of the instruction to the operand addressing bus 24
Activate address strobe 25 to access
The operand address is written to the address buffer 15 of the control unit 2. At the same time, the program counter, which is being decoded, is being stored in the write access key register 13 from the key register 7, which is being decoded.
Write key 26. This is the part in FIG. Here, the value of the key in the decoding key register 7 is added by +1 in the key incrementer 8 and stored in the decoding key register 7 again.

When the instruction decoding in the instruction decoding unit 1 is completed, the decoded program counter store strobe 30 is activated and the value of the decoding key register 7 is changed to the decoded program counter key register 11 and the program register. The program counter file key portion 5 in the counter associative storage file 4 is written, and at the same time, the value of the program counter 9 being decoded is stored in the program counter file data portion 6 in the program counter associative storage file 4.
Write to. Next, the next program counter store strobe 28 is activated to decode the value obtained by adding the value of the program counter 9 being decoded and the instruction length designation 29 from the instruction decode unit 1 by the program counter adder 10. Write to program counter 9 Here, since the decoding of the above-mentioned instruction has been completed, the instruction decoding unit 1 notifies the instruction execution unit 3 of the fact by the instruction designation information 23. When the instruction execution unit 3 receives the instruction specification information 23, it activates the program counter key store strobe 22 during execution and activates the contents of the decoded program counter key register 11 to execute the program counter key register. Write to 12. This timing is the portion in FIG.

Next, the instruction execution unit 3 writes the operand write data 27 to the write data buffer 16 of the access control unit 2 according to the instruction specification information 23. This timing is shown in FIG.

Here, the address bus 17 and the data bus 18 of the access control unit 2 correspond to each other, and a write cycle is performed. Thus, the instruction execution unit 3 moves to the next instruction execution operation, the value of the running program counter key register 12 will indicate the next instruction I ₂ of the instruction I ₁ having a write operand. This timing is shown in FIG.

The bus error signal to the write bus cycle of the command I ₁ to the access control unit 2
If 19 is input, key register 14 for bus error
Latches the value of the write access key register 13. This is the part in FIG.

Meanwhile, the instruction execution unit 3 transition instructions I ₂ to perform after the bus error processing, access control
The value of the bus error key register 14 in the unit 2 is read, and the key value is converted into a program counter file read key 21 to search the program counter associative memory file 4. The program counter file key section 5 in the program counter associative storage file 4 uses the received program counter file read key 21 as a search index to retrieve a corresponding program counter value I from the program counter file data section. Read ₁ and output it to the program counter file read bus 20.

Accordingly, as shown in the timing in FIG. 2, by searching a program counter associative memory file 4 with the value of the bus error during key register 14, the program counter of the instruction I ₁ that caused the bus error Value can be obtained.

In short, the present embodiment has a program counter file that can obtain a desired program counter value by using a key held in each pipeline stage as a search index, thereby providing a memory write bus bus. The program counter value can be accurately recognized even for an asynchronous input to a cycle.

FIG. 3 is a pipeline diagram showing a second embodiment of the present invention.
FIG. 2 is a block diagram similar to FIG. 1 of a microprocessor.

As shown in FIG. 3, this embodiment is also an example in which a program counter value is held for a bus error occurring during a write bus cycle. Therefore, instruction decoding
Unit 1, access control unit 2, instruction execution unit 3, decoding key register 7, key incrementer 8, decoding program counter 9, program counter adder 10, key registers 11, 12, etc. The second embodiment is the same as the first embodiment described above, except that the program counter associative storage file 4 including the program counter file key unit 5 and the program counter file data unit 6 is replaced by
It has a program counter register file 31, a write decoder 32 and a read decoder 33. The operation of the difference will be described below.

In this embodiment, the decoded program counter value stored at the end of the instruction decoding is obtained by decoding the program counter key 26 being decoded by the decoded program counter writing decoder 32 and mapping the mapped program counter register. -It is written to the entry of the file 31 at the timing of the decoded program counter store strobe 30.

Conversely, reading of a desired program counter value from the instruction execution unit 3 is performed by using a program counter
The file read key 21 is performed from the entry in the program counter register file 31 mapped by the program counter file read decoder 33.

Note that the other operations are the same as those of the first embodiment, and the description is omitted.

〔The invention's effect〕

As described above, the pipeline microprocessor of the present invention stores a program counter value of an instruction as a search index using a key corresponding to the instruction counter value, so that a program can be programmed by a microprogram when an external asynchronous input is received. Since a key having a smaller number of bits than the number of bits of the counter can be extracted from the unit that controls the external bus cycle, it is possible to use the index as a search index to accurately obtain the corresponding program counter value.

[Brief description of the drawings]

FIG. 1 is a block diagram around a program counter which is a main part of a pipeline microprocessor showing a first embodiment of the present invention, and FIG.
FIG. 3 is a timing chart for explaining the state of the counter, FIG. 3 is a block diagram similar to FIG. 1 of a pipeline microprocessor showing a second embodiment of the present invention, and FIG. FIG. 5 is a block diagram around the program counter of the line microprocessor, and FIG. 5 is a timing chart for explaining the state of the program counter shown in FIG. 1 ... instruction decode unit, 2 ... access control unit, 3 ... instruction execution unit, 4 ...
Program counter associative memory file, 5: Program counter file key section, 6: Program counter file data section, 7: Decoding key register, 8: Key incrementer, 9 ... … Decoding program counter, 10… Program counter adder, 11… Decoded program counter key register, 12… Executing program counter key register, 13… Write access key・
Register, 14 ... Key register at bus error, 15 ...
… Address buffer, 16… write data buffer, 17… address bus, 18… data bus, 19…
... Bus error signal, 20 ... Program counter file read bus, 21 ... Program counter file read key, 22 ... Executing program counter key store strobe, 23 ... Instruction designation information,
24 ... Operand address designation bus, 25 ... Operand address strobe, 26 ... Decoding program counter key, 27 ... Operand write data, 28 ... Next program counter store strobe, 29: Instruction length specification, 30: Decoded program counter store strobe, 31: Program
Counter register file, 32: Decoder for writing decoded program counter, 33 ... Decoder for reading program counter register file.

Claims (2)

(57) [Claims] A mechanism for transferring and holding a sequence number key of a number of bits capable of representing a numerical value including the number of stages of each instruction pipeline to a unit that controls each pipeline stage, and sequentially generating the keys. And program
Instruction decoding with a mechanism to pre-calculate the counter value
A unit, a program counter associative memory file for holding the key generated by the instruction decode unit and the program counter value in association with each other, and a unit for handling an external bus cycle, which is externally input during the external bus cycle A mechanism for holding a key corresponding to an instruction instructing a bus cycle in which the asynchronous signal is received when an asynchronous signal is generated, and a mechanism for reading a key of a bus cycle in which the asynchronous input is received from a microprogram. A mechanism for reading out the program counter value from the program counter associative storage file using a key designated by a microprogram as a search index. 2. The program counter associative storage file according to claim 1, wherein program counter registers are arranged in accordance with the type of keys, and the keys output from the instruction decode unit are mapped and written according to the decoding result, and the instruction is executed. A pipeline microprocessor characterized by a mechanism for mapping an arbitrary key designated by a unit according to a decoding result and reading out the data.