JPH0373021A - Microcomputer - Google Patents

Abstract

PURPOSE:To improve efficiency for executing an instruction in an execution control part (EXU) by stopping the start of preceding fetch of an instruction code when it is detected that the instruction is an instruction with the read/write of data. CONSTITUTION:Unless a data read request 13 or a data write request 14 is generated from an EXU 2, a bus control part (BCU) 3 continue the preceding fetch by using an address stored in a fetch pointer 15 until a queue buffer 19 is filled up. At such a time, a timing generating circuit 22 outputs the value of the fetch pointer 15 from a multiplexer 24 to an address bus 6 by using a select signal 25 and simultaneously outputs an RD signal 8. An instruction decoder 21 always monitors the instruction code on an instruction code bus 10 and detects the instruction with the read or write of a data memory 4. The timing generating circuit 22 forcedly stops the start of the preceding fetch of the instruction until the read/write of the data is completed. Thus, the instruction execution efficiency of the EXU can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a microcomputer, and more particularly to a microcomputer having a pre-control circuit for pre-fetching instruction codes.

[Conventional technology]

Conventionally, microcomputers that perform advance fetching of instruction codes have an execution control unit (hereinafter referred to as EX) that controls the execution of instructions.
The ECU consists of a bus control unit (hereinafter referred to as ECU) that performs advance fetching of instruction codes and control of data read/write using a common bus. This E
The CU is equipped with a queue buffer with a first-in/fast-out configuration that stores pre-fetched instruction codes, and when data is not read/written by executing an instruction, the pre-fetch of the instruction code is performed unless the queue buffer is full. It is controlled to perform. However, at a timing when no data is being read or written, advance fetch is performed unconditionally, so the advance fetch is performed unconditionally.

There is a problem in that the execution of instructions associated with reading/writing data is stopped while the check is being performed.

FIG. 4 is an operation timing diagram of the BCU and EXU in a microcomputer to explain an example of such a conventional system.

As shown in Fig. 4, Tn (n is 0 to 12) indicates the timing, the bus cycle controlled by the ECU operates in 4 cycles, and at the timings of To-T3 and T4 to T7, instructions for successor instructions are given. The code is being fetched ahead of time. On the other hand, the EXU can execute an instruction (instruction α in the figure) that does not involve reading/writing data independently of the ECU operation. However, when executing instruction β that involves reading/writing data, even if the data read is attempted to start at timing T5, the ECU has already started fetching instruction code B from timing T4, so instruction β is immediately executed. Read data for execution (
timing from T8 to Tll) cannot be performed.

Therefore, during the T5 to T7 timing period (Tidle in the figure), the EXU operation is completely stopped and no instructions can be executed, so after the instruction code β has been fetched, the EXU is Data is read and instruction execution is completed at timing T12.

[Problem to be solved by the invention]

The preceding control circuit in the conventional microcomputer described above continues fetching the instruction code even when executing an instruction that involves data read/write, and cannot stop the bus cycle once started. This has the disadvantage that the EXU operation stops until the bus cycle ends, reducing instruction execution efficiency.

An object of the present invention is to provide a micromanipulator that can improve the instruction execution efficiency of such an EXU.

[Means to solve the problem]

The microcomputer of the present invention includes an execution control section that controls execution of instructions, and a bus control section that performs advance fetching of instruction codes and reading/writing of data on a common bus, wherein the bus control section is a plurality of storage means for temporarily storing the previously fetched instruction code; and a detection means for decoding the instruction code output from the storage means and detecting that the instruction is an instruction that involves data read/write. and timing control means for stopping the start of advance fetching of the instruction code for a predetermined period when the detection means detects that the instruction is an instruction that involves data read/write.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a microcomputer for explaining the present invention in detail.

As shown in FIG. 1, a microcomputer 1 according to the present invention has an EXU that executes instructions, a data memory 4 and a program memory that use a common address bus 6 and a data node to fetch instruction codes and read/write data. 5 and BCU3. E
XU2 uses S to send an address to BCU3.
It is connected to the bus 11 and outputs a data read request 13 requesting data reading and a data write request 14 requesting data writing.

Furthermore, a D bus 12 for transmitting read/write data and an instruction code bus 10 for transmitting previously fetched instruction codes are connected between the BCU 3 and EXU 2. Connected from the BCU 3 to the memories 4 and 5 are an address bus 6 that outputs addresses for reading instruction codes and reading and writing data, and a data bus 7 that inputs and outputs both instruction codes and data. Lead/
RD signal specifying write timing8. WR signal 9
Output. This address bus 6, data bus 7, RD
The signal 8 is connected to a readable/writable data memory 4 and a program memory 5 in which instruction codes are stored.
WR signal 9 is connected only to data memory 4. Further, EXU2 is output from the instruction code bus 10 of the ECU3.

Control is performed according to the instruction code to realize instruction processing.

FIG. 2 is a specific configuration diagram of the ECU shown in FIG. 1 for explaining one embodiment of the present invention.

As shown in FIG. 2, the ECU 3 in this embodiment has a fetch pointer 15 that holds an address for prefetching, an incrementer 23 that increments the fetch pointer 15, and performs read/write of data. An address latch 16 that specifies the current address, and an output data latch 1 that temporarily stores the data to be written.
7, and an input data latch 18 that stores read data.
, a 3-byte queue buffer 19 for storing the previously fetched instruction code, and a queue status circuit 20.
It has an instruction decoder 21 that decodes the output of the queue buffer 19, a multiplexer 24, and a timing generation circuit 22 that generates various timing signals.

The ECU 3 uses the address stored in the fetch pointer 15 unless a data read request 13 or data write request 14 is generated from the EXU 2.
Advance fetching continues until the queue buffer 19 is full. At this time, the timing generation circuit 22 uses the select signal 25 to output the value of the fetch pointer 15 from the multiplexer 24 to the address bus 6, and at the same time,
Outputs RD signal 8. Then, the instruction code is read from the program memory 5 and written to the queue buffer 19 via the data bus 7.The first out (FIFO) 111Jffi buffer and the status of the queue buffer 19 are determined by the queue status circuit. 20 are monitoring. That is, when the queue buffer 19 does not contain any valid instruction codes, the queue empty signal 2 is output.
6, and when the queue buffer 19 is full and no more advance fetching is possible, a queue full signal 27 is output and input to the timing generation circuit 22.

The EXU 2 takes in the output of the queue buffer 19 via the instruction code bus 10 and executes the instruction.

Further, the instruction decoder 21 constantly monitors the instruction code on the instruction code bus 10, and detects an instruction that involves reading or writing the data memory 4.

Here, when the instruction decoder 21 detects the instruction, the decode output 28 goes to the "1" level, which causes the timing generation circuit 22 to forcibly stop the start of the advance fetch of the instruction until the data read/write is completed. let Furthermore, the EXU 2 writes an address for reading/writing data to the address latch 16 via the S bus 11 in response to the instruction code on the instruction code bus 10, and further outputs write data via the D bus 12 when writing data. Write to data latch 17.

When the data read request 13 or data write request 14 is output in such a state, the timing generation circuit 22 selects the address latch 16 as the output of the multiplexer 24, and simultaneously outputs the RD signal 8 or WR signal 9.
Output. In the case of data read, the output from the data memory 4 is latched by the input data latch 18 via the data bus 7, and then sent to the EXU 2 via the D bus 12. In addition, in the case of data write, the output data latch 17
The data written in is output to the data memory 4 via the data bus 7. Here, while the data memory 4 is being read/written, advance fetching to the queue buffer 19 is stopped, so the queue buffer 19 is
EXU2 consumes the instruction code of
may be empty. At this time, it becomes impossible to continue the instruction, so the queue status circuit 20 detects this and sends the queue empty signal 26 to the timing generation circuit 20.
Output to 2. The timing generation circuit 22 thereby detects that an instruction code needs to be fetched, forcibly fetches the instruction code from the program memory 5, and executes the instruction.

FIG. 3 is another specific configuration diagram of the ECU shown in FIG. 1 for explaining the second embodiment of the present invention.

As shown in FIG. 3, in addition to the instruction decoder 21, the BCU 3 in this embodiment includes a word length decoder 29 that detects the word length of an instruction, and a word length decoder 29 that detects how many instruction codes are stored in the queue buffer 19. The BCU 201 is the same as the BCU 201 of the first embodiment described above, except that the queue status circuit 2o has additional functions and the detection output 31 is connected to the timing generation circuit 22.

First, when the instruction decoder 21 detects an instruction that involves data read/write and the decode output 28 becomes "1", the timing generation circuit 22 monitors the output 30 of the word length decoder 29, and at this time the queue buffer It is known how many bytes of instruction code must be stored in 19 before the instruction can be executed. Here, the detection output 31 of the queue status circuit 20 is checked, and if the instruction code is insufficient, instruction processing does not start, and after the instruction code is forcibly fetched to the queue buffer 19, instruction execution begins. On the other hand, if enough instruction codes are stored, the instruction is started immediately.

By performing the above-described control, the queue empty signal 26 will not be generated during instruction execution, so there is no need to forcibly read the instruction code during instruction execution.

〔Effect of the invention〕

As explained above, the microcomputer of the present invention has
Since the start of instruction code fetch is stopped before executing an instruction that involves data read/write, there is no conflict with instruction code fetch when data is read/written by instruction execution, greatly improving the instruction execution efficiency of the EXU. This has the effect that it can be improved.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a microcomputer for explaining the present invention in detail, FIG. 2 is a specific configuration diagram of the ECU shown in FIG. 1 for explaining the first embodiment of the present invention, and FIG. This figure is another specific configuration diagram of the ECU shown in FIG. 1 for explaining the second embodiment of the present invention, and FIG. 4 is an operation timing of the ECU and EXU in a microcomputer for explaining a conventional example. It is a diagram. 1...Microcomputer, 2...Mark EX
U53...BCU, 4...Data memory, 5...Program memory, 6...
Address bus, 7... Data bus, 8...
...RD double signal 9...WR signal, 10...
...Order food bus, 11...S bus, 12.
...No.D bus, 13...Data read request, 1
4... Data ride request, 15...
...Fetch pointer, 16...Address latch, 17...Output data latch, 18...
...Input data latch, 19...Queue buffer, 20...Queue status circuit, 21...
...Instruction decoder, 22...Timing generation circuit, 23...Incrementer, 24...
...Multiplexer, 25...Select signal, 26...Queue empty signal, 27...
... Cue full signal, 28 ... Decode output, 29 ... Word length decoder, 30 ... Word length decoder output, 31 ... Detection output.

Claims (1)

[Claims] In a microcomputer, the microcomputer has an execution control unit that controls the execution of instructions, and a bus control unit that performs pre-fetching of instruction codes and reading/writing data on a common bus, wherein the bus control unit processes the pre-fetched instruction codes. a plurality of storage means for temporarily storing data; a detection means for decoding the instruction code output from the storage means and detecting that the instruction is an instruction that involves reading/writing data; 1. A microcomputer comprising: timing control means for stopping the start of advance fetching of the instruction code for a predetermined period when the detection means detects that the instruction involves /writing.