JPH0589031A - Microprocessor - Google Patents

Abstract

PURPOSE:To accelerate a device access processing by omitting a first state for preparing device access following to a second bus cycle in the continuous bus cycles at continuous addresses. CONSTITUTION:An instruction decode execution part 2 detects instructions with the continuous bus cycles at the continuous addresses. At such a time, when there are three bus cycles, the execution part 2 makes a BS<1>T3 signal 9 active H and when there are two bus cycles, a BS<1>T2 signal 10 is made active H. Then, it is informed to read the prescribed number of data at the continuous addresses in a burst mode. Assuming that a BURSTMD signal 11 is made active H and an external circuit (not shown in the figure) supports a bus cycle mode in a state as mentioned above, a bus control part 3 reads data by the 1st bus cycle composed of 1st and 2nd states and the bus cycles following the 2nd bus cycle composed of only the 2nd state. Thus, the 1st state after the 2nd bus cycle can be omitted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprocessor, and more particularly to a microprocessor capable of performing device access processing at high speed.

[0002]

2. Description of the Related Art Generally, in a device access process of a microprocessor, a bus cycle is composed of two states. That is, one state indicates that the output of an address, a control signal, etc. is valid, and the preparation of access to a device such as a memory (address
A state (hereinafter, referred to as T1 state) for performing decoding and the like, and another state is a state (hereinafter, referred to as T2 state) for device access.

By the way, for example, in an access to a stack memory associated with an interrupt instruction or a call instruction, the access is performed at consecutive addresses, and the address of the next cycle and the state of the control signal are known.
In the conventional microprocessor, the access is performed by repeatedly executing the bus cycle consisting of the T1 state and the T2 state, like the access in other cases.

FIG. 3 shows the read cycle timing from the stack memory at the time of executing an IRET (returning upon interruption) instruction in such a conventional microprocessor. In this example, reading with three consecutive addresses is T1, T2, T1, T2, T1, T2.
Then, the T1 state and the T2 state are repeatedly executed. In the figure, the ADS signal is an address / status signal, which becomes active in the T1 state, indicating that the address and control signals are valid. When the ADS signal is active, it activates the CONTROL control signal and enters the bus cycle. Also, READ
The Y signal indicates the end of the bus cycle.

[0005]

As described above, in the conventional microprocessor, even if the memory access in which the states of the address and the control signal are known in advance, the T1
Memory access is performed by repeatedly executing the state and the T2 state.

However, in the microprocessor,
It is desired to speed up various processes, and it is naturally required to further speed up the device access process as described above.

The present invention has been made in consideration of such a conventional situation, and an object of the present invention is to provide a microprocessor capable of performing device access processing at a higher speed than the conventional one.

[0008]

That is, the microprocessor of the present invention uses a bus cycle consisting of a first state for preparing access to a device and a second state for accessing the device to access the device. A decoding means for detecting and decoding an instruction for accessing a continuous address in a microprocessor for processing; and a continuous access instructing means for instructing that a bus cycle to be executed is a continuous address based on the decoding means, Detecting means for detecting whether or not the device is continuously accessible; and based on a detection result of the detecting means, the device is continuously accessible and the A first bus cycle consisting of one state and the second state; Characterized by comprising a bus cycle control means for sequentially executing the device access process by the second and subsequent bus cycle of state only.

[0009]

In the microprocessor of the present invention having the above structure,
When performing continuous bus access with consecutive addresses, in the second and subsequent bus cycles, the first state (T1 state) for device access preparation is omitted and the second state (T1 state) for accessing the device is omitted. T2
Bus access can be performed only by (state). Therefore, the device access process can be performed at a higher speed than in the past.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 1 shows a schematic configuration of a microprocessor according to an embodiment of the present invention. In FIG. 1, reference numeral 1 is a microprocessor. This microprocessor 1
Is an interface between an instruction decoding execution unit 2 that decodes an instruction and executes the instruction, a bus control unit 3 that controls a bus cycle, an address generation unit 4 that generates an address, and an external data bus. It has a certain data bus I / F 5. In FIG. 1, 6 is an internal data bus,
7 is a data bus connected to an external circuit (not shown), 8
Is an address signal sent from the address generator 4 to an external circuit (not shown).

The instruction decoding execution unit 2 is, for example, IRET.
When an instruction such as an instruction involving continuous bus access of consecutive addresses is detected, for example, if there are three bus cycles associated with instruction execution depending on the number of times of access (number of consecutive bus cycles), the BST3 signal 9 BST2 signal 10 is active high when there are two bus cycles
As a notification, it is notified that a predetermined number of data of consecutive addresses are read in the burst mode.

Further, the bus control unit 3 is supplied with a BURSTMD signal 11 from the external circuit, which indicates whether or not the external circuit supports the bus cycle burst mode. Then, the bus control unit 3 sets the BST3 signal 9 or the BST2 signal 10 from the instruction decoding execution unit 2 to active H and the BURSTMD signal 11 to active H to set the external circuit to the bus cycle burst mode. When it is supported, the BURST signal 12 is set to active H to notify the external circuit that the current bus cycle is in the bus cycle burst mode, and the first bus consisting of T1 state and T2 state The bus cycle is controlled so that the data is read by the cycle and the second and subsequent bus cycles including only the T2 state.

On the other hand, when the BURSTMD signal 11 is inactive L and the external circuit does not support the bus cycle burst mode, the bus control unit 3 causes the normal bus operation in which each bus cycle consists of T1 state and T2 state. The cycle controls the bus cycle to perform the reading of data.

In FIG. 1, the ADS signal 13 is
This is an address / status signal and becomes active H in the T1 state. Further, the CONTROL signal 14 is a bus control signal and defines the type of the bus cycle (memory data read / write) currently being performed. Furthermore, the READY signal 15 is a ready signal and indicates the end of the bus cycle.

FIG. 2 shows an example of the timing when the IRET instruction is executed by the microprocessor 1 of the present embodiment having the above configuration.

As shown in this figure, the instruction decoding execution unit 2
Sends a memory read request to the bus control unit 3, sets the BST3 signal 9 to active H, and sets three data of consecutive addresses (in this case, three programs related to the program counter, code segment, and flag saved in the stack). One data) needs to be read.

At this time, when the BURSTMD signal 11 is active H and the external circuit supports the bus cycle burst mode, the bus control unit 3 sets the BURST signal 12 to active H and the bus currently being performed to the external circuit. -Indicates that the cycle is in bus cycle burst mode.

Then, the memory read cycle is set to 1
The second bus cycle is T1 state and T2 state,
The second and third cycles are T1, T2, T2, and T2, which consist of only T2 state,
Take the lead.

Therefore, in the case of executing this IRET instruction, the processing time for two clocks can be shortened and the processing speed can be increased as compared with the conventional case shown in FIG.

[0021]

As described above, according to the microprocessor of the present invention, the T1 state of the second and subsequent bus cycles can be omitted in consecutive bus cycles at consecutive addresses. device·
The access process can be performed at a higher speed than in the past.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a microprocessor according to an exemplary embodiment of the present invention.

FIG. 2 is a diagram showing an example of timing when an IRET instruction is executed by the microprocessor of FIG.

FIG. 3 is a diagram showing a timing example when an IRET instruction is executed by a conventional microprocessor.

[Explanation of symbols]

 1 Microprocessor 2 Instruction Decoding Execution Unit 3 Bus Control Unit 4 Address Generation Unit 5 Data Bus I / F 6 Internal Data Bus 7 Data Bus

Claims (1)

[Claims] 1. A first method for preparing access to a device.
A decoding means for detecting and decoding an instruction for accessing a continuous address in a microprocessor for device access processing by a bus cycle consisting of a state and a second state for accessing the device. Based on the detection result of the detection means, a continuous access instruction means for instructing that the bus cycle to be executed is a continuous address, a detection means for detecting whether or not the device is continuously accessible, The first bus cycle consisting of the first state and the second state and the second and subsequent ones consisting of only the second state are accessible by the device and in response to the execution instruction of the continuous access instruction means. A bus cycle in which device access processing is sequentially executed by a bus cycle A microprocessor comprising: a control unit.