JPS6258348A - Memory control integrated circuit - Google Patents

Abstract

PURPOSE:To operate a CPU at a high speed with no-wait state kept by providing the functions of a clock generator, a bus controller, etc. to a memory control integrated circuit. CONSTITUTION:A status decoding circuit 12 receives the status signal S0, etc. from a CPU 21 and transmits the decoding result to a shut-down circuit 16, a control signal output circuit 17 and a memory timing generating circuit 18. The circuit 18 gives immediately an indication to a memory control signal output circuit 19 to give an access to a dynamic RAM 22 according to the decoding result. The access to the RAM 22 can be started at the middle of a state Ts to increase the processing speed. Thus it is not required to keep the CPU 21 waiting.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention is a memory control integrated circuit used in so-called high-performance personal computers, etc. 1. The present invention is a memory control integrated circuit used in so-called high-performance personal computers.
The present invention relates to a memory control integrated circuit that can operate at high speed while in Wait state.

[Conventional technology]

FIG. 4 shows an example of the conventional method, and FIG. 5 shows a time chart of the conventional method.

In FIG. 4, 21 is a CPU, 22 is a dynamic R
AM, 30 is a clock generator that supplies a synchronization signal to the CPU 21, 31 is a hash controller, and 32 is a memory control circuit that outputs an access control signal to the dynamic RAM 22.

The CPU 21 is an RLNTEL 80286 J, which is a 16-bit CPU from Intel Corporation, and the clock generator 30 is an RLNTEL 802134 J,
Hass controller 31 is rlntel 80288J
etc. is Ic.

When reading from the dynamic RAM 22.

The CPU 21 outputs the status signal 80 and the like to the bus controller 31 at the timing shown in the time chart of FIG. 5, and the bus controller 31 sends a memory read command signal MRDC to the memory control circuit 32. The memory control circuit 32 uses the timing based on the fall of this memory read command signal MRDC.

Activate access to the dynamic RAM 22.

Then, the clock generator 30 is notified of the synchronous ready signal 5RDY, and the clock generator 30 sends the ready signal READY to the CPU 21 to enter the first bus cycle.

Some CPUs 21 operate with a clock of, for example, 6MHz or 8M1lz, but clock generators 30. Lotus controller 31. When a family peripheral IC dedicated to the CPU 21, which is normally used, is used as the memory control circuit 32, etc.

Access to the dynamic RAM 22 is controlled by a memory read/write command signal (M
Since it is activated by RD C/MWT C), the activation timing is delayed.

That is, at 6MHz, each state Ts, Tc is 1
67ns and 2 normal speed Dynamis RA
When M22 is used, 1 Wait is required for the CPtJ operation due to a slight timing overflow. In this way, when operating with 6 Mlly, I Wait,
One bus cycle takes 500 ns.

[Problem that the invention seeks to solve]

Using peripheral IC specified by the manufacturer like the conventional method,
When operating the PU 21 at 8MI (z) 1. For example, use a static RAM with an access time of 100 ns or less, or put a Wait on the CPU 21 2. Guarantee the access time to the normal dynamic RAM 22 and use the dynamic RAM 22. It is necessary to choose whether to use it.

However, high-speed static RAM is expensive and has a cost performance problem. Also, when using normal dynamic RAM22, Intel's rI
When one bus cycle consists of two states Ts and Tc, such as Ntel 80286J, W
Inserting the l state using ait will reduce the speed by 50%.

There is a problem in that it greatly affects the processing capacity of the system.

[Means for solving problems]

The present invention aims to solve the above problems and provides a dedicated memory control integrated circuit having functions such as a clock generator and a bus controller.

This memory control integrated circuit has a built-in circuit for decoding status signals s o, s I, M/, to, etc. from the CPU, and immediately after decoding the status signals, the memory control circuit 32 shown in FIG. I am trying to start the part corresponding to . Therefore, access to the dynamic RAM is started from the middle of state Ts. As a result, access to the memory can be started earlier by the number of states, so 1, for example, 8MH
Even in the case of z.

Wait is no longer needed.

〔Example〕

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is an application example of the present invention, and FIG. 3 is a time chart of an embodiment of the present invention.

In FIG. 1, 10 is a memory control IC according to the present invention, 11 is a reset signal synchronization circuit that synchronizes reset signals, and 12 is a status signal S o from the CPU.
S+, a status decode circuit that decodes M/I O, 13 a DMA control circuit that controls DMA,
14 is a memory selection circuit that selects a memory based on address information; 15 is a ready signal synchronization circuit that sends a ready signal RE A DY to the CPU.

16 is a shutdown circuit having a processing function (shutdown logic) when a so-called multiple protection exception occurs; 17
is memory read command signal MRDC, memory write command signal MWTC or input/output command signal ■ORC
18 is a memory timing generation circuit, and 19 is a memory control signal output circuit that outputs a memory control signal.

The memory control IC10 shown in FIG.

For example, it consists of a bipolar gate array of about 600 gates, and as shown in FIG. 2, it is interposed between the CPU 21 and the dynamic RAM 22, and sends out a control signal to access the dynamic RAM 22 in response to a memory access request from the CPU 21. .

FIG. 3 shows a time chart when the CPU 21 is operated at 8 MHz. .

When the status decoding circuit 12 receives the status signal 30 etc. from the CPU 21, the status decoding circuit 12 outputs the decoding result as follows.
Shutdown circuit 16. Control signal output circuit 17. It is transmitted to the memory timing generation circuit 18. The memory timing generation circuit 18.

According to the decoding result, memory control signal output circuit 1 is immediately
9 to start accessing the dynamic RAM 22. This makes it possible to start accessing the dynamic RAM 22 from the middle of state Ts. Therefore, even if the CPU 21 operates at 8 MHz, a time of 187.5 ns can be secured for memory access, and as a result, there is no need to wait for the CPU 21 even when using a normally used dynamic RAM.

The control signal output circuit 17 outputs the memory read command signal MRDC in the state TC phase based on the decoding result of the status signal So.

Furthermore, during the bus cycle period, a latch signal (ALE) for keeping the address signal constant is also output earlier than usual, thereby speeding up access to the memory. Furthermore, a ready signal RE for terminating the bus cycle
ADY is also output from the memory control ICl0 by the ready signal synchronization circuit 15, so that the dynamic RAM 22 is controlled at the best timing overall.

〔Effect of the invention〕

As explained above, according to the present invention, for example, 8MHz, No.
It becomes possible to use the CPU by Wait operation, and it becomes possible to set one bus cycle to 250 ns. Furthermore, since various control functions are housed in a bipolar gate array within one chip, the overall system configuration can be simplified.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is an application example of the present invention, and FIG. 3 is a time chart of an embodiment of the present invention.
FIG. 4 shows an example of the conventional method, and FIG. 5 shows a time chart of the conventional method. In the figure, 10 is a memory control IC, 12 is a status decoding circuit, and 13 is a DMA control circuit. 14 is a memory selection circuit, 15 is a ready signal synchronization circuit, 1
6 is a shutdown circuit, 17 is a control signal output circuit, 1
8 is a memory timing generation circuit, 19 is a memory control signal output circuit, 21 is a CPU, and 22 is a dynamic RA.
Represents M.

Claims (1)

[Claims] A memory control integrated circuit in which one bus cycle consists of a first state Ts and a second state Tc, and which generates and outputs an access control signal to a dynamic RAM based on a status signal from a CPU. There is a circuit (12) that decodes the status signal from the CPU.
); a timing generation circuit (18) that starts accessing the dynamic RAM from the middle of the first state Ts after decoding the status signal; or a circuit (17) for outputting control signals related to input/output in one chip.