JPS58205236A - Internal bus contention preventing circuit - Google Patents

Abstract

PURPOSE:To allow variance of address decoders and data buffers, by realizing high-speed data transfer between an input and an output port in every successive clock period. CONSTITUTION:A signal BSS indicating the address of a port 320 is supplied to the BSS decoder 340 of a unit 30-0 in synchronization with a system clock CLK and when a signal SEL rises, the input port 320 of the unit 30-0 is energized to send data DATA latched therein out to a bus 40. A signal BDS indicating the address of a port 1 is inputted to the BDS decoder 342 of a unit 30-1 in the same period of the clock CLK. When the signal SEL falls and a leading edge of a latch signal LCH arrives, an output port 322 is energized to latch data on the bus 40, i.e. data DATA transferred from the port as effective data at the port.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides an internal bus contention prevention circuit, in particular, an internal bus contention prevention circuit, in which a data source such as an input port is connected to a bidirectional common parallel transmission line (bus), and operates in synchronization with a system clock. This invention relates to an internal bus contention prevention circuit in processing devices such as micro processors and other devices.

In such processing devices, conventionally, when data is transferred from a data source such as an input port connected to a bidirectional data bus to a data sink such as an output port, data is transferred from the input beat to the central processing unit in one clock cycle. Data was transferred to a register within the (CPU), and data was transferred from this register to the output port at the next clock. Therefore, data transfer between input and output ports requires at least two clock cycles.

For example, when processing a large amount of input data such as image data and forming an output image from the processed result data, it is often necessary to operate on a large number of parallel bits, such as 24 bits, at high speed. For example, complex calculations such as unsharp mask processing must be executed in a short period of 20 microseconds. It is advantageous to perform such high-speed operations on a large number of parallel bits with a processing device having a bit slice configuration. As mentioned above, in a data transfer control system that requires two cycles for data transfer between human output ports, the effect of such high-speed arithmetic processing is canceled out. Therefore, it is desirable to have a system configuration that does not waste time on relatively simple operations such as port-to-port transfer, and can provide time margin for arithmetic processing specific to the application.

Therefore, a data transfer method is conceivable in which data transfer between input and output ports is completed within one clock cycle. Near the end of one clock period, a latch signal is provided to the device to which the data is transferred, such as an output port, which identifies the data as valid, thereby causing the output port to retain the data. Generally, a bidirectional path has a data source and a data sink commonly connected. Therefore, at the boundary of the black and ri cycles, the current black,
The output of the data source that was transferring data at the next clock cycle may be delayed due to variations in the propagation delay time of the address decoder, data source output, group, etc.

may remain at the beginning of the cycle. In such cases, the outputs of the two data sources compete on the bidirectional path, generating large currents that can damage elements within the integrated circuit or cause noise.
may occur, resulting in malfunction.

The input/output port circuit connected to the path of the processing device generally has both input ports and output ports on one electronic circuit board to form one package unit. It is desirable (and economical) in terms of reducing the amount of water and standardizing its management.
This type of unit is equipped with both an input port and an output port in one package unit.

A system is conceivable in which the i-port is connected to the path at the middle level. A plurality of ports may be installed on one unit, and in that case, it is preferable that the upper few digits of the port address specify the unit number and the lower several digits specify the port number. Conflicts between the outputs of multiple data sources on a path due to element variations can be avoided by installing a conflict prevention function between data sources for each unit, which outputs data after confirming that there are no outputs from other data sources on the path. This can be avoided by adding .

However, in such a system in which -C input/output ports coexist within one unit via internal paths, the data source output varies and remains at the end of one clock cycle as described above, and the next The problem of internal contention between the output of a receiver that receives data from another data source at the beginning of a clock cycle cannot be solved by the contention prevention function between data sources. In other words, between the input port and the path receiver included in one unit, it is necessary to prevent outputs from competing on the internal path due to variations in the propagation delay time of circuit elements such as address decoders and data buffers. .

An object of the present invention is to provide an internal path contention prevention circuit that eliminates these drawbacks, prevents output contention between a data source and a path receiver on an internal path, and enables high-speed data transfer. shall be.

This objective is achieved by an internal path contention prevention circuit according to the invention as follows. In other words, this circuit is a transmitting/receiving circuit that transfers data every cycle of a black signal between a first bidirectional transmission path and a second bidirectional transmission path that are commonly connected to a data source and a data sink. An internal/mass contention prevention circuit for controlling output contention in a first bidirectional transmission path between a data source and a transmitting/receiving circuit,
a delay circuit that receives a first signal indicating that a data sink is selected and generates a second signal that is a predetermined delay of the first signal; a second signal; and a data source that is selected. and a control circuit that controls the transmitting and receiving circuit to transfer the signal from the second bidirectional transmission path to the first bidirectional transmission path when both of the third signals are present.

Next, embodiments of the internal gas contention prevention circuit according to the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 shows an example of a processing device to which an internal bus contention prevention circuit according to the present invention is applied, and is comprised of a microcontroller. In the same figure, the central processing unit (CPTJ)
Connected to data bus 40 are read only memory (ROM) 20, random access memory (RAM) 22, and input/output circuits 30-0 and 30-1. - The cell 40 is, for example, an 8-bit parallel bidirectional transmission line. Note that in the figure, bidirectional transmission paths for parallel bits are indicated by arrows in both directions.

As is well known, the CPU 10 has a control section 12 that decodes and executes instructions, and a renostar/arithmetic logic operation section 14 as an area that performs various arithmetic and logical operations. R.O.
The M 20 stores program instructions, fixed data, etc., and the RAM 22 functions as a high-speed memory for the system. The input/output circuits 30-0 and 30-1 include an input/output port 32 and an input/output control circuit 34. In this example, two input/output circuits are provided, but any number of input/output circuits may be provided within the limit of specifying the address of the input/output port in the system.

Input/output capo-1/32 has data bus 40 and input/output terminal 5O
A circuit that interfaces with an external input/output device (including a processing device) connected to -Of or 50-1,
Includes data controllers, channels, path drivers/receivers, etc. The input/output control circuit 34 includes a decoder that decodes the input/output address sent from the control unit 12 through the control line 42;
It also includes a circuit for preventing contention between input and output ports, which will be described in detail later. The input/output circuits 30-0 and 30-1 may each be mounted on one electronic circuit board to constitute each unit. The specific configuration of one of the units is shown in FIG.

The input/output circuit 30 shown in FIG. 2 includes an input port or data source 320 and an output column 320. - a data sink 322 and a path driver/receiver 324, which constitute the input/output port 32 of FIG. The input port 320 and the output port 322 are, for example, 8 bit, 1.
Including data ra and chi. The input terminal 500 to which input data is supplied from an external input device is input 4? The output of the human power I-1 320 is connected to a path driver/receiver 324 via a parallel transmission line 350. A path driver/receiver is connected to data bus 40.

The transmission line 350 is also connected to the input of the output port 322, and the output of the output port 322 is connected to the output terminal 502 to which the output device is connected.

Input terminal 500 and output terminal 502 constitute input/output terminal 50-0 or 50-1 in FIG. In FIG. 2, the parallel bit transfer paths are indicated by arrows indicating the transfer direction. Further, although this embodiment uses 8-bit parallel processing, that is, an 1-word 8-bit configuration, it goes without saying that the present invention can also be effectively applied to a 16-bit or more bit configuration using the bit slicing method.

The circuit 30 in FIG. 2 includes a BSS decoder 340, a BDS decoder 342, and a path conflict prevention circuit 344 as the input/output control circuit 34 (FIG. 1). The BSS decoder is
A signal BSS indicating the input port number (address) sent from the control unit 12 via the control line 420, which is one of the control lines 420.
, and this is the input contained in the unit 30,
When indicating p-to 320, lead 35 is activated in response to the signal layer of control line 426 indicating that signal BSS is significant.
The decoding circuit energizes the input port 320 through the input port 320.

The BDS decoder is also connected from the control section 12 to the control line 42.
This is a decoding circuit that decodes a signal BDS indicating an output port number sent through one of the ports 422 and 422. Signal BDS
indicates the output port 322 included in the own unit 30, the signal layer of the control line 426 and the latch signal LC
In response to H, output port 322 is energized through lead 354. In addition, as explained later, the child signal LC
H does not necessarily have to be provided.

The path conflict prevention circuit 344 prevents conflicts in the use of the path 40 between the units 30-0 and 30-1 and the CPU I00, and also prevents conflicts in the use of the path 40 between units 30-0 and 30-1 and the CPU I00.
Conflict in sending and receiving data on path 350 within 0,
That is, it is a circuit that prevents contention between the human power port 320 and the path receiver 324. To this end, the leads 424 of the prevention circuit 344 are connected to each unit, ) 30-0 and 30
-1, and the prevention circuit 344 attaches the lead 356 after confirming that the signal layer from the other unit or gate is in the de-energized state when the own unit or gate 30 is selected. The path driver/receiver 324 is activated, and the lead 424 is driven to activate the signal ACK. This will be explained in detail later.

These control signals BSS, BDS, SEL and LCH are synchronized with the system clock CL in the CPU 10.
The time relationship is shown in FIG. The system clock CLK is created from the basic clock within the control unit 12 and has a period of, for example, 180 nanoseconds.

Signals BSS, EDS, and BLACK are delayed by a predetermined phase φ with respect to the rising edge 600 of clock CLK. This delay φl is due to the propagation delay of the circuit elements. First, the child signal LCH has the same waveform as the clock CLK, and leads the clock CLK by a predetermined phase φ2.

For example, assume that data is transferred from the input port 320 (port 0) of the uni, ) 30-0 to the output port 322 (port 1) of the uni, ) 30-1. In synchronization with the system clock CLK, a signal BSS indicating the address of port 0 is supplied to the BSS decoder 340 of the unit 30-0, and when the signal ≦IL falls, the signal BSS indicating the address of port 0 is supplied to the unit 30-0.
The human power port 320 is energized and the data stored thereon, DATA, is sent out onto the path 40.

On the other hand, within the same period of rio7ri CLK, 12,)
A signal BDS indicating the address of port 1 is input to the BDS decoder 342 of 30-1.

When the signal layer falls and then the rising edge 602 of the child signal LCH arrives, the output p-4322 is activated,
The data on the path 40, that is, the data DATA transferred from -+beat 0, is passed to 2-2 as valid data.
be touched. From port 0 by this? This means that the data transfer to port 1 was performed within one cycle of the system clock CLK. In addition, Uni, To ao-o to Uni, To3
Although we have described the case where data is transferred between different units, ie, between different units, it is also possible to transfer data from the input port 320 to the output port 322 within the same unit, for example, 30-θ. The same applies to the case.

In the embodiment of FIG. 2, the output port 322 includes a signal L
In response to the rising edge 602 of CH, the data is written. Since the rising edge 602 is a little earlier in time than the rising edge 600 of the clock CLK, there is sufficient time to hold the data. It is desirable that the output port 322 be configured to read data in response to the child signal LCH, but when the latch signal LCH rises 602
Instead, data may be held in synchronization with the rising edge 600 of the clock CLK. In this case, BD
The control line 428 of the S decoder 342 is supplied with a signal CLK instead of the signal LCH. However, when configured like this, the IBSS, BD
Since the state of all signals such as S and SEL changes,
When the output port 322 retrieves data, there is a possibility that the retention time may become somewhat strict.

A specific configuration of the path conflict prevention circuit 344 is shown in FIG. This circuit 344 consists of two parts: a data source conflict prevention circuit 700 that prevents conflicts between data sources such as input ports 320 of different units l-30-0 and 30-1;
and an internal contention prevention circuit 800 for preventing contention between zeros.

The data source conflict prevention circuit 700 includes an OR chain 02,
It consists of an AND gate 04 and an inverter 706. The inverter 706 is an IC that has the output of an auto collector, and its output is an OR key.
The control line 424 is connected to one input of the unit 30, and is also commonly connected to the corresponding part of the other units 30 in a wired OR format as the control line 424, as described above. This signal is the craft. OR case - Door 02's output cuff 08 is A, ND case.
- Connected to one input of door 04,
The other input of 4 is the output of the BSS decoder 340, that is, the output 352 which decodes the address of the input capo-1-320.
It is connected to the. AND cage-door 04 out cuff 10
is connected to the input of inverter 706, the other input of OR gate 02, and one control line 356B to the driver/receiver 324. Control line 356B constitutes control line 356 in FIG. By energizing it, path driver/receiver 324 is configured to operate as a driver for transmitting data onto path 40 .

Input port address decoding output 3 of BSS decoder 340
52 is an AND gate 80 of the internal contention prevention circuit 800.
It is also connected to one inverting input of 2. ANDke'
The other input 804 of the output 802 is connected to the output 354 of the BDS decoder 342 via a delay circuit 806. As previously mentioned, the output 354 of BDS decoder 342 is the decoded output of the address of output port 322 (FIG. 2). As will be explained later, the delay circuit 806
This circuit provides the output with a delay τ (FIG. 6) that compensates for variations in propagation delay time of elements included in the S decoder 340, the BDS decoder 342, and the like. In one example, it is desirable to provide a delay on the order of 30-50 nanoseconds from the rising edge of input 354 to the rising edge of output 804.

The output of the AND gate 802 is a pass driver and constitutes the other control line 356R of the receiver 324. Control line 356R constitutes control line 356 of FIG. 2 and is energized to configure path driver/receiver 324 to operate as a receiver for receiving data from path 40. Control line 356R constitutes control line 356 of FIG. Note that the path conflict prevention circuit 344
For convenience of explanation, it has been explained as a logic circuit including an AND gate, an OR gate, and an inverter, but in reality it can also be configured with a logic circuit consisting of a NAND gate or a NOR gate. good.

Referring to FIG. 5, one period φC1 of black and white CLK
Uni, i・0 input port) 320 (input, ff-to 0
) sends data DATA to path 40, and the next period φC
Assume that the input port 320 (input port 1) of unit 2 sends data DATA to the path 40. Uni at clock cycle φC1.

The data source contention prevention circuit 700 of 1-1 is in a dormant state, and the output voltage 10 of the AND key 4704 is set low. The signal 424 on the control line 424, which is commonly connected to unit 0 and field OR, is kept at a low level by the data source contention prevention circuit 700 of unit 0 while input port 0 is transmitting data. Therefore, the output cuff 08 of the OR gate 02 of the competition prevention circuit 700 of the unit 1 is at a low level because both human forces are at a low level. Next period φC
2, when the BSS decoder 340 of unit 1 detects the address of the input port 320 of its own unit, the control line 352
becomes high level. If the data source conflict prevention circuit 700
were not provided, units O and 1
Due to variations in the propagation delay times of circuit elements such as the BSS decoder 340, the path drivers/receivers 324
may be driven simultaneously, and the data DATA of input ports 0 and 1 may conflict on path 40.

However, in this embodiment, the data source conflict prevention circuit 700 of the unit 1 confirms the completion of data transmission from the input port O at the rising edge 610 of the signal (FIG. 5), and then
data DATA is sent to the path 40.

When the output 352 of the BSS decoder 340 of unit 1 becomes high level, the AND key of the contention prevention circuit 700
One input 352 of 04 is activated. However, uniz
As long as the low level signal ACK is sent from the unit 0 to the control line 424, the other input cuff 08 of the AND cage 04 of unit and unit 1 is de-energized. Therefore, unit 1
Even if one input 352 of the AND key 04 is energized by the BSS decoder 340 of the unit 1, the output cuff 10 is at a low level, so the output driver/receiver 324 of the unit 1 is not driven. .

When input port O finishes sending data, unit, port 0
The data source contention prevention circuit 700 prevents signal interference from occurring at a high level 61
0 (Figure 5). Therefore, OR key of unit 1)
The output cuff 08 of 702 becomes high level due to the high level signal V〒.

Therefore, in the AND key door 04, both the human forces 352 and 708 are at a high level, and the output cuff 10 is at a high level. As a result, the path driver/receiver 324 of unit 1 is driven as a path driver since the control line 356B is energized, and the data DATA of input port 1 is driven as a path driver.
is sent on path 40. At the same time, the high level on output cuff 10 is inverted by inverter 706 and control line 424
is sent as a low level signal ACK. OR key
The door 02 has one input 424 at a low level, but the other input cuff 10 has a high level, so the AND key 704
Continue to energize one of the inlet cuffs 08. Therefore, as long as unit 1's BSS decoder 340^; output 352 is held high, unit 1's bus driver/receiver 324 continues to function as a driver.

The low level signal is wired OR connected to the control line 42.
4 to the data source contention prevention circuit 700 of Uniy) 0, and prohibits input port 0 from functioning as a data source in the clock cycle φC2. In this manner, data source conflict prevention circuit 700 prevents output conflicts on path 40 between input ports 320.

By the way, the internal path 3 is connected between the input port 320 and the path receiver 324 included in the same unit (for example, 0).
Both outputs at 50 may conflict. That is, the output output from the pass driver receiver 324 to the operating internal path 350 may conflict with the output of the input port 320. The internal conflict prevention circuit 800 prevents this.

As shown in FIG. 6, for example, when one cycle of the clock CLK is φC:3, the input is 1? - Data DATA is read out from port 320 onto path 40, and in the next cycle φC4, data DATA is read from bus 40 to output port 322 in the same unit.
Suppose that the ATA can be written to.

Assuming that there is no internal conflict prevention circuit 344, black,
At the boundary between the periods φC3 and φC4, due to variations in the propagation delay times of the circuit elements included in the BSS decoder 340 and the BDS decoder 342, the input, t? - The output from bus driver/receiver 324 acting as a path receiver and the output from bus driver/receiver 324 may conflict on path 350. The large current caused by this competition may damage elements within the integrated circuit or cause malfunction due to noise generation.

In order to prevent this conflict, a delay circuit 806 is provided to compensate for variations in propagation delay times of circuit elements. Since the input port address decoding output 352 of the BSS decoder 340 is activated in clock period φC3, the AND r'-to 802 of the internal conflict prevention circuit 800 is deactivated.

When the black and white period φC3 ends, the decoder output 352
becomes low, and one input of AND gate 802 is energized via an inverter.

After a short delay, the input port 320 is de-energized.

When the BDS decoder 342 identifies the address of the output port 322 of its own unit in the next cycle φC4 of the clock CLK, the decoded output 354 becomes high level. This high level is transmitted to the other input 804 of AND gate 802 after a delay time .tau. (FIG. 6) of delay circuit 806. During this period τ, the output 352 of BSS decoder 340
becomes completely low level. Input port 320 is also completely deactivated, and the input at path 350, t? −)
The output of 320 also disappears completely. The high level on lead 804 causes the output 356R of AND gate 802 to go high, causing bus lipper/repairer 324 to perform a receive operation and data DATA on path 40 to be transferred to output port 322.

If the BSS decoder 340 of that unit is driven again at the beginning of the period φC5 following the period φC4,
Since the decoded output 352 becomes high level, AND gate 8
02 immediately de-energizes output 356R. This causes the path driver/receiver 324 to stop operating as a receiver.

Furthermore, even if the BSS decoder 340 of that unit is not driven by 1, the output port 322 at the end of the period φC4
When writing of data to the BDS decoder 32 is completed, the BDS decoder 32
The output 354 of 4 becomes low level, AND key-)80
The output 356R of 2 is deenergized and stops functioning as a helical driver/receiver 324id register. Therefore, the path driver/receiver 324 operates as a path receiver and the output output to the path 350 has a period φC
The input capo that is driven next at the boundary between 4 and φC5)
320 output and on path 350 are prevented. In this way, output conflicts on internal path 350 are prevented when going from reading from input port 320 to writing to output port 322 and vice versa within the same unit.

゛ In order to avoid complicating the explanation, an example in which one input/output circuit unit 30 is provided with a single input port 320 and output port 322 has been described.
Even when a plurality of these are provided in one unit, the path conflict prevention circuit 344 can function in the same manner as described above. In that case, the bus contention prevention circuit 344 treats these multiple input/output capacitors 320 and 322 as one group. Therefore, the decoded output 3 of BSS decoder 340
52 is expanded for each individual input port 320, but the input of the AND gate o4 of the data source contention prevention circuit 700 and the input of the AND gate 802 of the internal contention prevention circuit have common information for the group. , that is, the input/output circuit unit 30 is logically summed and supplied as a single signal. The same is true for the decoding output 354 of the BDS decarder 342, and the decoding output 354 is developed for each individual output port 322, but the input of the delay circuit 806 of the internal contention prevention circuit 8oo has a logic for that group. The sum is taken and supplied as a single signal.

The internal path contention prevention circuit according to the present invention is configured as described above, so that even if there are variations in circuit elements such as address decoders and data buffers, the output of the data source and the bus receiver can be controlled near the boundary of the clock cycle and the bus receiver. High-speed data transfer between input and output ports can be achieved in each successive clock cycle without conflicting with the output on the internal path. Therefore, not only can a certain degree of variation be tolerated in circuit elements such as address decoders and data buffers, but also by standardizing the unit by mounting both input ports and output ports on one electronic circuit board unit. , Uni,
It is possible to reduce the number of types of ports, simplify management, and make it possible to configure the system economically. Furthermore, circuit elements are not destroyed by large currents during output competition, and malfunctions due to noise do not occur. However, data transfer between ports can be completed within one cycle of 7 stem clocks in this way, so if applied to a bit slice processor, for example, high-speed arithmetic processing can be performed more effectively. Note that each of the above-mentioned signals, namely CLK and Bss.

If the BDS, SEL, LCH, etc. are configured to be directly controlled by a microprogram, calculations in the ALU in the processing unit and data transfer between these independent ports can be performed simultaneously in one clock.

The process can be completed within a short period, and high-speed processing can be achieved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of a processing device to which the internal bus contention prevention circuit according to the present invention can be applied, FIG. 2 is a block diagram showing the configuration of the input/output circuit in FIG. 1, and FIG. 2 is a signal waveform diagram showing the operation of the circuit shown in FIG. 2, FIG. 4 is a block diagram showing a specific configuration example of the bus contention prevention circuit shown in FIG. 2, and FIGS. 5 and 6 are diagrams showing the operation of the circuit shown in FIG. 4. FIG. Explanation of symbols of main parts 30... Input/output circuit 40... Data bus 320... Input port 322... Output port 340... BSS decoder 342... BDS decoder 344... Bus contention prevention circuit 700... Data Source conflict prevention circuit SOO...Internal conflict prevention circuit 806...Delay circuit 1st column 3 (-1 Shomon- Figure 2 ff'5t.1 Tin amount -6'.

Claims (1)

[Claims] 1. Transferring data every cycle of a clock signal between a first bidirectional transmission path and a second bidirectional transmission path that are commonly connected to a data source and a data sink. Internal bus contention prevention 1 for controlling a transmitting/receiving circuit and preventing output contention on a first bidirectional transmission path between the data source and the transmitting/receiving circuit;
1-A delay circuit that receives a first signal indicating that the data sink is selected and generates a second signal by delaying the first signal by a predetermined time; and a second signal; and a third signal indicating that the data source is not selected, controls the transmitting/receiving circuit to transfer data from the second bidirectional transmission path to the first bidirectional transmission path. An internal bus contention prevention circuit comprising a circuit. 2. In the internal bus contention prevention circuit according to claim 1, the control circuit switches the second bidirectional transmission path from the second bidirectional transmission path to the first bidirectional transmission path in response to the disappearance of the third signal. An internal bus contention prevention circuit characterized by stopping data transfer.