JPS58205235A - Preventing circuit against data source contention - Google Patents

Abstract

PURPOSE:To prevent output contention between data sources such as input ports and to perform high-speed data transfer, by connecting the data sources to a two-way common parallel transmission line and operating them in synchronization with a system clock. CONSTITUTION:A bus contention preventing circuit 344 prevents the contention of the use of a bus 40 between units 30-0 and 30-1, and a CPU10, and also prevents the contention of data transmission and reception in the units 30, i.e. contention between an input port and a bus receiver. For this purpose, the lead 424 of the preventing circuit 344 is connected in common between the units 30-1 and 30-1 and when its own unit 30 is selected, the circuit 344 confirms that a signal ACK from the other unit is off, and then energizes a lead 356 to put a bus driver/receiver 342 in operation while driving the lead 424 to activate the signal ACK.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data source contention prevention circuit, and in particular to a data source such as a microprocessor in which a data source such as an input port is connected to a bidirectional common parallel transmission path and operates in synchronization with a system clock. The present invention relates to a data source conflict prevention circuit in a processing device such as the above.

Conventionally, in such processing devices, when data is transferred from a data source such as an input port connected to a bidirectional data bus to a data sink such as an output port, data is first transferred from the input port to the central processing unit (CPU) using one clock. )
Data was transferred to a register inside the device, and data was transferred from this register to the output port on the next clock. Therefore, data transfer between input and output ports requires at least two clock cycles.

For example, when processing a large amount of input data, such as image data, and forming an output image from the processed data, it is often necessary to operate on a large number of parallel bits, such as 24 bits, at high speed. For example, complex calculations such as unsharp mask processing must be executed in a short period of 20 microseconds. It is advantageous to perform such high-speed operations on a large number of parallel bits with a processing device having a bit slice configuration. In a data transfer control system that requires two clock cycles to transfer data between input and output ports as described above, the effect of such high-speed arithmetic processing is canceled out. Therefore, it is desirable to have a system configuration that can provide time margin for application-specific calculation processing without wasting time on relatively simple operations such as transfer between boats.

Therefore, a data transfer method can be considered in which data transfer between input and output ports is completed within one clock cycle. This provides a latch signal that identifies data as valid around one clock period to a device to which the data is transferred, such as an output port, so that the output port retains the data. Generally, however, multiple data sources, including input ports, are commonly connected to a system path. Therefore, at the boundary of the clock cycle, the output of the data source that was transferring data in the current clock cycle may change to the next clock due to variations in gate propagation delay time in the address decoder, data source output buffer, etc. It may conflict with the output of a data source that transfers data periodically. If the data source outputs compete on the path, even if temporarily at the boundary of the clock period, noise may be generated due to excessive current, causing malfunctions or causing problems within other integrated circuits (ICs). There is a possibility that the device may be destroyed.

SUMMARY OF THE INVENTION An object of the present invention is to provide a data source conflict prevention circuit that eliminates these drawbacks, prevents output conflicts between data sources, and enables high-speed data transfer.

This objective is achieved by a data source contention prevention circuit according to the invention as follows. In other words, in this circuit, a plurality of data sources are connected to a common transmission path, and data is outputted from one of the plurality of data sources selected by a processing device to the common transmission path in one cycle of a clock signal. In a data transfer method that transfers this data to a sink, a data source conflict prevention circuit is provided corresponding to a group of data sources returning from at least one data source, and the data sources of the group output data to a common transmission path. a signal generation circuit that generates a first signal indicating that the data source is in the middle of the data source conflict prevention circuit on a first signal path commonly connected to each data source contention prevention circuit; a signal detection circuit for detecting (the signal generation circuit is connected to the output of the signal detection circuit, and when one data source included in the group of data sources corresponding to the data source conflict prevention circuit is selected, When the signal detection circuit detects the absence of a first signal associated with another group of data sources, it causes data to be output from the selected data source and generates a first signal on the first signal path. This prevents conflicts between multiple data sources.

Next, embodiments of the data source conflict prevention circuit according to the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 shows an example of a processing device to which a data source conflict prevention circuit according to the present invention is applied, and is composed of a microprocessor. In the figure, the central processing unit (CPU)
10, a read-only memory (ROM) 20, a random access memory (RAM) 22, and input/output circuits 30-0 and 30-1 are connected to a data bus 40. Path 40 is, for example, an 8-bit parallel bidirectional transmission line. Note that in the figure, bidirectional transmission paths for parallel bits are indicated by arrows in both directions.

As is well known, the CPU 10 has a control section 12 that decodes and executes instructions, and a reno/arithmetic logic operation section 14 as an area that performs various arithmetic and logical operations. R
The OM 20 stores program instructions, fixed data, etc., and the RAM 22 functions as a high-speed memory for the system. The input/output circuits 30-0 and 30-1 include an input/output port 32 and an input/output control circuit 34. In this example, two units of input/output circuits are provided, but any number of units can be provided within the limit of specifying addresses of input/output ports in the system.

The input/output port 32 is connected to the data bus 40 and the input/output terminal 50-
This circuit interfaces with an external input/output device (including a processing device) connected to 0 or 50-1, and includes a data latch, a path driver/receiver, etc. The input/output control circuit 34 includes a decoder for decoding the input/output port address sent from the control unit 12 through the control line 42, and a circuit for preventing contention between input/output ports, which will be described in detail later. The input/output circuits 30-0 and 30-1 may each be mounted on one electronic circuit board to constitute each unit. The specific configuration of one of the units is shown in FIG.

The input/output circuit 30 shown in FIG. 2 has an input port or data source 32o1, an output port or data sink 322, and a path driver/receiver 324, which constitute the input/output port 32 in FIG. Input port 320 and output port 322 include, for example, 8-bit data latches. An input terminal 500 to which input data is supplied from an external input device is connected to the input port 320,
The output of input port 320 is connected to path driver/receiver 324 via parallel transmission line 350. A path driver/register is connected to data bus 40.

The transmission line 350 is also connected to the input of the output port 322,
The output of N-to 322 is connected to an output terminal 502 to which an output device is connected.

Input terminal 500 and output terminal 502 constitute input/output terminal 50-0 or 50-1 in FIG. In FIG. 2, the parallel bit transfer paths are indicated by arrows indicating the transfer direction. Although this embodiment uses 8-bit parallel processing, that is, one word has an 8-bit configuration, it goes without saying that the present invention can also be effectively applied to a 16-bit or more bit configuration using the bit slicing method.

The circuit 30 in FIG. 2 has a BSS decoder 340, a BDS decoder 342, and a path conflict prevention circuit 344 as the input/output control circuit 34 (FIG. 1). The BSS decoder receives a signal B indicating an input port number (address) sent from the control unit 12 via 420, which is one of the control lines 4z.
When the SS is decoded and indicates an input port 320 included in its own unit 30, the lead 3 is decoded in response to a signal on the control line 426 indicating that the signal BSS is significant.
A decoding circuit that powers input port 320 through 52.

The BDS decoder also receives an output signal 422 sent from the control section 12 via one of the control lines 422. - This is a decoding circuit that decodes a signal BDS indicating a port number. When the signal BDS indicates the output port 322 included in its own unit 30, the signal SEL on the control line 426 and the latch signal L
Output port 322 through lead 354 in response to CH
energize. Note that, as explained later, the latch signal L
CH does not necessarily have to be provided.

The path conflict prevention circuit 344 prevents conflicts in the use of the path 40 between the units 30-0 and 30-1 and cPUlo, and prevents data transmission and reception on the path 350 within the unit 30 itself. This is a circuit that prevents contention, ie, contention between input port 320 and controller 324. For this purpose, the prevention circuit 34
4 leads 424 connect to each unit 30-0 and 30-1.
When the own unit 30 is selected, the prevention circuit 344 prevents the signal T from other units from being connected.
After confirming that the signal is in the de-energized state, the lead 356 is energized, the path driver/receiver 324 is activated, and the lead 424 is driven to energize the signal source. This will be explained in detail later.

These control signals BSS, BDS, SEL and LCH are connected to the system clock CL in the CPU 10.
The time relationship is shown in FIG.

The system clock CLK is created from the basic clock within the control unit 12 and has a period of, for example, 180 nanoseconds. Signals BSS, BDS and flight clock CL
It is delayed by phase φ1 with respect to the rising edge 600 of K. This delay φ1 is due to the propagation delay of the circuit facing elements. Latch signal LCH has the same waveform as clock CLK, and leads clock CLK by a predetermined phase φ2.

For example, the input port 32° (, f?
-)0) to the output port)322 (port 1) of the unit)30-1. In synchronization with the system clock CLK, a signal BSS indicating the address of port 0 is sent to unit 3O-0 (7) BSS decoder 3.
40, and when the signal SEL falls, the unit)
30-00 Å, the e-tos is energized and the data DATA' latched thereon is sent out on path 40. On the other hand, within the same cycle of the clock CLK, a signal BDS indicating the address of port 1 is input to the BDS decoder 342 of the unit 30-1. When the signal I falls and the latch signal LCH rises 602, the output (N-) 322 is activated, and the data on the path 40, that is, the data DATA transferred from port 0, is transferred to port 1 as valid data. latched to. As a result, the system clock C is transferred from tE'-)0 to port 1.
This means that data transfer was performed within one LK cycle.

We have explained the case where data is transferred from the unit 30-0 to the unit 30-1, that is, between different units. The same applies when transferring data.

In the embodiment of FIG. 2, output port 322 has a latch signal L
Data is latched in response to the rising edge 602 of CH. Since the rising edge 602 is a little earlier than the rising edge 600 of the clock CLK, there is sufficient time to hold the data. It is desirable that the output port 322 be configured to latch data in response to the latch signal LCH, but when the latch signal LCH rises 602
Instead, data may be held in synchronization with the rising edge 600 of the clock CLK. In this case, BD
A clock CLK is supplied to the control line 428 of the S decoder 342 instead of the signal LCH. However, with this configuration, BSS and B are synchronized with clock CLK.
Since the states of all the signals such as DS and SEL change, when the output capacitor 322 latches the data,
There is a possibility that the retention time becomes somewhat strict.

A specific configuration of the path conflict prevention circuit 344 is shown in FIG. This circuit 344 consists of two parts, namely a data source conflict prevention circuit 7 that prevents conflicts between data sources such as input ports 320 of different units 30-0 and 30-1.
00, and an internal conflict prevention circuit SOO that prevents conflicts between the input f-) 320 and the path driver/register 324.

The data source conflict prevention circuit 700 includes an OR dart 702,
AND gate 704. and an inperter 706. The inverter 706 is an IC with an open collector output, and its output is connected to one input of the OR gate 702, and the control line 424 is connected as described above.
As shown in FIG. This signal is troublesome. O
The output gate 08 of the R gate 702 is connected to one input of the AND gate 704, and the other input of the AND gate 704 is connected to the BS
It is connected to the output of the S decoder 340, ie, the output 352 which decodes the address of the input port 320. AN
The control line 356B of the D gate 704 is connected to the input of the inverter 706, the other input of the OR dart 702, and one control line 356B to the driver/register 324. A control line 356 is configured. By energizing this, the gas driver/
The register 324 is configured to act as a driver to send data to the path 40.

Input port address decoding output 3 of BSS decoder 340
52 is an AND gate 802 of the internal conflict prevention circuit SOO.
It is also connected to one inverting input of the . AND gate 8
The other input 804 of 02 is connected to BD via a delay circuit 806.
It is connected to the output 354 of the S decoder 342. As previously mentioned, the output 354 of BDS decoder 342 is the decoded output of the address of output port 322 (FIG. 2). As will be explained later, the delay circuit 806 has a delay τ that compensates for variations in propagation delay time of elements included in the BSS decoder 340, BDS decoder 342, etc.
(Fig. 6) is a circuit that provides an output. In one example,
30~ from the rising edge of input 354 to the rising edge of output 804
It is desirable to provide a delay of about 50 nanoseconds.

The output of AND gate 802 is a path driver/register.
This constitutes the other control line 356R of the line 324. The control line 356R constitutes the control line 356 in FIG.
is configured to operate as a cash register for receiving color data. Note that the path conflict prevention circuit 344 is constructed using an AND gate and an OR gate for convenience of explanation.
Although it was explained as a logic circuit including a converter and an inverter,
Actually, it may be constructed from a logic circuit consisting of a NAND gate or a NOR gate.

Referring to FIG. 5, one period φC of clock CLK]
And the input of Uni and ToO? -) 320 (input, t?
-) 0) sends data DATA to the path 40, and in the next cycle φC2, the input port 320 (input port 1) of Unit 1 sends data DATA to the path 40. In the clock cycle φC1, the data source contention prevention circuit 700 of unit l is in a dormant state.
704's cuff 10 is low and Beltual. The signal type of the control line 424, which is commonly connected to Uni, To0 and wired OR, is human power, 1? -) During data transmission of 0, the data source contention prevention 11-circuit 700 of unit 0 keeps the level low. Therefore, when there is a conflict between Uni and Tri [14 circuits 7
Since the OR group 02 of 00 has a low level of both human strength, the chemical cuff 08 is at a low level.

In the next cycle φC2, when the BSS decoder 340 of unit 1 detects the address of the input port 320 of its own unit, the control line 352 becomes high level. If the data source conflict prevention circuit 700 were not provided, due to variations in the propagation delay time of circuit elements such as the BSS decoder 340 of units 0 and 1, the Gus driver/
・The cash register 324 may be driven at the same time,
Input on Gus 40? - The data DATA of data 0 and 1 may conflict with each other. However, in this practical example,
After the data source conflict prevention circuit 700 of No. 1 confirms the completion of data transmission from input port 0 at the rising edge of the signal 610 (FIG. 5), the input a? - send data DATA of x to path 40;

When the output 352 of the BSS decoder 340 of unit 1 goes high, the AND key of the contention prevention circuit 700
One input 352 of 04 is activated. However, as long as a low level signal is sent to the control line 424 from unit 0, the other input cuff 08 of unit 1's AND key 704 is deenergized.
Even if one input 352 of the AND cage 04 is energized by the 0BSS decoder 340, the output cuff 10 is at a low level, so the striker/receiver 324 of the unit 1 is not driven. do not have.

When input port 0 finishes sending data, unit 0
The data source contention prevention circuit 700 in FIG. Therefore, the OR of unit 1
- The output cuff 08 of the door 02 becomes high level due to the high level signal section.

Therefore, both human forces 352 and 708 of the AND cage 04 are at a high level, and the output cuff 10 is at a high level. As a result, unit) 1's driver/recino' 32, :, 4 id, control ff) 1 + ti13
Since 56B is energized, it is driven as a pass driver and sends data DATA of input port 1 onto -mass 40. At the same time, the high level of the outcuff is 7.
06 and sent to the control line 424 as a low level signal ACK. The OR key 702 continues to energize one input cuff 08 of the door 04 because one input 424 is low but the other input cuff 10 is high. BS of 1
While the S decoder 340 has output 352 high, the pass driver/register 324 of unit I continues to function as a driver.

The low level signal section is wired OR connected to the control line 42.
4 to data source conflict prevention circuit 700 of unit 0, and prohibits input port 0 from functioning as a data source in clock period φC2. In this manner, data source conflict prevention circuit 700 prevents output conflicts on path 40 between input ports 320.

By the way, both outputs on the internal path 350 may conflict between the input, 1-) 320 and the path receiver 324 that are included in the same unit (for example, 0). That is, the output output from the bus receiver 324 to the internal path 350 may conflict with the output from the input port 320. The internal conflict prevention circuit 800 prevents this.

As shown in FIG. 6, for example, data DATA is read out from the input port 320 onto the path 40 in one cycle φC3 of CLK, and in the next cycle φC4, the data is read out from the path 40 to the output port 322 in the same unit. Suppose that DATA is written.

Assuming that there is no internal conflict prevention circuit 344, black,
At the boundary between periods φC3 and φC4, the propagation l! of the circuit elements included in the BSS decoder 340 and the BCS decoder 342 occurs. Due to variations in delay time, input port 32
The output from 0 and the output of path driver/receiver 324, which functions as a path controller, may conflict on path 6350. The large current caused by this competition may damage elements within the integrated circuit or cause malfunction due to the generation of noise.

In order to prevent this conflict, a delay circuit 806 is provided to compensate for variations in propagation delay times of circuit elements. Since the BSS decoder 3400 Å cupode address decoding output 352 is activated in clock cycle φC3, the AND gate 802 of the internal conflict prevention circuit 800 is deactivated. At the end of clock period .phi.C3, decoder output 352 goes low/bell, and one input of AND gate 802 is energized via an inverter. After a short delay, the input port 320 is de-energized. In the next cycle φC4 of clock CLK, BDS dehooder 342
When the decoded output 354 identifies the address of its own unit's output port 322, the decoded output 354 goes high. This high level is transmitted to the other input 804 of AND card 802 after a delay time .tau. (FIG. 6) of delay circuit 806. During this period τ, the output 352 of BSS decoder 340 goes completely low. Input port 320 is also completely de-energized, and the output of input port 320 on path 350 is also completely lost. AND by the high level of lead 804
Output 356R of 802 goes high, path driver/receiver 324 operates normally, and data DATA on path 40 is transferred to output port 322.

If the BSS decoder 340 of that unit is driven again at the beginning of the period φC5 following the period φC/I, the decoded output 352 becomes high level, so the AND
- port 802 immediately de-energizes output 356R. This causes the gas driver/remover 324 to stop operating as a receiver.

In addition, the BSSφC4SS-da 340 of that unit is
Even if not driven, at the end of the period the output 1c'-)3
When writing of data to 22 is completed, BDS data: 7-
When the output 354 of the gate 324 goes low, the output 356R of the AND gate 802 is deactivated, and the driver/register 324 ceases to function as a driver. Gustry・gu/Len・gu324
While acting as a path receiver, the output output to the path 350 is connected to the output of the human power 59-) 320 that is next driven at the boundary between the periods φC4 and φC5 and the K on the path 350.
i3 contention is prevented. In this way,
Output conflicts on internal bus 350 when going from reading from input port 320 to writing to output port 322 and vice versa within the same unit are prevented.

In order to avoid complicating the explanation, an example in which one input/output circuit unit 30 is provided with a single input port 320 and a single output port 322 has been described, but it is also possible to provide a plurality of these in one unit. The path contention prevention circuit 344 can also function in the same manner as described above. In that case, the path conflict prevention circuit 344 treats these multiple input/output capacitors 320 and 322 as one group. Therefore, the decoded output 352 of BSS decoder 340
is expanded for each individual input port 320, but the AND+''-) 704 input of the data source contention prevention circuit 700 and the AND+''-) 8020 input of the internal contention prevention circuit have a common value for the group, i.e. The input/output circuit unit) 30 is logically summed and supplied as a single signal.The same applies to the decoded output 354 of the BDS decoder 342, and the decoded output 354 is expanded for each output port 322. However, to the input of the delay circuit 806 of the internal contention prevention circuit 800, the logical sum of the group is taken and the result is supplied as the signal A-.

By configuring the data source conflict prevention circuit according to the present invention in this manner, high-speed data transfer between input and output cover beats in each of consecutive clocks and cycles 1 is realized without conflicting outputs between data sources. can do. Therefore, a certain degree of variation can be tolerated in circuit elements such as the address zero address decoder and data buffer, and circuit elements can be prevented from being destroyed by large currents 6 during output competition or malfunctions due to noise. do not have.

In addition, since data transfer between ports can be completed within one period of one system clock, high-speed arithmetic processing can be performed more effectively if applied to, for example, a bit slice processor. Each of the aforementioned signals, namely CLK, BSS, BDS
.

■If you configure the ALU and LCH to be directly controlled by a microprogram, the calculations in the ALU in the processing unit and the independent data transfer between ports can be completed simultaneously within one clock cycle, achieving high-speed processing. can do.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an example of a processing device to which the data source conflict prevention circuit according to the present invention can be applied, FIG. 2 is a block diagram showing the configuration of the input/output circuit in FIG. 1, and FIG. Figure 2 is a signal waveform diagram showing the operation of the circuit shown in Figure 2. Figure 1 is a block diagram showing a specific configuration example of the path contention prevention circuit shown in Figure 2. Figures 5 and 6 are the circuit shown in Figure 4. FIG. 3 is a signal waveform diagram showing the operation of FIG. Explanation of symbols of main parts 30 - Input/output circuit 40... Data path 320... Human power port 322... Output port 340... BSS decoder 342... BDS decoding 344... Gus conflict Prevention circuit 700...Data source conflict prevention circuit 800...Internal conflict prevention circuit 806...Delay circuit

Claims (1)

[Claims] 1. A plurality of data sources are connected to a common transmission path, and in one cycle of a clock signal, one of the plurality of data sources selected by a processing device is connected to the common transmission path. In a data source conflict prevention circuit that prevents conflicts between multiple data sources in a data transfer method that outputs data and transfers the data to a data sink, the data source conflict prevention circuit includes at least one data source. A first signal provided corresponding to a group of data sources and indicating that the data sources of the group are outputting data on the common transmission path C is connected to the common transmission line for each data source conflict prevention circuit. a signal generation circuit that generates a signal on a first signal path; and a signal detection circuit that detects the presence or absence of the first signal on the first signal path, the signal generation circuit being connected to an output of the signal detection circuit;
When one data source included in a group of data sources corresponding to the data source conflict prevention circuit is selected, the signal detection circuit detects the absence of a first signal associated with a data source of another group. A data source conflict prevention circuit characterized in that, upon detection, outputs data from the selected data source and generates a first signal on a first signal path. 2. In the circuit according to claim 1, the signal detection circuit has one input connected to the first signal path.
The signal generation circuit includes an R gate, one input of which is connected to the output of the OR dart, and the other input of which is connected to a second data source for selecting a group of data sources corresponding to the data source contention prevention circuit.
The data source contention prevention method is characterized in that the output of the signal generation circuit is connected to the first signal path by calculating the logical sum for each data source contention prevention circuit. circuit.