JP2723267B2 - Asynchronous input interface device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial application field) The present invention relates to a video tape recorder (hereinafter referred to as a VTR).
Control unit (microcomputer)
The present invention relates to an asynchronous input interface device effective as an interface for a control signal between a signal processing unit and a function switching unit provided inside the VTR.

(Prior Art) In a video signal processing system such as a home VTR, the operation is controlled by a microcomputer with diversification of functions. In this case, it is preferable that the change of the operation content and the switching of the function be performed in synchronization with the video signal, and it is particularly preferable that the change be performed during the blanking period in which the display screen is not affected.

FIG. 4 shows an interface circuit between the microcomputer and the controlled unit.

The control unit 11 includes control data for controlling the controlled device.
It outputs COND and an address ADD corresponding to the control data COND. The address ADD is supplied to the decoder 121, and the control data COND is supplied to the register unit 13. The register unit 13 has a register group 131 and a register group 132 in order to fetch the control data COND in synchronization with the control unit 11. The register group 131 supplies a decode output from the decoder 12 to the register group 132 as a clock in synchronization with the reception clock of the control unit 11.

Here, the control unit 11 outputs the control data COND in a synchronization relationship unrelated to the synchronization signal of the controlled device (for example, VTR), and positions (registers) where data should be latched during the output period of the control data COND. Is output. Now, assuming that the first address ADD is output and the decode output D1 is obtained from the decoder 12, the output D1 becomes
It is latched at the timing of the received clock in the register R11 of the register group 131, and is supplied as a clock to the register R21 for latching the control data COND. Thus, the control data corresponding to the address AD1 is latched in the register R21.

Next, the control data CON1 stored in the register R21 is
The data is transferred to the register R31 of the register unit 14 that operates by the synchronization signal of the controlled device. As a result, from the output terminal OUT1,
The control data CON1 is output in synchronization with the synchronization signal of the controlled device, and the controlled device is controlled. Here, the address ADD from the control unit 11 corresponds to the control points P1, P2,.
, And the control data COND indicates the control content of each location. When the controlled device is, for example, a VTR, the terminal 15 is supplied with, for example, a vertical synchronization signal. First, the control unit causes the first-stage register group 132 (R21, R22,... R2n) to latch control data in a synchronization state unrelated to the vertical synchronization signal. Next, the control data is simultaneously transferred and output from the register group 132 to the register unit 14 when the vertical synchronization signal arrives.

As described above, when the control unit 11 and the VTR are in an asynchronous state, it is necessary to output control data by a two-stage operation.

However, according to this method, if the transfer is performed to the second-stage register unit in a state where all necessary control data is not received in the first-stage register unit, the control of the VTR is different from the intended control. There is a problem of being controlled by the state.

On the other hand, a method is also conceivable in which a vertical synchronizing signal is supplied to the control unit 11 (microcomputer) as an interrupt signal, and control data is reliably transferred during this interrupt period. In this case, only one register is required. However, in this method, the control unit 11 controls the VTR synchronization signal period to
In this period, the control unit 11 cannot perform other processing, so that efficiency is reduced. Also, the program becomes complicated.

(Problems to be Solved by the Invention) As described above, according to the conventional interface circuit, there is a problem that when the control data is transferred by interrupting the control unit, the processing efficiency of the control unit is reduced. Further, if a register unit having a two-stage configuration capable of transferring control data even when the control unit and the VTR are asynchronous is used,
Before all data transfer of the control data to the register unit of the second stage is not completed, the control data is output to the register unit of the second stage by the vertical synchronization signal, and there is a high risk of error control.

Accordingly, the present invention provides a highly reliable asynchronous input by providing a check function for reliably transferring control data even when the control unit and the controlled unit are asynchronous, and for monitoring the progress of control data transfer. It is an object to provide an interface device.

[Means for Solving the Problems] The present invention relates to a plurality of addresses sequentially stored within a fixed address period and control data corresponding to each address irrespective of the cycle of a video signal. A decoder that decodes an address from the controller and obtains a decoded output at a position corresponding to the content of each address; and a decoder that synchronizes with a synchronization signal of a blanking period of the video signal. Release means for canceling the passage of the decode output at each position, a decode output supplied from the release means, and an address period start detection means for detecting the decode output of the first address in the address period; Only when the detection means is outputting the period start detection signal, there is a decode output of the last address in the predetermined period. An address period end detecting means for controlling the canceling means to prohibit the passage of the decode output by detection, and each decode output from the canceling means is supplied, and each decode output is supplied, and this is used as a clock. First latch means for latching the control data corresponding to each decode output, and only when the address period end detecting means is outputting a period end detection signal, in synchronization with the synchronization signal of the next blanking period. Second latch means for latching output data of the first latch means.

(Operation) When control data is output from the control unit by the above means, the start and end of the data output period are detected using the address content as a medium. Thereby, the reception is automatically started from the beginning of the control data output period, and the data reception is stopped at the end of the control data output period. In this period, even if the vertical synchronizing signal is input, the transfer to the output register is not performed, but is performed after the last address is detected. For this reason, even if the control unit and the controlled unit are asynchronous, a control data reception error does not occur.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows an embodiment of the present invention. The address ADD from the control unit 21 indicates the control location of the non-control device and is supplied to the decoder 22, and the control data COND is supplied to the latch circuit 24. The decoder 22 decodes the address content and obtains a decoded output at a location corresponding to the address. This decoded output is supplied to a latch circuit via a gate circuit 23 which passes the decoded output under the conditions described later.
24 is supplied as a clock (latch pulse). The latch circuit 24 is driven by the decode output and latches control data from the control unit 21. Therefore, the address ADD is associated with the control data COND, and the address indicates the control location of the controlled device, and the control data indicates the control content. The contents of the latch circuit 24 are simultaneously supplied to each controlled unit via the latch circuit 25. The output timing of the control data is, for example, a VTR blanking period.

The period until the control data of the latch circuit 24 is stored and the timing at which the control data is output from the latch circuit 25 are asynchronous. Asynchronous like this,
Data acquisition and transfer errors do not occur because the following configuration is further provided.

That is, when the synchronization signal (vertical synchronization signal) is input to the input terminal 26, the release circuit 27 controls the gate circuit 23 so that the decoded output can pass. Next, when outputting the address, the control unit 21 sequentially outputs the address in a predetermined address period so as to designate all the control locations of the controlled device. In response to the address output, control data at the designated position is also output. Therefore, if the address output period of the control unit 21 exists during the vertical blanking period, the decode output is output from the gate circuit.
The signal is supplied to the latch circuit 24 through the switch 23. Here, the output order of each address corresponding to each control point of the controlled device is determined in advance. The first address in the address output period is detected by the address period start detection circuit 28. When the address period start detection circuit 28 detects the start of the address period, the address period end detection circuit 29 is also enabled. The address period end detection circuit 29
This circuit detects whether or not the last address (the last address in the address period) obtained from the gate circuit 23 has been decoded. When the end of the address period is detected by the address period end detection circuit 29, the output thereof inhibits the gate circuit 23 from passing the decode output. Further, when the end of the address period is detected by the address period end detection circuit 29, the latch pulse generation circuit 30 is enabled. The latch pulse generating circuit 30 is enabled only when the previous address period start detecting circuit 28 detects the start of the address period and the address period end detecting circuit 29 detects the end of the address period. When a vertical synchronizing signal is input from the controller, a latch pulse is generated. The latch pulse is supplied to the latch circuit 25, whereby all of the control data stored in the latch circuit 24 is simultaneously output and supplied to each control point of the controlled device.

According to the above configuration, when the first vertical synchronizing signal of the video signal is input, the gate circuit 23 is released, a clock (decode output) is input to the latch circuit 24, and control data can be captured. The stored control data is control data output from the start to the end of the address period in any case. When the release circuit 27 releases the gate circuit 23, the address period end detection circuit 29 detects the start of the address period even if the third address in the address period is sent out and is not the first address. The control data at this time is not transferred from the latch circuit 24 to the latch circuit 25. Data held after the address is detected by the address period start detection circuit 28 is used. Moreover, the control data at this time is used only when the address is decoded continuously from the beginning to the end.

With the above-described device, the control data output from the control unit 21 is stably taken in even if the control unit 21 is completely asynchronous with the controlled device.

FIG. 2 is a circuit that further embodies the block of FIG. 1, and FIG. 3 is a signal waveform of each part of the circuit of FIG.
The same reference numerals as those given to the respective signal waveforms are attached to FIG. 2 to indicate locations where the corresponding waveforms can be obtained.

In an actual circuit, the release circuit 27, the address period start detection circuit 28, the address period end detection circuit 29, etc.
As shown in the figure, the pulse generator 31, the flip-flop FF
1, NAND circuit NAND, flip-flop FF2, NOR circuit NOR
Etc. The pulse generating circuit 31 uses the system clock (K), the vertical blanking pulse (b), and the horizontal blanking (a) to generate timing pulses (c),
(D), (e) and (f) are generated. The flip-flop FF1 is reset by the timing pulse (d), and thereby enters a state of waiting for an address start detection. Also,
The gate control signal (g) for controlling the gate circuit 23 is controlled such that the timing pulse (c) is supplied to the NOR circuit NOR so that the gate circuit 23 can pass the decode output from the decoder 22. . The gate circuit 23 includes AND circuits AND1 to AND1 corresponding to the respective outputs of the addresses AD to AD11.
1 and transfer units TR1 to TR11 that transfer the outputs of the AND circuits AND1 to AND11 in synchronization with the system clock.

Assuming that there is a decode output corresponding to the address AD1, the transfer unit TR1 transfers the decode output to the register R1 of the latch circuit 24 as a clock, and supplies the address period start detection signal (1) to the flip-flop FF1. . As a result, the flip-flop FF1 is set, and the NAND circuit NAD enters a standby state for detecting the last address (the last address in the address period).
When addresses are sequentially transmitted (in this embodiment, it is assumed that there are 11 control items) and there is a decode output of the last address, an output is obtained from the AND circuit AND11, and the transfer unit TR11 The decoded output is latched by a latch circuit 24.
As a clock for the register R11. At the same time, an address period end detection signal (m) is obtained, and this is
Supply to NAND. As a result, the flip-flop FF2 is set, the gate control signal (g) is inverted by the output (r), and the signal passage in the gate circuit 23 is inhibited.

In this state, when the next timing pulse (f) is obtained, since the signal (r) is at the high level, the latch pulse generation circuit 30 is driven by the system clock (k) and outputs the latch pulse (s). ) Can occur. Therefore, during the address period, the register R1 of the latch circuit 24 is
~ R11 are stored in the latch circuit 2
5 is transferred to the registers R01 to R011. FIG. 3 shows a state (o) in which the control data (n) is latched by the latch circuit 24 and a state (t) in which the control data (n) is transferred to the latch circuit 25 and output.

In the above embodiment, the controlled device has been described as a VTR. However, the present invention is not limited to this, and it goes without saying that the device can be applied to any device that handles video signals.

[Effects of the Invention] As described above, according to the present invention, even if the control unit and the controlled unit are asynchronous, the transfer of the control data is reliably performed, and the progress of the transfer of the control data is monitored. By having the check function, a highly reliable operation can be obtained without mistake in taking in control data.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram showing the block of FIG. 1 more specifically, and FIG.
FIG. 4 is a signal waveform diagram of each part shown for explaining the operation of the circuit of FIG. 2, and FIG. 4 is a diagram showing a conventional interface circuit. 21 ... Control unit, 22 ... Decoder, 23 ... Gate circuit, 2
4, 25 latch circuit, 27 release circuit, 28 address period start detection circuit, 29 address period end detection circuit,
30 Latch pulse generation circuit.

Claims (1)

(57) [Claims] 1. A control unit for outputting a plurality of types of addresses sequentially stored within a fixed address period regardless of a cycle of a video signal, a control unit for outputting control data corresponding to each address, and an address from the control unit. And decoding to obtain a decoded output at a position corresponding to the contents of each address, in synchronization with the synchronization signal of the blanking period of the video signal, and canceling the passage of the decoded output at each position due to the decoding Means, a decode output from the canceling means, an address period start detecting means for detecting a decode output of a first address in the address period, and the address period start detecting means outputting a period start detection signal. Only when is the case, the release means is controlled by detecting that there is a decode output of the last address in the certain period. Address period end detecting means for prohibiting passage of the decode output, and first decode means supplied with each decode output from the canceling means, and using the clock as a clock to latch the control data corresponding to each decode output. A second latch unit that latches output data of the first latch unit in synchronization with a synchronization signal of a next blanking period only when the address period end detection unit is outputting a period end detection signal; An asynchronous input interface device comprising: