JP3354488B2 - Serial data transfer device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a serial data transfer device for serially transferring data in synchronization with a clock. In particular, when the same instruction is applied to a plurality of controlled circuits at the same time, transfer timings are equal. And a serial data transfer device.

[0002]

2. Description of the Related Art In some cases, a TV receiver or a home VTR has a plurality of ICs inside, and the plurality of ICs are controlled by a single controller (microcomputer). There are serial and parallel control methods, but the serial method is often used because the number of lines is small. In the serial method, a start signal, a slave address signal, transfer data, a stop signal, and the like are created by using a combination of logical values of “H” and “L” of data and a clock, and one cycle includes the plurality of signals. To use repetitive signals. Various information is added to the transfer data. FIG. 2 shows data and a clock of such a serial data transfer device of the serial system. FIG. 2A shows the data in FIG.
(B) shows a clock. Time t1 indicates a start point, and time t2 indicates a stop point. During this time, necessary transfer data exists.

[0003] A start point is when data changes from "H" to "L" when the clock is "H". The stop point is when the data is "L" when the clock is "H".
It is time to change from "H" to "H". Then, by reading the value of the data at the falling edge of the clock (for example, t3), the data is taken in.

When one transfer data ends, a stop signal is generated to notify the end of the data transfer. Then, when the next start signal arrives, the next transfer data is sent.

[0005]

However, the serial method has a problem that it takes a long time to send an instruction to a plurality of ICs at the same time because the instruction is serial.

For example, in a home VTR, it is necessary to simultaneously switch a plurality of ICs (for example, a main YC signal processing IC, a head amplifier IC, and an OSD IC) to a reproduction mode or a recording mode. In this case, if the mode change information is transmitted serially, there is a problem that a plurality of ICs cannot be operated at the same time.

At present, the mode is formally switched after the mode switching is completed in all ICs.

[0008]

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and is directed to a serial data transfer device for serially transferring data, comprising: an input terminal to which serial data is applied; A first memory for temporarily storing serial data from the first memory, a first memory for storing data from the first temporary memory, and a second memory for temporarily storing serial data from the input terminal. And a second memory for storing data from the second temporary memory, and a first memory for generating a first control signal indicating that serial data from the input terminal is being transferred.
A transfer state detection circuit, a second transfer state detection circuit that generates a second control signal indicating that serial data from the input terminal is being transferred, and the first and second transfer states when a transfer command arrives. It is determined that the second control signal has not arrived, and the data from the first temporary memory is stored in the first temporary memory.
And a control circuit for transferring the data from the second temporary memory to the second memory and transferring the data to the first memory and the second memory in response to the transfer command. Is transferred.

Further, the present invention has been made in view of the above points, and is a serial data transfer device for serially transferring data, comprising: an input terminal to which serial data is applied; A first temporary memory for temporarily storing data, a first memory for storing data from the first temporary memory, and a second temporary memory for temporarily storing serial data from the input terminal. A second memory for storing data from the second temporary memory, a first control signal indicating that serial data from the input terminal is being transferred, and a fact that the transfer of the serial data has been completed. A first transfer state detecting circuit for generating a second control signal indicating that the serial data is being transferred from the input terminal; a third control signal indicating that serial data from the input terminal is being transferred; A second transfer state detecting circuit for transfer to generate a fourth control signal indicating the end,
When the transfer command arrives, it is determined that the first and third control signals have not arrived, the data from the first temporary memory is transferred to the first memory, and the second temporary signal is transmitted. A control circuit for transferring data from a memory to the second memory, wherein data is simultaneously transferred to the first memory and the second memory in response to the transfer command. I do.

[0010]

FIG. 1 shows a serial data transfer apparatus according to the present invention, wherein 1 is an input terminal to which serial data is applied, and 2 is a memory for temporarily storing serial data from the input terminal 1. A first temporary memory 3 for storing data from the first temporary memory 2; a second temporary memory 4 for temporarily storing serial data from the input terminal 1; Is a second memory for storing data from the second temporary memory 4, and 6 is a first control signal A1 indicating that serial data from the input terminal 1 is being transferred, and a transfer of the serial data. A first transfer state detection circuit for generating a second control signal B1 indicating that the serial data from the input terminal 1 is being transferred, and a third control signal A2 indicating that serial data from the input terminal 1 is being transferred.
A second transfer state detection circuit for generating a fourth control signal B2 indicating that the transfer of the serial data has been completed;
Determines that the first and third control signals A1 and A2 have not arrived when the transfer command from the terminal 9 has arrived, and stores the data from the first temporary memory 2 into the first memory. The control circuit 10 transfers the data from the second temporary memory 4 to the second memory 5 and opens and closes in response to the output signal of the control circuit 8 e4e9.
A switch 11 is a switch that opens and closes in accordance with an output signal of the control circuit 8, a luminance signal processing block 12 is used for recording / reproducing a video signal of a home VTR, and a recording / reproducing process 13 is a video signal of a home VTR. This is a chroma signal processing block used for.

In the apparatus shown in FIG. 1, the control start timings of the luminance signal processing block and the chroma signal processing block of the home VTR are simultaneously set in accordance with the serial data. For example, when changing from the recording mode to the reproduction mode, it is necessary to transfer the information whose mode has been switched and the information (image quality adjustment information) accompanying the information. The serial data in that case has a form as shown in FIG.

That is, the data D2 includes chroma information (information on switching modes and image quality adjustment information), and the data D1 includes luminance information (information on switching modes and image quality adjustment information).

The serial data shown in FIG. 3A is applied to the input terminal 1 shown in FIG. The serial data is serially stored in the first temporary memory 2 and the second temporary memory 4. The serial data is transmitted to the first transfer state detecting circuit 6.
Is applied to the second transfer state detection circuit 7. The first transfer state detection circuit 6 decodes the serial data and outputs a pulse A1 indicating that the data D1 is being transferred (FIG. 3B).
To the first temporary memory 2. Then, the first temporary memory 2 starts storing the serial data from the input terminal 1.

The first transfer state detecting circuit 6 decodes the serial data and applies a pulse B1 indicating that the data transfer is completed to the first temporary memory 2. Then, the first temporary memory 2 stops storing the serial data from the input terminal 1.

The second transfer state detecting circuit 7 performs the same operation, and applies the pulse A2 shown in FIG. 3 (c) to the second temporary memory 4. Then, the second temporary memory 4 stores the input terminal 1
To start storing the serial data from. Further, the second transfer state detection circuit 7 decodes the serial data and applies a pulse B2 indicating that the data transfer is completed to the second temporary memory 4. Then, the second temporary memory 4 stops the operation of storing the serial data from the input terminal 1.

The first transfer state detection circuit 6 and the second transfer state detection circuit 7 decode incoming serial data and can determine to which block the contents are transferred. Therefore, when data D1 arrives,
The first temporary memory 2 operates so that the data is transmitted to the luminance signal processing block 12, and when the data D2 arrives, the second temporary memory 4 is operated so that the data is transmitted to the chroma signal processing block 13. It is supposed to work.

In this way, the data D1 and D2 transferred serially are stored in the first temporary memory 2 and the second temporary memory 2.
Is temporarily stored in the temporary memory 4.

It is assumed that a transfer command arrives at the terminal 9 from this state. This transfer command is for transferring data from the temporary memory to the original memory (the first memory 3 and the like).

This transfer instruction is composed of data D1 and data D
2 is asynchronous in timing. Therefore, a transfer command is issued while the serially transferred data D1 and data D2 are being written to the first temporary memory 2 and the second temporary memory 4.

First temporary memory 2 and second temporary memory 4
If data is transferred while data is being written to the data, data information will be lost.

Therefore, in the present invention, when a transfer command is received by the control circuit 8, it is confirmed that the data transfer period is not in progress, and then the transfer is performed from the temporary memory to the original memory (for example, the first memory 3). are doing.

More specifically, the transfer command shown in FIG. 3F is applied to the control circuit 8, and the transfer command shown in FIG.
The pulse of (h) is created. During the "H" level period of the pulse of FIG. 3H, the pulse A1 of FIG.
Is at the “H” level.

FIG. 4 shows a specific example of the control circuit 8 shown in FIG. The transfer pulse of FIG. 3F is applied to the terminal 20 of FIG. The system control circuit 21 generates a control pulse shown in FIG. 3 (h) and a detection pulse shown in FIG. 3 (g) according to the transfer pulse. This detection pulse is transmitted or cut off when the switch 22 opens and closes. When the detection pulse is transmitted, the memory contents are transferred.

It is a latch determination circuit 23 that switches the opening and closing of the switch 22. The latch discriminating circuit 23 operates during the period in which the control pulse of FIG.
It is determined whether the pulse A1 in (b) and the pulse A2 in FIG. 3C are at the “H” level or the “L” level.

Now, assuming that the pulse of FIG. 3 (h) is in the “H” level period T1, the pulse A1 in that period is “H”.
Cannot transfer because it is level. Therefore, a control signal for opening the switch 22 is generated from the latch determination circuit 23. Then, the detection pulse is not transmitted.

For this reason, the switches 10 and 11 are opened as shown in accordance with a control signal from the control circuit 8. If the switches 10 and 11 are open as shown, there is no transfer from the temporary memory to the original memory (for example, the first memory 3).

Next, when a transfer command at the next timing of FIG. 3F is applied to the control circuit 8, the pulse (period T2) of FIG. The detection pulse of (g) is created. In the "H" level period of the pulse (period T2) in FIG.
The pulse A1 in FIG. 3B and the pulse A2 in FIG.
It detects whether it is a level or not.

In this case, since both the pulse A1 in FIG. 3B and the pulse A2 in FIG. 3C are at the "L" level, it is clear that the transfer is not in progress. Therefore, the switch 22 is closed by the latch determination circuit 23, and the control signal of FIG. 3 (i) is generated from the control circuit 8, and the switches 10 and 11 are closed according to the control signal. Switch 10,
When 11 is closed, the storage data is transferred from the temporary memory to the original memory (for example, the first memory 3).

Therefore, the first memory 3 and the second memory 5
, The data is transferred at the same time, and the data can be simultaneously transmitted to the luminance signal processing block 12 and the chroma signal processing block 13.

[0030]

As described above, according to the present invention, when the same instruction is simultaneously applied to a plurality of controlled circuits, the transfer timings can be made equal.

In particular, according to the present invention, during the data transfer to the temporary memory, the data is not transferred to the original memory, so that the data can be transferred reliably.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a serial data transfer device of the present invention.

FIG. 2 is a waveform diagram for explaining a conventional serial data transfer.

FIG. 3 is a waveform chart for explaining serial data transfer according to the present invention;

FIG. 4 is a specific circuit diagram of a control circuit 8 of the present invention.

[Explanation of symbols]

 (1) Input terminal (2) First temporary memory (3) First memory (4) Second temporary memory (5) Second memory (6) First transfer state detection circuit (7) Second Transfer state detection circuit (8) Control circuit

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04L 13/08 G06F 13/38 350

Claims (3)

(57) [Claims] 1. A serial data transfer device for serially transferring data, comprising: an input terminal to which serial data is applied; a first temporary memory for temporarily storing serial data from the input terminal; A first memory for storing data from a first temporary memory; a second temporary memory for temporarily storing serial data from the input terminal; and a second memory for storing data from the second temporary memory. 2, a first transfer state detection circuit that generates a first control signal indicating that serial data from the input terminal is being transferred, and that the serial data from the input terminal is being transferred. A second transfer state detection circuit for generating a second control signal indicating that the first and second control signals have not arrived when a transfer command has arrived; A control circuit for transferring data from a temporary memory to the first memory and transferring data from the second temporary memory to the second memory, wherein the first memory is responsive to the transfer command. And data are simultaneously transferred to the second memory. 2. A serial data transfer device for serially transferring data, comprising: an input terminal to which serial data is applied; a first temporary memory for temporarily storing serial data from the input terminal; A first memory for storing data from a first temporary memory; a second temporary memory for temporarily storing serial data from the input terminal; and a second memory for storing data from the second temporary memory. A first control signal indicating that serial data from the input terminal is being transferred, and a second control signal indicating that the transfer of the serial data has been completed.
A transfer state detection circuit, a third control signal indicating that serial data from the input terminal is being transferred, and a fourth control signal indicating that the transfer of the serial data has been completed. 2
A transfer state detecting circuit for determining that the first and third control signals have not arrived when a transfer instruction has arrived, and transferring data from the first temporary memory to the first memory. And a control circuit for transferring data from the second temporary memory to the second memory, wherein data is simultaneously transferred to the first memory and the second memory in response to the transfer command A serial data transfer device characterized in that: 3. A serial data transfer device for serially transferring data, comprising: an input terminal to which serial data is applied; a first temporary memory for temporarily storing serial data from the input terminal; A first memory for storing data from a first temporary memory; a second temporary memory for temporarily storing serial data from the input terminal; and a second memory for storing data from the second temporary memory. 2, a first transfer state detection circuit that generates a first control signal indicating that serial data from the input terminal is being transferred, and that the serial data from the input terminal is being transferred. A second transfer state detection circuit for generating a second control signal indicating a transfer command, generating a control pulse in response to a change in state of a transfer pulse indicating a transfer command, and A system control circuit for generating a detection pulse whose generation timing is delayed from the control pulse in accordance with a state change; and wherein the first and second control signals arrive during the generation of the control pulse from the system control circuit. A latch discrimination circuit for discriminating that the detection pulse has not been transmitted, and a switch for passing or blocking the detection pulse according to a discrimination output signal of the latch discrimination circuit.
Transfer the data from the temporary memory to the first memory and transfer the data from the second temporary memory to the second memory, and transfer the first memory and the second memory in response to the transfer pulse. A serial data transfer device, wherein data is simultaneously transferred to a memory.