JP2001210026A - Reproducing device and method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To precisely detect the synchronizing data. SOLUTION: A reproducing device is constituted of a reproducing means reproducing a data line consisting of plural synchronous blocks respectively having the synchronizing data and the ID data, a synchronous detection means detecting the synchronizing data from the reproducing data line, an ID detection means detecting the ID data from the reproducing data line and a control means using the detection result of the ID detection means controlling the detective operation of the synchronous detection means.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reproducing apparatus and a reproducing method, and more particularly to detection of synchronous data in a reproduced data sequence.

[0002]

2. Description of the Related Art As this kind of apparatus, a digital VTR for recording and reproducing image signals and audio signals as digital signals on a magnetic tape has been known.

In a digital VTR, a sync block composed of a predetermined amount of data is usually generated, and recording and reproduction are performed in units of the sync block. That is, at the time of recording, sync data and ID data having a fixed pattern are added to a predetermined amount of image data and audio data, and a parity for error correction at the time of reproduction is added to form a sync block. Then, recording is performed on a large number of tracks formed on the magnetic tape.

At the time of reproduction, sync data is detected from the reproduced data, ID data is detected based on the detected sync data, and image data and audio data are reproduced.

Thus, in a digital VTR,
In order to accurately reproduce image data and audio data, it is important to accurately detect sync data.

However, in a transmission path of a digital VTR or the like, a data pattern similar to the sync data may occur in data other than the original sync data due to mixing of noise and the like. This is called a pseudo sync.
If this pseudo sync is erroneously detected as true sync data, the subsequent image data and audio data cannot be correctly reproduced.

As a countermeasure, there has been proposed a method of masking the detection result of the sync data except for a period in which it is predicted that the sync data will be obtained.

On the other hand, since ID data is often used as an address when writing reproduction data to a memory, it is important to accurately detect ID data.

Conventionally, in order to accurately detect ID data, for example, an ID predicted from previously detected ID data is compared with newly detected ID data. It is also considered to write data into a memory.

[0010]

In the method of masking the sync data detection result as described above, generally, when the sync data is no longer detected, the mask is released and the sync data is detected in an open state. Therefore, if a pseudo sync is detected in a mask open state, a mask is applied at that time, and it takes a long time to detect real sync data again.

When the opening / closing of the mask is controlled based only on the detection result of the sync data as described above, a correct result is obtained as a result of the comparison of the ID data as described above. However, even if the data is written to the memory, if the sync data cannot be detected, the mask is opened and a pseudo sync is detected, so that good reproduction data may not be written to the memory.

An object of the present invention is to solve the above-mentioned problems.

Another object of the present invention is to enable a synchronous signal to be accurately detected.

[0014]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems and achieve the above object, the present invention provides a reproducing means for reproducing a data string comprising a plurality of synchronous blocks each having synchronous data and ID data. Synchronization detection means for detecting the synchronization data from the reproduction data string; ID detection means for detecting the ID data from the reproduction data string; and detection of the synchronization detection means using the detection result of the ID detection means. And control means for controlling the operation.

[0015]

Embodiments of the present invention will be described below in detail with reference to the drawings. In the embodiment described below, a case where the present invention is applied to a well-known digital VTR will be described.

FIG. 1 is a diagram showing a configuration of a reproduction system of a VTR 100 to which the present invention is applied.

In FIG. 1, a rotary head 103 traces a large number of tracks on a tape 101 alternately by two head elements, reproduces information recorded on the tape 101, and outputs the information to a reproducing circuit 105. The reproduction circuit 105 processes the output of the head 103 using an amplifier and an equalizer,
Further, digital data is detected from the reproduced signal and output to the synchronization detection circuit 107, the ID detection circuit 113, and the memory 127.

Reference numeral 135 denotes a PG head which generates a PG signal indicating a rotation phase in accordance with the rotation of the rotary head 103 and outputs it to the SWP generation circuit 135. The SWP generation circuit 137 generates a head switch pulse for switching between the two head elements of the head 103 according to the PG signal, and outputs it to the reproduction circuit 105 and the edge detection circuit 139.

The reproducing circuit 105 alternately switches the two head elements based on the head switch pulse and receives an output. Further, the edge detection circuit 139 detects a rising edge and a falling edge of the head switch pulse, and outputs a detection pulse to the mask control circuit 109 and the counter 111.

Here, the configuration of the sync block of the reproduction data in the present embodiment will be described.

FIG. 2 shows the structure of one sync block. One sync block includes sync data 201 (2 bytes), ID 203 (2 bytes), ID parity 205 (1 byte) for detecting an ID error, data 207 (77 bytes) such as audio and image, and data parity. It is composed of 209 (8 bytes) 85-byte data.

The synchronization detecting circuit 107 extracts the sync data 20 shown in FIG. 2 from the reproduced data sequence output from the reproducing circuit.
1 and the mask control circuit 109 and the counter 111
Output a detection pulse.

FIG. 3 is a diagram showing a configuration of the synchronization detection circuit 107.

A reproduction data string from the reproduction circuit 105 is input from the input terminal 301 to the comparison circuit 303. Memory 3
Reference numeral 05 stores a 2-byte sync pattern. The comparison circuit 303 compares the input reproduced data sequence with the sync pattern from the memory 305, and outputs a detection pulse to the mask circuit 307 when they match.

The mask circuit 307 operates in accordance with a mask control signal from the mask control circuit 109 as will be described later.
3 is masked, and only the detection pulse output in the mask open state is output from the output terminal 309.

The counter 111 is a block counter for counting the number of blocks in each track, a symbol counter for counting the number of data in each block, and a timing signal generating circuit for generating various timing signals based on the count value of each counter. Consists of The block counter is reset by an edge pulse from the edge detection circuit 139, and counts a detection pulse from the synchronization detection circuit 107. The symbol counter is reset by an output pulse from the synchronization detection circuit 107, and counts a clock having a frequency corresponding to the reproduced data.

The ID detection circuit 113 extracts ID data and IDP data from the reproduced data sequence based on the count value of the symbol counter of the counter 111, outputs the ID data to the switch 117 and the comparison circuit 123, and outputs
The D data and the IDP data are output to the IDP operation circuit 115.

The IDP calculation circuit 115 performs a predetermined calculation process using the ID data and the IDP data output from the ID detection circuit, checks whether there is an error in the ID data and the IDP data, and checks the check result. The output binary signal is output to the mask control circuit 109, the switch 117, the state machine 125, and the switch 133.

The switch 117 is connected according to the inspection result from the IDP operation circuit 115 when there is no error as a result of the inspection and outputs the ID data from the ID detection circuit 113 to the register. Is open. On the other hand, the switch 133 is connected to the IDP operation circuit 115.
Thus, when an output with an error is obtained, the connection state is established and the prediction ID data from the arithmetic circuit 121 is output to the register 119, and when there is no error, the connection state is open.

The register 119 stores the ID data output from the switch 117 or the switch 133.
The arithmetic circuit 121 adds 1 to the value of the ID data stored in the register 119, generates predicted ID data having the ID data value of the sync block predicted to be detected next, 133.

As described above, the switch 117 and the switch 1
When the IDP operation circuit 115 obtains an error-free inspection result, the ID data newly detected by the ID detection circuit 113 is output to the register 119, and an error-inspection result is obtained. In this case, the prediction ID data obtained by the arithmetic circuit 121 is output to the register 119.

The comparison circuit 123 compares the ID data newly obtained by the ID detection circuit 113 with the predicted ID data, and outputs binary data indicating the comparison result to the state machine 125. As described above, in the present embodiment, the continuity of the ID data is confirmed by the comparison circuit 123.

The state machine 125 includes a microprocessor, a register, and the like.
Based on the inspection result of the above and the comparison result of the comparison circuit 123, the mask processing by the mask control circuit 109 and the operation of writing the reproduced data to the memory 127 are controlled.

The signal processing circuit 129 subjects the image data and audio data read from the memory 127 to error correction decoding processing using parity data, decoding processing corresponding to recording, and the like. Output.

The mask control circuit 109 includes the synchronization detection circuit 10
7, the mask processing by the synchronization detection circuit 107 is controlled based on the detection pulse from the IDP 7, the error check result from the IDP operation circuit 115, and the control signal from the state machine 125.

Next, the operation of the state machine 125 will be described.

FIG. 4 is a state transition diagram for explaining the operation of the state machine 125.

In FIG. 4, the test result of the IDP operation circuit 115 is idG when there is no error, and idNG when there is an error. Also, the comparison circuit 1
CmpG when the result of comparison by No. 23 matches, and cmpNG when the result does not match.

In the case of idNG, there is an error in the reproduced ID data, and the comparison circuit 123 cannot perform the comparison operation.
idNG, idG and cmpG, idG and cmpNG
It becomes three. A timing signal is output from the block counter of the counter 111 to the state machine 125, and the state transition is permitted once for each sync block.

In FIG. 4, the state machine 125 is reset by an edge pulse from the edge detection circuit 139, and enters the idle state 401.

Here, when idG is detected at the timing when the state transition is permitted, the state transitions to the wait1 state 403. In the wait1 state 403, id immediately before
The ID data that has been G is stored in the register 119.

When the state transition is permitted next in the wait1 state 403, if idG and cmpG are satisfied,
Since the continuity of the ID data is confirmed, the state transitions to the lock1 state 409. On the other hand, in the case of idNG, since no new ID data is obtained, the comparison operation is not performed, the switch 117 is opened, and the predicted ID data from the arithmetic circuit 121 is output to the register 119 by the switch 133. Then, the state transits to the wait2 state 405.

At the timing when the state transition is permitted in the wait2 state 405, if idG and cmpG, the continuity of the ID data is confirmed, so that the state transitions to the lock1 state 409. On the other hand, in the case of idNG, since no new ID data is obtained, the comparison operation is not performed, the switch 117 is opened, and the switch 133 outputs the predicted ID data from the arithmetic circuit 121 to the register 119. Then, the state transits to the wait3 state 407.

In the wait3 state 407, at the timing when the state transition is permitted, if idG and cmpG, the continuity of the ID data is confirmed, and the state transitions to the lock1 state 409. On the other hand, in the case of idNG, idG cannot be obtained three consecutive times, and the ID correctly detected earlier is used.
Since the data interval between the data and the newly detected ID data becomes longer, and even if the comparison result between the predicted ID data and the newly detected ID data coincides with each other, the reliability is lowered. The state transits to the idle state 401 and waits for a new idG.

At the timing when the state transition is permitted in the lock1 state 409, if idG and cmpG, the continuity of the ID data has been confirmed, so the lock1 state 409 is held as it is. On the other hand, if idNG, no comparison operation is performed because no new ID data is obtained, and the switch 117 selects the predicted ID data from the arithmetic circuit 121 and outputs it to the register 119. Then, the state transits to the lock2 state 411.

At the timing when the state transition is permitted in the lock2 state 411, if idG and cmpG, the continuity of the ID data is confirmed, so that the state transitions to the lock1 state 409. On the other hand, in the case of idNG, since no new ID data is obtained, the comparison operation is not performed, and the switch 117 selects the predicted ID data from the arithmetic circuit 121 and outputs it to the register 119. And lock3
Transition to the state 413 is made.

At the timing when the state transition is permitted in the lock3 state 413, if idG and cmpG, the continuity of the ID data has been confirmed, so that the state transitions to the lock1 state 409. On the other hand, in the case of idNG, w
As in the ait3 state 407, idG cannot be obtained three consecutive times, and the data interval between the ID data detected correctly first and the newly detected ID data becomes long. Even if the comparison result with the detected ID data matches, the reliability is lowered. Therefore, the state transits to the idle state 401 again, and a new idG
Wait for.

Also, wait1, wait2, wait
In each of the states 3, 3, lock1, lock2, and lock3, at the timing when the state transition is permitted, idG and c
In the case of mpNG, the IDP inspection result indicates that there is no error in the ID data, but the ID data is discontinuous, and the state transitions to the wait1 state 403 and the ID data is newly detected. Control is performed to confirm continuity.

Of the above states, the lock1 state 40
9, each of the lock2 state 411 and the lock3 state 413 is a capture state in which the continuity of the ID data is confirmed, and the state machine 125 sets the lock1 state 40.
9, generates a binary signal that goes to a high level in any one of the lock2 state 411 and the lock3 state 413, and outputs it to the mask control circuit 109 and the memory 127.

The memory 127 also outputs ID data from the ID detection circuit 113 together with the control signal from the state machine 125, and responds to the ID data supplied when the control signal from the state machine 125 indicates the capture state. The reproduction data is stored at the specified address. Further, when the state is other than the capturing state, the storage of the reproduction data is prohibited.

Next, the operation of the mask control circuit 109 will be described.

FIG. 5 is a block diagram showing the configuration of the mask control circuit 109.

A detection pulse from the synchronization detection circuit 107 is input to the input terminal 501, delayed by the delay circuit 503, and output to the AND circuit 505. The inspection result from the IDP operation circuit 115 is input to the input terminal 507, and is input to the AND circuit 505.

The delay circuit 503 delays the synchronization detection pulse from the input terminal 501 by a period (3 bytes) until the IDP calculation by the IDP calculation circuit 115 is completed, and outputs it to the AND circuit 505. Accordingly, from the AND circuit 505, the sync data is detected by the synchronization detecting circuit 107, and the IDP operation circuit 1 following the sync data is detected.
A binary signal which becomes high level when the inspection result by No. 15 is free from error is output.

The counter 509 has 1 for one sync block.
A timing pulse is output from the time counter 111. When the timing pulse is input, the counter 509 loads a predetermined value n (n is an integer of 1 or more) when the output signal from the AND circuit 505 is at a high level. If the output of the AND circuit 505 is at the low level when the timing pulse is input, the count is decreased by one. Therefore, sync data cannot be detected continuously for n sync blocks, or
When the IDP calculation result indicates an error, the counter 5
The count value of 09 becomes 0.

The counter 509 generates a binary signal having a low level when the count value of the counter 509 is 0 and a high level when the count value is any other value, and outputs the signal to the OR circuit 511.

The input terminal 513 receives a binary signal (hereinafter, “lock signal”) indicating the capture state from the state machine 125, and the OR circuit 511 outputs a logic signal between the output of the counter 509 and the lock signal from the input terminal 513. The sum is obtained and output to the AND circuit 515.

As described above, when the value of the counter 509 becomes 0, that is, when no sync data is detected continuously for n sync blocks or when the IDP inspection result indicates an error, the lock signal is output. Is low level, that is, I
OR circuit 511 when continuity of D data cannot be confirmed
Becomes low level.

The input terminal 517 has a counter 111
Are input. The arithmetic circuit 519 performs an arithmetic operation by using the count value, and generates a binary signal that is at a low level for a few byte periods near the input of the sync data and is at a high level during the other periods. Output. AND circuit 51
Reference numeral 5 denotes a logical product of the output of the OR circuit 511 and the output of the arithmetic circuit 519, and the synchronization detection circuit 1 via the output terminal 521.
07.

Therefore, while the output from the OR circuit 511 is at the high level, a binary signal corresponding to the output signal from the arithmetic circuit 519 is output from the AND circuit 515.

Next, the operation of the circuit of FIG. 5 will be described with reference to the timing chart of FIG.

FIG. 9A shows the SWP generation circuit 137.
, The counter 111, the mask control circuit 109, and the state machine 125 are reset at each edge.

FIG. 6B shows detection pulses output from the comparison circuit 303 in the synchronization detection circuit 107 shown in FIG. 3, and 601 and 609 are pseudo sync detection pulses.
FIG. 6C shows the inspection result output from the IDP operation circuit 115. When there is no error, the pulses 611 and 613 are output.
Is output. For the sync data 603 and 607 in the figure, the IDP inspection result has no error, and for the sync data 605, the IDP inspection result has an error.

FIG. 6D shows the value of the ID data stored in the register 119.
Of 0x1415 is the actually detected value, 0x1 of 617
0x1416 of 414, 621, 0x1417 of 619
Are predicted ID data obtained by the arithmetic circuit 121, respectively.

FIG. 6E shows a signal indicating the comparison result of the comparison circuit 123.
This indicates that the value 0x1415 predicted from 1413 matches the value 0x1415 of the newly detected ID data.

FIG. 6F shows the transition state of the state machine 125. In FIG. 6F, after the state becomes idle at the edge of the SWP, the state transits to the wait1 state with the ID of 603, and the next block is idNG because it is idNG.
In the next block, the predicted value from the previous ID data matches the value of the detected ID data in the next block, and the continuity of the detected ID data is confirmed. After that, since no ID data is detected,
The state has shifted to the idle state again through the lock2 and lock3 states.

FIG. 6 (g) shows a lock signal indicating the locked state of the state machine 125. As shown in FIG. 6 (f), the state machine 125
It becomes high level in the lock3 state.

FIG. 6H shows a mask control signal output from the mask control circuit 109. As aforementioned,
The high-level period sync detection pulse is masked.

As shown in FIG. 6, in this embodiment, 601
Even if a pseudo sync is detected in
Since the sync detection pulse is not masked unless the test result indicates that there is no error, it is possible to prevent the false sync from being detected due to the transition to the sync mask state by the pseudo sync.

While the lock signal is confirmed to be in the capture state, the sync mask is not opened even if sync data to shift to the sync pulse 607 cannot be detected, and the pseudo sync 609 is masked. Thus, the counter 111 can be prevented from being reset. Also, the ID number 0x141 indicated by 623
7 can be continuously written to the memory 127.

As described above, in this embodiment, when the sync data is detected and the IDP inspection result shows no error, or when the lock signal indicates the capture state, the output signal from the arithmetic circuit 519 is output. The sync mask signal is output to the sync detection circuit 107 as it is.

In other words, in this embodiment, even if the sync data is not detected three times in a row or the IDP inspection result shows an error three times in a row, the lock signal is in the capture state. That is, in the state where the continuity of the ID data is confirmed, the sync mask is not opened and the sync mask state is maintained as it is.

Therefore, the data of the sync block whose continuity has been confirmed can be reliably written to the memory.

Further, since the mask is not opened when the continuity is confirmed, it is possible to prevent the false sync from being detected, and to stably detect the sync data.

In this embodiment, in FIG.
After being in the k1 state, the state changes to the idle state when the state is idNG three times in succession. In addition, for example, the state is idNG continuously m times (m is an integer of 2 or more). It is also possible to make a transition in the event of a change.

In the above embodiment, the case where the present invention is applied to a digital VTR has been described.
In addition, the present invention can be applied to an apparatus and a configuration for reproducing an information signal from a digital data string together with sync data and ID data via another recording medium or a transmission path,
It has a similar effect.

[0077]

As described above, according to the present invention,
Synchronous data can be detected accurately and stably.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration example of a VTR to which the present invention is applied.

FIG. 2 is a diagram showing a configuration of a sync block of data reproduced by the apparatus of FIG. 1;

FIG. 3 is a diagram illustrating a configuration of a synchronization detection circuit of the device of FIG. 1;

FIG. 4 is a diagram for explaining an operation of the state machine of FIG. 1;

FIG. 5 is a timing chart for explaining the operation of the device of FIG. 1;

FIG. 6 is a diagram illustrating a configuration of a mask control circuit of the apparatus in FIG. 1;

Claims (23)

[Claims] 1. A reproducing means for reproducing a data string composed of a plurality of synchronous blocks each having synchronous data and ID data; a synchronous detecting means for detecting the synchronous data from the reproduced data string; A reproducing apparatus comprising: an ID detection unit that detects the ID data; and a control unit that controls a detection operation of the synchronization detection unit using a detection result of the ID detection unit. 2. The method according to claim 1, wherein the control unit generates a mask signal using a detection result of the ID detection unit, and the synchronization detection unit detects the synchronization data from the reproduction data sequence based on the mask signal. The playback device according to claim 1, wherein 3. The reproducing apparatus according to claim 2, wherein said synchronization detecting means outputs a synchronization detection pulse only when said synchronization data is detected when said mask signal is in an open state. 4. The apparatus according to claim 3, wherein said control means determines continuity among the plurality of ID data detected by said ID detection means, and generates said mask signal in accordance with a result of the determination. The playback device according to any one of the preceding claims. 5. The control unit generates a first mask signal that is open only for a predetermined period at predetermined time intervals while a determination result indicating that there is continuity between the plurality of ID data is obtained, A second mask signal that is continuously opened when n (n is an integer of 2 or more) consecutive times indicating a lack of continuity is obtained. 5. The playback device according to 4. 6. The reproducing apparatus according to claim 5, wherein said control means further generates said mask signal using an output of said synchronization detecting means. 7. The reproducing apparatus according to claim 6, wherein the control unit generates the first mask signal in response to the detection of the synchronization data by the synchronization detection unit. 8. The control unit performs a comparison operation using a plurality of ID data values detected by the ID detection unit, and controls a detection operation of the synchronization detection unit based on the comparison result. The playback device according to claim 1, wherein 9. The control means for comparing a value obtained by adding a predetermined value to the value of the ID data detected by the ID detection means with a value of the ID data newly detected by the ID detection means. The reproducing apparatus according to claim 8, wherein 10. The plurality of synchronization blocks each further include ID error check data for detecting an error in the ID data, and the control unit further includes an ID error detection using the ID error check data. 2. The reproducing apparatus according to claim 1, wherein a detection operation of said synchronization detecting means is controlled using a result. 11. A memory for storing the reproduction data, wherein the control means further controls an operation of writing the reproduction data string to the memory based on a detection result of the ID data. The playback device according to claim 1. 12. A reproducing apparatus for reproducing a data string composed of a plurality of synchronous blocks each having synchronous data and ID data, wherein the synchronization is performed from the reproduced data string in accordance with the continuity of the ID data in the reproduced data string. A reproducing apparatus for detecting data. 13. A data sequence comprising a plurality of synchronization blocks each having synchronization data and ID data,
A method for detecting the synchronization data and the ID data from the reproduction data string, wherein a detection operation of the synchronization data is controlled using a detection result of the ID data. 14. The reproducing method according to claim 13, wherein a mask signal is generated using the detection result of the ID data, and the synchronous data is detected from the reproduced data sequence based on the mask signal. 15. The reproducing method according to claim 14, wherein a synchronization detection pulse is output only when the synchronization data is detected when the mask signal is in an open state. 16. The reproducing method according to claim 15, wherein continuity between the plurality of detected ID data is determined, and the mask signal is generated according to a result of the determination. 17. A first mask signal that is open only for a predetermined period every predetermined time while a determination result indicating that there is continuity between the plurality of ID data is generated, and n (n
17. The method according to claim 16, wherein a second mask signal that is continuously opened is generated in response to a determination result indicating that there is no continuity obtained continuously for two or more integer times. Playback method. 18. The reproducing method according to claim 17, wherein the mask signal is generated using an output of the synchronization detecting means. 19. The reproducing method according to claim 18, wherein the first mask signal is generated in response to the detection of the synchronization data by the synchronization detection means. 20. The apparatus according to claim 1, wherein a comparison operation is performed using a plurality of detected ID data values, and a detection operation of the synchronous data is controlled based on the comparison result.
3. The reproduction method according to 3. 21. The comparison operation according to claim 20, wherein in the comparison operation, a value obtained by adding a predetermined value to the detected ID data value is compared with a newly detected ID data value. Playback method. 22. The plurality of synchronization blocks further include ID error check data for detecting an error in the ID signal, and the synchronization block uses an ID error detection result using the ID error check data to perform synchronization. 14. The reproducing method according to claim 13, wherein a data detecting operation is controlled. 23. The reproducing method according to claim 13, wherein a writing operation of said reproduction data string to a memory storing said reproduction data string is controlled based on a detection result of said ID data.