JPH0397169A - Frame synchronizing circuit - Google Patents

Abstract

PURPOSE:To increase the detection rate of a 1st synchronizing pattern on the recording track by setting an error permissible value only in a period wherein the synchronizing pattern is generated possibly for the 1st time on the recording track. CONSTITUTION:A head switching pulse SP corresponding to the switching timing of the track T on a magnetic tape TP is inputted to an input terminal 1 and then supplied to a gate pulse generating circuit 2. This gate pulse generating circuit 2 receives the head switching pulse SP, generates a high-level gate pulse GP with specific pulse width W in the period wherein the 1st frame synchroniz ing pattern P0 is generated possibly on the track T, and supplies the gate pulse GP to a synchronizing pattern detecting circuit 3. Therefore, the detection rate of the frame synchronizing pattern at the head of the track is increased and the misdetection rate of other frame synchronizing patterns is decreased. Consequently, the 1st synchronizing pattern on the recording track is detected with high accuracy.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention is applicable to audio digital tape recorders (DAT), etc., which convert data into PCM (pulse code modulation) and record it on magnetic tape. The present invention relates to a frame synchronization circuit used in a PCM recording and reproducing device.

(Prior art) In a PCM recording and reproducing device that records PCM audio data etc. on a magnetic tape using a rotating head, when performing frame synchronization, as shown in the frame structure shown in Figure 6, Frame synchronization is performed by recording a fixed pattern of synchronization signal (synchronization pattern) P in a time-division manner and detecting this synchronization pattern P during playback.In the figure, the code 1 indicates a control signal; D indicates data to be transmitted such as audio data.Furthermore, FIG. 7 schematically shows a frame synchronization pattern P recorded on a track T on the magnetic tape TP.By the way, this synchronization pattern P When detecting pattern P, it may become impossible to detect pattern P due to the influence of noise mixed into the data in the communication system (signal transmission system). Conventionally, pattern errors were tolerated to some extent in order to eliminate this problem. The synchronization pattern P can be effectively detected by implementing error tolerance in which the synchronization pattern P is detected.

Also, if detection is difficult even with error tolerance implementation,
Synchronization maintenance has been carried out by forcibly generating a synchronization signal based on the synchronization and continuity of the synchronization signal to achieve synchronization.

(Problems to be Solved by the Invention) In implementing the above-mentioned error tolerance, increasing the error tolerance value reduces the undetectable rate due to errors; however, even things that are not originally synchronous patterns may be mistakenly detected as synchronous patterns. , and the number of false positives increases. Therefore,
Normally, the desired performance was achieved by using both error tolerance and synchronization maintenance.

On the other hand, the first frame synchronization pattern P on track T after head switching. In the case of detecting the synchronization, it is impossible to maintain synchronization as described above due to the occurrence of discontinuity due to head switching. Therefore, it is necessary to detect the leading synchronization pattern P0 only by the pattern detection operation, but detection errors are generally likely to occur at the beginning and end of the tape due to head impact, tape tear, etc.

Therefore, a synchronization pattern P is created with a large error tolerance. It is conceivable to increase the detection rate of , but as described above, if the error tolerance is set large, the probability of false detection will increase, and as a result, the accuracy of synchronization detection will be lowered.

The present invention was proposed to solve such problems, and an object of the present invention is to provide a frame synchronization circuit that can detect the first synchronization pattern on a recording track with high precision.

[Structure of the Invention (Means for Solving the Problems)] In order to achieve the above object, a frame synchronization circuit according to the present invention records and reproduces digital signals on tracks on a magnetic tape using a rotating magnetic head. In a digital recording and reproducing device that performs a digital recording/reproduction process, when detecting the first frame synchronization pattern recorded at the beginning of the track, the first frame synchronization pattern is detected at a timing position where the first frame synchronization pattern is likely to occur based on the head switching pulse.
A gate pulse generation circuit that generates a gate pulse, and a frame synchronization pattern recorded on the track by changing an error tolerance when detecting the frame synchronization pattern based on the gate pulse supplied from the gate pulse generation circuit. A frame synchronization pattern detection circuit is provided.

(Function) According to the above-described configuration, the error tolerance is set to a large value when the gate pulse is supplied to the frame synchronization detection circuit,
By setting the error tolerance to a small value when no gate pulse is supplied, the detection rate of the frame synchronization pattern at the beginning of the track can be increased, and the false detection rate of other frame synchronization patterns can be reduced.

(Example) Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIG. 1 is a block diagram of essential parts showing an embodiment of a frame synchronization circuit according to the present invention.

In this figure, a head switching pulse SP corresponding to the switching timing of the track T on the magnetic tape TP is input to the input terminal l, and this head switching pulse SP
P is supplied to the gate pulse generation circuit 2. In this gate pulse generation circuit 2, the head switching pulse SP
(Responding to Fig. 2 (a)>), the pulse width W has a predetermined pulse width W as shown in Fig. 2 (b) during a period in which the first frame synchronization pattern P0 may occur on the track T. A high level (“H” level) gate pulse GP is set and this gate pulse GP is supplied to the synchronization pattern detection circuit 3.

In the synchronization pattern detection circuit 3, the gate pulse generation circuit 2
When the error tolerance value is set in response to the output from the
For example, the error tolerance value K is set to "2", and when the gate pulse GP is not supplied and the input is at a low level ("off" level), the error tolerance value K is set to "rl". Here, if the error tolerance value K is set to "2", code errors at the time of detection are tolerated up to 2 bits, and if the error tolerance value K is set to "1", the code error at the time of detection is tolerated. Sign error is l
Only bits are allowed.

Synchronization pattern detection time 13 with error tolerance value K set
The data reproduced from the track T on the magnetic tape TP is supplied from the input terminal 4, and a frame synchronization pattern P shown in FIG. 2(C) is detected. Output terminal 5
The detected synchronization signal sync is output from.

At this time, the first frame synchronization pattern P on track T. During the period in which synchronization pattern P is likely to be detected, the error tolerance value K is set to a large value of "2" as described above, so the detection rate increases and the synchronization pattern P. can be detected effectively. In addition, the pulse width W of the gate pulse GP
By narrowing , it is possible to shorten the detection time of the synchronization pattern P0 in a state where the error tolerance value K is set to a large value, and therefore it is possible to reduce the false detection rate.

Figure 3 shows, for example, the probability P that synchronization detection will be impossible due to the difference in error tolerance K when the frame synchronization pattern is 16 bits and the pit error rate is 3X10'.
1 and the probability of false detection P2. As can be seen from this Figure 3, the error tolerance value K is changed from "1" to "
2'', the probability P1 of being undetectable is improved by 103 orders. On the other hand, since the probability P2 of false detection is on the order of 101, the pulse width W of the gate pulse GP is
The interval in which the error tolerance value K is set to "2" by narrowing the range is 17 in total.
If it is limited to 10, the probability of false detection P2 will drop to 1/10, and the influence of increasing the error tolerance value K can be eliminated.

Note that if the first synchronization pattern P0 on the track T can be detected effectively, other synchronization patterns can be detected with high accuracy by using both error tolerance and synchronization maintenance thereafter.

Next, a specific circuit example of the synchronization pattern detection circuit 3 will be explained based on FIG.

In this figure, the data reproduced from the track T is supplied to the shift register 6 from the input terminal 4, and each bit output of the shift register 6 is output to each exclusive NOR gate 7. The other input terminal of these exclusive NOR gates 7 has
For example, data of a 16-bit synchronization pattern predetermined as 1010...10 is supplied from the input terminal 8, and the output data of the shift register 6 is compared in the exclusive NOR gate 7. Each exclusive NOR gate 7 outputs "1" when two input bits match, so when a complete synchronization pattern is input into the shift register 6 from the input terminal 4, each exclusive NOR gate 7
The 16 inputs of the decoder 9 to which the outputs of are supplied are all "1".

Here, error tolerance is set in the decoder 9,
As shown in FIG. 5, the output states of the output terminals OUTI and OUT2 are determined by the number of input "1"s. Since the output terminal OUTI becomes "1" when the number of input "1"s is 15 or 16, the error tolerance value K is set to "1" at this time. The output terminal OUT2 is
Only when the number of input “1°” is 14, it becomes “°1”.

One output terminal OUTI of the decoder 9 is connected to the OR gate 1.
0 to the output terminal 5. The other output terminal OUT2 of the decoder 9 is connected to the other input terminal of the OR gate 10 via the AND gate 11, and the gate pulse GP from the gate pulse generation circuit 2 is connected to the other input terminal of the AND gate 11. It is supplied from the input terminal 12.

In this structure, when the gate pulse GP is "0" {Lll level}, the output of the output terminal OUTI becomes the output of the output terminal 5, and the error tolerance value K is set to rl,
Synchronization pattern detection output (synchronization signal sy
nc) can be taken out from the output terminal 5.

Also, the gate pulse GP is “1” <“H′゛ level>
When , either output terminal OUTI or OUT2 is “
1", "1' is output to the output terminal 5, so in this case, the synchronization pattern detection output (synchronization signal sync) when the error tolerance value K is set to "2" can be taken out from the output terminal 5. can.

[Effect of the Invention] As explained above, according to the present invention, based on the head switching pulse, the error tolerance is set to a large value only for the period in which a synchronization pattern may first occur on the recording track. , it is possible to increase the detection rate of the first synchronization pattern on the track. Furthermore, since detection of synchronization patterns in other parts is performed with a small error tolerance, false detections can be reduced, and overall frame synchronization pattern detection accuracy can be improved.

[Brief explanation of drawings]

FIG. 1 is a block diagram of main parts showing an embodiment of the frame synchronization circuit according to the present invention, FIG. 2 is a waveform diagram for explaining the operation of the frame synchronization circuit of FIG. 1, and FIG. 3 is a diagram showing the error tolerance. 4 is a circuit diagram showing a specific circuit example of the synchronization pattern detection circuit, and FIG. 5 is the output of the decoder constituting the synchronization pattern detection circuit of FIG. 4. FIG. 6 is a diagram schematically showing the frame structure, and FIG. 7 is a diagram schematically showing the frame synchronization pattern on the track of the magnetic tape. 2... Gate pulse generation circuit 3... Synchronization pattern detection circuit 6... Shift register 7... Exclusive NOR gate 9... Decoder 10.
...Or Gate 11...And Gate P.
Po...Synchronization pattern SP...Head switching pulse GP...Gate pulse K...Error tolerance W.
...Pulse width TP...Magnetic tape T...
·truck

Claims (1)

[Claims] In a digital recording and reproducing device that uses a rotating magnetic head to record and reproduce digital signals on a track on a magnetic tape, a head switching pulse is used to detect the first frame synchronization pattern recorded at the beginning of the track. Based on this, there is a gate pulse generation circuit that generates a gate pulse at a timing position where the first frame synchronization pattern may occur, and an error when detecting a frame synchronization pattern based on the gate pulses supplied from this gate pulse generation circuit. A frame synchronization circuit comprising: a frame synchronization pattern detection circuit that detects a frame synchronization pattern recorded on the track by changing a tolerance value.