JP2896478B2 - Remote control pulse receiving circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a remote control pulse receiving circuit of a so-called remote control device for remotely controlling home electric appliances such as a television set, a VTR and an air conditioner.

[0002]

2. Description of the Related Art In recent years, home appliances such as television sets, VTRs, and air conditioners are generally operable by remote control. FIG. 5 is a block diagram showing a conventional configuration example of a remote control pulse receiving circuit provided on a controlled side of such a remote control device (hereinafter, referred to as a remote control device) such as a home appliance.

The type of remote control pulse differs depending on the manufacturer of the home electric appliance. Generally, as shown in FIG. 6, a pulse sequence having different pulse-to-edge intervals as shown in FIG. Pulse with short edge interval
A long pulse is defined as data "1" as "0", and such data "0" or "1".
Is different depending on the manufacturer of each remote control device.

The number of edges of a pulse transmitted in one transmission, in other words, the number of bits of data varies from several bits to several tens of bits depending on the manufacturer of each remote control device. However, in one remote control system, the number of bits of data transmitted each time is constant. Various commands can be transmitted from the remote control device by combining "0" and "1" with this fixed number of bits.

In FIG. 5, reference numeral 1 denotes a pulse input terminal to which a remote control pulse is input. The remote control pulse input to the pulse input terminal 1 is applied to an edge detection circuit 2 to detect a rising edge of the pulse, and the edge detection circuit 2 outputs a one-shot pulse 2a in synchronization with the timing.
This one-shot pulse 2a is applied to the reference clock counter 4,
It is input to the shift register 6 and the edge counter 7.

Reference numeral 3 denotes a clock generation circuit which generates a reference clock and supplies it to the above-described reference clock counter 4 and a CPU 9 described later.

The reference clock counter 4 is reset by the one-shot pulse 2a, and starts counting the reference clock generated by the clock generation circuit 3 described above. The count value of the reference clock counter 4 is given to the comparison circuit 5. Reference numeral 10 is a reference data register,
The circuit shown in FIG. 5 holds reference data predetermined in hardware in accordance with the specification of the remote control pulse to be received.

The comparison circuit 5 is provided with the reference data register 10 described above.
Is compared with the count value of the reference clock counter 4 immediately before being reset by the one-shot pulse 2a. For example, as shown in FIG. 7, the specification of the remote control pulse to be received is
Assuming that the edge interval of data “0” is 2 msec and the edge interval of data “1” is 4 msec, data “0” and “0”
The boundary for judging “1” is set to 3 msec. In such a case, if the reference clock cycle is 50 μsec, the data “60” in decimal is held as reference data in the reference data register 10 described above. ing.

The comparison circuit 5 sets "0" when the count value of the reference clock counter 4 is smaller than the reference data held in the reference data register 10 and "1" when the count value is larger than the reference data held in the reference data register 10 as the remote control data 5a. Output to the shift register 6.

The shift register 6 has a one-shot pulse 2a.
The remote control data 5a is sequentially stored while being shifted in synchronization with. As described above, the number of bits constituting the shift register 6 is equal to the number of bits of data transmitted at one time by the remote control method applied to the circuit shown in FIG.

The edge counter 7 is reset by a control signal 7b provided from the CPU 9 and counts the one-shot pulse 2a. The edge counter 7 is configured to generate an overflow when the count value becomes equal to the number of constituent bits of the shift register 6. When an overflow occurs, the edge counter 7 outputs an interrupt request signal 7a to the CPU 9.

The CPU 9 receives the interrupt request signal 7a, reads the contents of the shift register 6 via the data bus 8, and executes a process corresponding to a combination of data "0" and "1".

[0013]

Since the conventional remote control pulse receiving circuit of the remote control device for home electric appliances or the like is configured as described above, the comparison value with the reference clock is a fixed value and only one type is set. It is difficult to receive any remote control pulse as desired by the user. Also, in the above conventional example,
The edge counter, which is a means for counting the edges of the received pulse, overflows only when a certain value is counted, and generates an interrupt request signal to the CPU as the control means. Therefore, such a conventional remote control pulse receiving circuit can only receive a remote control pulse of a specific specification, and cannot cope with various types of remote control pulse formats. There is also a problem that the remote control device attached to the home appliance cannot be used for operating other home appliances.

[0014]

The invention according <br/> in made in view of the circumstances Ah is, the remote control pulse capable of generating an interrupt request signal to the control unit at the timing of receiving the number of data bits of arbitrary It is intended to provide a receiving circuit.

[0016]

[0017]

A remote control pulse receiving circuit according to the present invention compares a count value of a counting means for counting the number of edges of a received pulse with a value arbitrarily set by the control means. The control means is configured to be interrupted when the two match.

[0018]

[0019]

[0020]

[0021]

According to the present invention, the value arbitrarily set by the control means is compared with the number of edges of the received pulse counted by the pulse counting means, and if the two coincide, the control means is interrupted.

[0022]

[0023]

[0024]

[0025]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the drawings showing the embodiments.

FIG. 1 through FIG. 4 is a block diagram showing a remote control pulse receiving circuits according to Examples 1-4. In FIGS. 1 to 4, the same reference numerals as those in FIG. 5 referred to in the description of the above-described conventional example indicate the same or corresponding parts.

[0027] First, a description about the remote control pulse receiving circuits of the first embodiment with reference to FIG.

In FIG. 1, reference numeral 1 denotes a pulse input terminal to which a remote control pulse is input. The remote control pulse input to the pulse input terminal 1 is supplied to an edge detection circuit 2 as edge detection means.
, The rising edge of the pulse is detected, and the edge detection circuit 2 outputs a one-shot pulse 2a in synchronization with the timing. The one-shot pulse 2a is input to the reference clock counter 4, shift register 6, and edge counter 7.

Reference numeral 3 denotes a clock generation circuit which generates a reference clock and supplies it to the above-described reference clock counter 4 and a CPU 9 as control means described later.

The reference clock counter 4 functions as clock counting means, and is reset by the one-shot pulse 2a and starts counting the reference clock generated by the clock generation circuit 3. The count value of the reference clock counter 4 is given to the comparison circuit 5. Reference numeral 11 denotes a mask ROM as storage means.
In the manufacturing stage, an arbitrary value is written as reference data according to the specification of the remote control pulse to be received by the circuit shown in FIG.

The comparison circuit 5 functions as comparison determination means,
The reference data held by the mask ROM 11 is compared with the count value of the reference clock counter 4 immediately before being reset by the one-shot pulse 2a. For example, as shown in FIG. 7, the specification of the remote control pulse to be received is such that the edge interval of data “0” is 2 msec,
Assuming that the edge interval of data “1” is 4 msec,
The boundary for judging data “0” and “1” is set to 3 msec. In such a case, if the cycle of the reference clock is 50 μsec, data “60” in decimal is written in the mask ROM 11 as reference data in the stage of manufacturing this circuit.

When the count value of the reference clock counter 4 is smaller than the reference data held in the mask ROM 11, the comparison circuit 5 shifts "0" as the remote control data 5a. Output to register 6. The shift register 6 sequentially stores the remote control data 5a while shifting it in synchronization with the one-shot pulse 2a. As described above, the number of bits of the shift register 6 is equal to the number of bits of data transmitted at one time by the remote control method applied to the circuit shown in FIG.

The edge counter 7 is reset by a control signal 7b provided from the CPU 9 and counts the one-shot pulse 2a. The edge counter 7 is configured to generate an overflow when the count value becomes equal to the number of constituent bits of the shift register 6. When an overflow occurs, the edge counter 7 outputs an interrupt request signal 7a to the CPU 9. The edge counter 7 is reset by a control signal 7b given from the CPU 9, and counts the one-shot pulse 2a. When the count value becomes equal to the number of bits constituting the shift register 6, an overflow occurs. Therefore, the edge counter 7 sends an interrupt request signal to the CPU 9.
Output 7a.

The CPU 9 receives the interrupt request signal 7a, reads the contents of the shift register 6 via the data bus 8, and executes a process corresponding to a combination of data "0" and "1".

Therefore, the first embodiment shown in FIG.
In the remote control pulse receiving circuits manufacturing stage according to the edge spacing it becomes possible to write an arbitrary value as the reference data in the mask ROM 11, the remote control system of various specifications, specifically data "0" And data "
It is possible to correspond to the difference from the edge interval of 1 ″.

[0036] Next, a description will be given of the remote <br/> over preparative control pulse receiving circuits according to the second embodiment with reference to FIG.

Embodiment 2 shown in the block diagram of FIG.
The difference from the first embodiment shown in FIG. 1 is that the register 12 is used in the second embodiment instead of the mask ROM 11 used in the first embodiment as storage means for the reference data. Further, this register 12 can set an arbitrary value as reference data from the CPU 9 by software. Real Other configurations and operations shown in Figure 1
This is exactly the same as in the first embodiment.

The register 12 can write an arbitrary value as reference data under the control of the CPU 9 according to the specification of the remote control pulse to be received by the circuit shown in FIG. The writing of data into the register 12 by the CPU 9 is processing performed by software. In other words, the value set as the reference data in the register 12 is the value set in the second embodiment shown in FIG.
It is possible to set an arbitrary value at the time of writing the control software to a ROM (not shown) in the circuit manufacturing stage.

Accordingly, the second embodiment shown in FIG.
Of the production phase of the remote control pulse receiving circuits, since the value stored in the register 12 as reference data can be set in software to an arbitrary value, the remote control system of various specifications, specifically, data"
It is possible to correspond to the difference between the edge interval of 0 "and the edge interval of data" 1 ".

Next, a description will be given to the remote control pulse receiving circuits of Example 3 with reference to FIG.

Embodiment 3 shown in the block diagram of FIG.
The second embodiment is different from the second embodiment shown in FIG. 2 in that the comparison circuit 14 compares the count value of the edge counter 7 and a register capable of setting an arbitrary value from the CPU 9 to the comparison circuit 14.
13 is provided. Other configurations and operations are exactly the same as those of the second embodiment shown in FIG.

The edge counter 7 has the above-described conventional example and its implementation.
As in the first and second examples, the one-shot pulse 2a is reset by being reset by the control signal 7b given from the CPU 9. However, in the third embodiment , the count value of the edge counter 7 is output to the comparison circuit 14.

Reference numeral 13 denotes a register.
Any value can be written under the control of. The writing of data into the register 13 by the CPU 9 is a process performed by software. Therefore, the register
The value set as the reference data in 13 can be set to any value at the time of writing the control software to the ROM (not shown) in the manufacturing stage of the circuit of the third embodiment shown in FIG. It is.

The value set in the register 13 is given to the above-mentioned comparison circuit 14, and the comparison circuit 14 compares the count value of the edge counter 7 with the value held in the register 13. If they match, an interrupt request signal 14a is output to the CPU 9.

The CPU 9 outputs the interrupt request signal 14a from the comparison circuit 14.
, The contents of the shift register 6 are read via the data bus 8, and the processing corresponding to the combination of the data "0" and "1" is executed.

Therefore, the third embodiment shown in FIG.
In the manufacturing stage of the remote control pulse receiving circuits, it becomes possible to set the value held in the register 13 in the software manner any value, the remote control system of various specifications, specifically sent each time It is possible to cope with the difference in the number of bits of the data. Noh.

Next, a description will be given to the remote control pulse receiving circuits of the fourth embodiment with reference to FIG.

Embodiment 4 shown in the block diagram of FIG.
And the third embodiment shown in FIG. 3 described above is that the count value of the edge counter 7 is output to the data bus 8 via the signal line 7c. Therefore, the CPU 9 can read the count value of the edge counter 7 output to the data bus 8 at any time. Other configurations and operations are exactly the same as those of the third embodiment shown in FIG.

Therefore, the fourth embodiment shown in FIG.
The remote control pulse receiving circuits, CPU 9 since it is possible to read the count value of the comparison circuit 14 at any time, to expand application usage in terms of software processing. For example, the count value of the edge counter 7 is
, And the content of the shift register 6 is read at the time of coincidence with the predetermined value by software processing, and the subsequent processing is performed.

It is to be noted that the above-described first and third embodiments can be combined, and that the second and third embodiments can be combined. Further, the fourth embodiment can be combined with the first, second and third embodiments. It is.

[0051]

According to the present invention, the number of received pulses and the number of received pulses can be set by the CPU, so that it is possible to easily cope with remote controllers of different systems. .

[0052]

[0053]

[0054]

[Brief description of the drawings]

1 is a block diagram showing the configuration of the actual Example 1 of the present invention.

FIG. 2 is a block diagram illustrating a configuration of a second embodiment .

FIG. 3 is a block diagram illustrating a configuration of a third embodiment .

FIG. 4 is a block diagram illustrating a configuration of a fourth embodiment .

FIG. 5 is a block diagram showing a configuration example of a conventional remote control pulse receiving circuit.

FIG. 6 is a waveform diagram showing data “0” and data “1” of a remote control pulse.

FIG. 7 is a waveform diagram illustrating an edge interval between data “0” and data “1” of a remote control pulse.

[Explanation of symbols]

 2 Edge detection circuit 3 Clock generation circuit 4 Reference clock counter 5 Comparison circuit 6 Shift register 7 Edge counter 9 CPU 10 Reference data register 11 Mask ROM 12 Register 13 Register 14 Comparison circuit

Claims (1)

(57) [Claims] 1. A predetermined combination of a pulse representing data “0” having a first time interval between edges and a pulse representing data “1” having a second time interval between edges. Edge detecting means for receiving a remote control pulse representing one command by a number of pulses and detecting an edge of each pulse; counting means for resetting each time the edge detecting means detects an edge and counting a reference clock; A reference data storage unit that stores, as reference data, the number of the reference clocks corresponding to an intermediate time between the first time and the second time; a value of the counting unit and the reference data storage unit By comparing the received pulse with the reference data, it is determined whether the received pulse represents data “0” or data “1”. A comparison / determination unit that outputs a signal; a storage unit that stores a plurality of bits of an output signal of the comparison / determination unit; a count of the number of times the edge detection unit has detected an edge; Edge counting means for outputting a signal, and control means for reading out the content stored in the storage means when the edge counting means outputs the predetermined signal, and executing processing in accordance with the content. A remote control pulse receiving circuit, comprising: a register for storing a value given from the control means; and a comparing means for comparing a value stored in the register with a count value of the edge counting means. Reads out the content stored in the storage means when the comparison result of the comparison means matches, and executes a process corresponding to the content. Remote control pulse receiving circuit, characterized in that are no order to the row.