JPH11338712A - Interruption sequence saving circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the precision of a fault analysis using interruption information and to decrease the man-hour for the fault analysis by eliminating a disorder of a fault place due to the difference between an interruption generation sequence and an interruption sequence by saving where and when an interruption request is generated in a storage means in the generation order each time the interruption request in generated. SOLUTION: A mask circuit 11 gives priority to maskable interruption request signals and when an interruption request of higher priority is generated, an interruption processing for the interruption request of higher priority is performed precedently to interruption requests of lower priority. Each time an interruption request is generated, the interruption request source and interruption generation time information are written in order in a storage means 23. Then the interruption request source and interruption generation time stored in the storage means 23 are freely read out by a CPU 12. Here, an address generating means (counter 22) increases an address by a specific value after interruption information is written to the storage means 23.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus such as a computer, and more particularly to an interrupt control circuit capable of storing an interrupt order in an information processing apparatus.

[0002]

2. Description of the Related Art In an information processing apparatus such as a computer, FIG.
As shown in the figure, the CPU 1 responds to an interrupt request from each port.
2 is provided with a mask circuit 11 that performs a mask operation in accordance with an instruction from the second instruction. When an interrupt request is generated from each port, the mask circuit operates according to the operating status of the CPU 12.
In some cases, it is not possible to immediately execute the interrupt processing in step 2, so that the interrupt request is temporarily put into a waiting state.

In the initial state, the mask is closed, and when the CPU 12 is ready to accept the interrupt processing, the CPU 12 issues a command to the mask circuit 11 to open the mask. Upon receiving this command, the mask circuit 11 releases the mask and outputs the interrupt state at that time to the CPU 12 for a certain period of time. The CPU 12
Confirm this, and execute the interrupt processing. When the interrupt processing in the CPU 12 is completed, the mask of the mask circuit 11 is closed again, and the same processing is performed thereafter.

In some cases, a plurality of interrupt requests are issued almost simultaneously. Multiple interrupt requests 1-4 during mask closure
Occurs, the CPU 12 confirms a plurality of interrupt requests at once by opening the mask. In this case, the CPU
12 determines which interrupt processing should be executed with the highest priority according to interrupt priorities specified in advance by software or the like,
Processing is performed from the one with the highest priority. As described above, priorities are set in advance for a plurality of interrupt requests, and the interrupt processing is executed from the interrupt request with a higher priority, thereby achieving higher processing efficiency. .

[0005]

However, in the above-described conventional interrupt control system, the order of generation of interrupt requests and the order of processing for the interrupt are not always the same. May be.

For example, if an abnormality occurs in a certain port while the mask is closed, the port issues an interrupt request to the CPU 12 to notify the CPU of the abnormality. At this time, it is assumed that an interrupt request is issued from another port before the CPU 12 releases the mask. In this case, if the port that issued the interrupt request later has a higher priority, the CPU 12 performs the interrupt processing first after the mask is released.
This is the higher priority interrupt request that issued the interrupt request later.

When the order of the interrupt request to the CPU and the order of the interrupt processing in the CPU are reversed, it becomes difficult to correctly investigate the cause of the failure, and the accuracy of the failure analysis is reduced. In addition, there is a problem that the number of work steps and the load required for the analysis are increased.

Accordingly, the present invention has been made in view of the above problems, and an object of the present invention is to provide an interrupt control circuit capable of preserving an interrupt generation order.

[0009]

In order to achieve the above object, the present invention comprises means for storing the location and time of occurrence of interrupt requests in a storage unit in the order of occurrence of interrupt requests each time an interrupt request is generated. Due to the difference between the order and the order of the interrupt processing, the analysis work that required a large amount of work is reduced.

[0010]

Embodiments of the present invention will be described below. In a preferred embodiment of the interrupt control circuit of the present invention, priorities are assigned to a plurality of interrupt request signals that can be masked by a mask circuit (11 in FIG. 1), and the higher priority When an interrupt request occurs, in an information processing apparatus in which an interrupt process is performed on the higher priority interrupt request prior to the lower priority interrupt request than the interrupt request, A storage unit (23 in FIG. 1) in which an interrupt request source is associated with interrupt occurrence time information every time an interrupt occurs.
Means (21, 2 of FIG. 1)
2), and the CPU (22 in FIG. 1) is configured so that the interrupt request source and the interrupt occurrence time information stored in the storage means (23 in FIG. 1) can be read out freely.
In the embodiment of the present invention, the storage means (2 in FIG. 1)
3) an address generating means (22 in FIG. 1) for generating an address for writing the interrupt information to (3), and the address generating means stores the interrupt information in the storage means (23 in FIG. 1).
Then, the address is increased by a predetermined value.

An embodiment of the present invention will be described in more detail with reference to the drawings. FIG. 1 is a diagram showing a configuration of an embodiment of the present invention. Referring to FIG. 1, one embodiment of the present invention includes a mask circuit 11 to which interrupt request signals 1, 2, 3, and 4 are input, a CPU 12, and an interrupt generation order storage circuit 31. I have. Interrupt generation order storage circuit 31
Comprises an interrupt circuit 21, a counter 22, a memory 23, and a timer 24. Note that the number of interrupt request signals is not limited to four.

The interrupt circuit 21 is connected to interrupt request signals 1 to 4, and when any of the interrupt request signals 1 to 4 is input, the interrupt circuit 21 The interrupt location (the source of the interrupt request) and the time at which the interrupt request occurred are stored.
At this time, the write address to the memory 23 is supplied from the counter value of the counter circuit 22. The counter circuit 23 is incremented each time the interrupt location and its time are stored in the memory 23. Note that the interrupt circuit 21 acquires the interrupt request occurrence time from the timer 24.

Next, when the interrupt request signals 1 to 4 are input again, the interrupt circuit 21 stores the current interrupt location and time in the incremented address as data. Hereinafter, the same processing is performed.

When performing a failure analysis, the CPU 12
By reading data from the memory 23 and outputting the data to the output device, the order in which interrupts occur can be confirmed.
Therefore, the confusion of the failure analysis due to the difference between the order of the interrupt occurrence and the order of the interrupt processing can be eliminated, and the work efficiency can be improved. Hereinafter, a specific description will be given in accordance with embodiments.

[0015]

Referring to FIG. 1, in one embodiment of the present invention, an interrupt generation order preserving circuit 31 is provided. When the interrupt request signals 1 to 4 are input, the interrupt generation order preserving circuit 31 includes an interrupt circuit 21 for storing the location and time of the interrupt in a memory 23. Timer circuit 24 for transmitting, and memory 2 for storing interrupt state
3 and is also connected to a counter circuit 22 for generating a write address of the memory 23. In the event of a failure, the CPU 12 obtains information on the order in which the interrupts occur in the memory 2.
3 for controlling the access address of the memory 23, and also to the counter circuit 22.

The operation of this embodiment will be described. Normal,
Interrupt request signals 1 to 4 from each port are input to a mask circuit 11 for holding signal information before inputting to the CPU 12 or masking the interrupt. CPU 12
Confirms the interrupt port from the mask circuit 11 and performs an interrupt process.

The interrupt request signals 1 to 4 are also input to the interrupt circuit 21. When the interrupt request signals 1 to 4 are input to the interrupt circuit 2, the interrupt circuit 2 uses the input interrupt request signal as a trigger to check the interrupt port and its time. At this time, the time is managed by the timer circuit 24 and the CPU 12
The time can be set by setting from.

From the timer circuit 24 to the interrupt circuit 21,
At any time, the current time is input.

When an interrupt request signal is input, the interrupt circuit 21 writes the confirmed interrupt port and its time (interrupt request occurrence time) to the memory 23. At the same time, the interrupt circuit 21 notifies that the counter circuit 22 has been interrupted.

The counter circuit 22 receives the notification from the interrupt circuit 21 and increments the counter value. The next input interrupt information (interrupt port and interrupt occurrence time) is written to the incremented address. Thereafter, similarly, the interrupt information is sequentially written to the memory 23.

FIG. 2 is a diagram showing an example of the format of interrupt information written from the interrupt circuit 21 to the memory 23 in one embodiment of the present invention. Referring to FIG. 2, the first byte is an interrupt port, followed by an interrupt occurrence time [hour] in the second byte, an interrupt occurrence time [minute] in the third byte,
The interrupt occurrence time [seconds] is stored in the fourth byte, and the above four-byte information is written to the memory 23 for one interrupt.

At this time, assuming that the transfer from the interrupt circuit 21 to the memory 23 is two accesses of 2 bytes, it is assumed that an interrupt request is generated from each import in the order shown in FIG. The contents of the interrupt information written in the block 23 are as shown in FIG.

When obtaining interrupt information at the time of a failure or the like, the CPU 12 reads the current counter value from the counter circuit 22 and checks the latest address value. The CPU 12 acquires necessary interrupt information by reading the memory 23 based on the latest address value.

The counter 22 for generating the access address of the memory 23 stores the interrupt information cyclically by resetting the address to the minimum access address after the counter value reaches the maximum access address of the memory 23. You may make it.

[0025]

As described above, according to the present invention,
The effect of eliminating confusion in failure analysis due to the difference between the order in which interrupts occur and the order of interrupts, improving the accuracy of failure analysis using interrupt information, and significantly reducing the number of work steps during failure analysis. To play.

The reason is that, in the present invention, each time an interrupt request is generated, the source of the interrupt and the time information are sequentially stored in the storage device, so that the storage device is read out at the time of failure analysis, whereby This is because the exact order of occurrence can be traced.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a diagram showing an example of a format of interrupt information stored in a memory according to an embodiment of the present invention.

FIG. 3 is a diagram showing a sample example of interrupt information stored in a memory according to an embodiment of the present invention.

FIG. 4 is a diagram for explaining one embodiment of the present invention;
FIG. 9 is a diagram illustrating an example of an interrupted port and an interrupt occurrence time.

FIG. 5 is a diagram illustrating an example of a conventional interrupt control circuit.

[Explanation of symbols]

 1, 2, 3, 4 Interrupt request signal 11 Mask circuit 12 CPU 21 Interrupt circuit 22 Counter 23 Memory 24 Timer 31 Interrupt generation order storage circuit

Claims (7)

[Claims] An interrupt control circuit of an information processing apparatus includes means for controlling so as to save an interrupt request source and interrupt occurrence time information in a storage means every time an interrupt request is input. Characteristic interrupt control circuit. 2. An interrupt control circuit of an information processing apparatus, comprising: means for controlling so that each time an interrupt request is input, an interrupt request source and interrupt occurrence time information are associated with each other and written into storage means. An interrupt control circuit, wherein the interrupt request source and the interrupt occurrence time information stored in the storage means can be read from the CPU. 3. A priority is assigned to a plurality of maskable interrupt request signals, and when an interrupt request with a higher priority occurs, an interrupt request with a lower priority than the interrupt request. In an information processing apparatus in which the interrupt processing for the higher priority interrupt request is performed with priority, the interrupt request source and the interrupt occurrence time information correspond each time an interrupt request is generated. An interrupt request source and an interrupt occurrence time information stored in said storage means which can be read out from the CPU side. . 4. An interrupt control circuit comprising a mask circuit for inputting interrupt request signals from a plurality of interrupt sources and controlling on / off of transmission of the plurality of interrupt request signals to a CPU. Each time an interrupt request is made to any one of the plurality of interrupt request signals, obtains interrupt information consisting of the request source of the interrupt request and interrupt occurrence time information, and stores the interrupt information in storage means. An interrupt control circuit comprising means for controlling writing. 5. An address generating means for generating an address for writing the interrupt information to the storage means, wherein the address generating means sets an address every time the interrupt information is written to the storage means. 5. The interrupt control circuit according to claim 4, wherein the value is increased by a value. 6. An information processing apparatus comprising a mask circuit for inputting interrupt request signals from a plurality of interrupt sources and controlling on / off of transmission of the plurality of interrupt request signals to a CPU. Each time an interrupt request is made to any of the interrupt request signals, the CPU acquires interrupt information consisting of the request source of the interrupt request and interrupt occurrence time information, and writes the interrupt information to storage means. Means for generating an address for writing the interrupt information to the storage means, wherein an interrupt request is made, and the address is written after the interrupt information is written to the storage means. An information processing apparatus, comprising: an interrupt generation order storage circuit having address generation means for updating the number of times of the interrupt information, and timer means for providing time information. 7. The information processing apparatus according to claim 6, wherein said address generating means comprises a counter.