JPH0668015A - Assign information holding circuit - Google Patents

Abstract

PURPOSE:To automatically reset assign information in the case that it is not reset within a prescribed time. CONSTITUTION:An assign information set signal 101, an assign information reset signal, 102, and time data 106 of the output signal of a time data holding circuit 4 are inputted to a timer circuit 3, and a time counting end signal 104 of this circuit 3 is inputted to an OR circuit 2, and OR between this signal and the assign information reset signal 102 is operated and is outputted as a flip flop circuit reset signal 105. A flip flop circuit 1 outputs assign information 103 by the assign information set signal 101.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention holds the assignment information in the peripheral device in order to maintain the right to control the peripheral device even after the host device disconnects the peripheral device in the information processing device. The present invention relates to an assignment information holding circuit for storing.

[0002]

2. Description of the Related Art In an information processing apparatus having a large-to-medium-scale configuration, the following means are used in order to prevent the performance of a higher-order device from being degraded while waiting for a peripheral device having a slow processing speed. Processing for the device.

That is, first, a peripheral device is connected and a processing instruction is given, the peripheral device is temporarily disconnected, another process is executed while the peripheral device is performing a process, and after the process is completed, The peripheral device is connected again and the next process is instructed to the peripheral device.

However, since the host device does not monitor the completion of the processing of the peripheral device after disconnecting the connection of the peripheral device, the peripheral device may be used by another host device.

In order to avoid this, it is necessary to retain information for maintaining the right to control the peripheral device even after the peripheral device is disconnected. This information is called assignment information, and the circuit that holds the assignment information is called the assignment information holding circuit.

The conventional assignment information holding circuit is a circuit that simply holds assignment information.

[0007]

As described above, since the conventional assignment information holding circuit is a circuit that simply holds the assignment information, the holding of the assignment information is canceled due to the failure of the host device. When it is no longer possible, the other higher-level device cannot determine whether the high-level device is actually using the peripheral device or whether the retention of the assignment information cannot be released due to the failure of the high-level device, In addition, even when the assignment information holding circuit fails and the holding of the assignment information cannot be released from the host device, another host device asks whether the host device is actually using the peripheral device. It is not possible to determine whether the holding of the assignment information has been released due to a failure of the holding circuit.In either case, the other host device will keep the assignment information forever. There have the disadvantage that shall wait for being released, Thus, have caused a decrease in overall system performance.

Further, when the peripheral device is a magnetic disk device shared by a plurality of systems, there is a problem that all the systems are stopped.

[0009]

An assignment information holding circuit according to the present invention comprises a holding circuit for holding assignment information according to an assignment information holding command issued from a higher-level device and releasing the holding of the assignment information by an assignment information cancellation signal. ,
A time data holding circuit for holding preset time data or a time data holding circuit for inputting time data and a time data setting signal from a host device and holding the time data by the time data setting signal; A timer circuit that sets the time data held by the time data holding circuit by an information holding command, starts time counting, and outputs a time counting end signal when the set time has elapsed, and a timer circuit output from the host device. And an OR circuit that outputs the assignment information cancellation signal by a logical sum of the assignment information cancellation command and the clocking end signal.

The assignment information holding circuit of the present invention also includes
Two holding circuits that hold assignment information by an assignment information holding command issued from a higher-level device and release the holding of the assignment information by an assignment information release signal, and output signals of the two holding circuits are input to them. And a logical product circuit that outputs assignment information based on the logical product of.

[0011]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention, FIG. 2 is a block diagram showing details of a timer circuit of the embodiment of FIG. 1, and FIG. 3 is a diagram showing a normal operation of the embodiment of FIG. 4 is a timing chart showing the waveform of the signal, FIG. 4 is a timing chart showing the waveform of the signal when the host device fails and resets the assignment information within a predetermined time in the embodiment of FIG. 1, and FIG. FIG. 3 is a circuit diagram showing details of a time data holding circuit of the first example.

In FIG. 1, assignment information set signal 1
01 is input to the flip-flop circuit (F / F) 1 and the timer circuit 3. Assignment information reset signal 1
02 is input to the OR circuit 2 and the timer circuit 3. Time data 10 of output signal of time data holding circuit 4
6 is also input to the timer circuit 3. The time counting end signal 104 from the timer circuit 3 is input to the logical sum circuit 2. The OR circuit 2 uses the assignment information reset signal 102
And the clock end signal 104 are ORed, and the OR is taken to be the flip-flop circuit reset signal (F / F reset signal) 1
It is output to the flip-flop circuit (F / F) 1 as 05. F / F1 is assignment information set signal 1
01 and the F / F reset signal 105 to output the assignment information 103.

The timer circuit 3 has a structure as shown in FIG. That is, the assignment information set signal 101
Is input to the flip-flop circuit (F / F) 5 and the counter circuit 8. Assignment information reset signal 10
2 is input to flip-flop circuits (F / F) 5 and 9. The clock signal 112 of the output signal of the clock circuit 6 and the clock control signal 111 of the output signal of the flip-flop circuit (F / F) 5 are input to the AND circuit 7. Clock signal 11 of output signal of AND circuit 7
3 and time data 10 of the output signal of the time data holding circuit 4
6 is input to the counter circuit 8. Counter circuit 8
The count end signal 114 of the output signal of 1 is input to the flip-flop circuit (F / F) 9.

As shown in FIG. 6, the time data holding circuit 4 outputs time data 106 fixedly set as 8-bit data.

Next, the operation of the assignment information holding circuit configured as described above will be described with reference to FIGS. 1 to 4 and 6.

When the host device and the assignment information holding circuit are operating normally, the assignment information set signal 10
When 1 becomes low level “L” (reference numeral a in FIG. 3),
The assignment information 103 which is the output of the F / F1 becomes a high level "H" (reference numeral b). At this time, the timer circuit 3
Operates as follows to start timing.

First, the clock control signal 111 is "L".
Since it is (reference code c), even if the clock signal 112 becomes "H" (reference code d), the clock signal 113 output from the AND circuit 7 is always "L" (reference code e). Here, the assignment information set signal 101 is “L”
When it becomes (reference numeral a), the time data 106 output from the time data holding circuit 4 is set in the counter circuit 8. Also, the assignment information set signal 101 is “L”
When it becomes (reference numeral a), the F / F 5 is set and the clock control signal 111 becomes "H" (reference numeral f).
When the clock signal 112 becomes “H” (reference numeral g) while the clock control signal 111 is “H” (reference numeral f),
The clock signal 113 also becomes "H" (reference numeral h). As a result, the clock signal is supplied to the counter circuit 8, so that the counter circuit 8 starts clocking. At this time, the count end signal 114 and the time count end signal 104 are both “H” (reference symbols i and j).

If the assignment information reset signal 102 becomes "L" (reference numeral k) before the counter circuit 8 finishes measuring time, the F / F because the timing end signal 104 is "H" (reference numeral 1). The reset signal 105 becomes "L" (reference numeral m), the F / F1 is reset, and the assignment information 103 becomes "L" (reference numeral n). As a result, the timer circuit 3 operates in the following manner and stops counting time.

The assignment information reset signal 102 is "L"
When it becomes (reference numeral k), the F / F 5 is reset and the clock control signal 111 becomes "L" (reference numeral o).
At this time, the clock signal 112 is “H” (reference numeral p)
However, the clock signal 113 remains “L” (reference numeral q). As a result, the clock signal is no longer supplied to the counter circuit 8, and the counter circuit 8 stops counting time.

When the host device fails and the assignment information is not reset within a predetermined time, the operation is as follows.

The operation until the assignment information set signal 101 becomes low level "L" and the timer circuit 3 starts counting time is the same as the above case.

When a preset time elapses, the counter circuit 8 stops clocking and the count end signal 114 becomes low level "L" (reference numeral r in FIG. 4). As a result, the F / F 9 is set, and the timing end signal 104 becomes "L" (reference numeral s). At this time, since the assignment information reset signal 102 is "H" (reference symbol t), the F / F reset signal 105 becomes "L" (reference symbol u), the F / F1 is reset, and the assignment information 103 is ". L ″ (reference numeral w). That is, if the assignment information is not reset within the preset time, it is determined that the host device has failed, and the assignment information is automatically reset.

When the host device is restored, the assignment information reset signal 102 is set to "L" (reference numeral w),
The F / F 5 is reset, the clock control signal 111 becomes “L” (reference numeral x), and the clock signal 113 remains “L” (reference numeral y). Further, the F / F 9 is also reset, and the timing end signal 104 becomes "H" (reference numeral z).

FIG. 5 is a block diagram showing a second embodiment of the present invention, and FIG. 7 is a circuit diagram showing details of the time data holding circuit of the embodiment of FIG.

In the present embodiment, the time data holding circuit 10 is replaced in place of the time data holding circuit 4 of the embodiment of FIG. 1, and the configuration of the other parts is the same as the embodiment of FIG.

As shown in FIG. 7, the time data holding circuit 10 outputs the value of the time data 107 as the time data 116 when the time setting signal 108 becomes "L",
The latch circuit 11 holds the output of the time data 116 when the time setting signal 108 becomes "H".
As a result, the time measured by the timer circuit 3 can be changed from the outside. When the time data 107 and the time setting signal 108 are connected to the switch, it becomes possible to change the time measured by the timer circuit 3 by setting the switch. If connected to the host device, the host device can set an arbitrary time. The configuration and operation of the other parts are the same as in the embodiment of FIG.

FIG. 8 is a block diagram showing a third embodiment of the present invention.

In FIG. 8, assignment information set signal 1
01 is a flip-flop circuit (F / F) 21 and 2
You are typing in 2. Assignment information reset signal 102
Is also input to the F / Fs 21 and 22. F / F21
The assignment information 123 is output from the F / F 22 and the assignment information 124 is output from the F / F 22, both of which are input to the AND circuit 23. The logical product circuit 23 outputs the assignment information 125.

Next, the operation of the assignment information holding circuit configured as described above will be described.

When the assignment information reset signal 102 is inactive and the assignment information set signal 101 is activated, both the assignment information 123 and the assignment information 124 become "H". Therefore, the AND circuit 2
The output assignment information 125 of No. 3 is "H". next,
When the assignment information set signal 101 is made inactive and the assignment information reset signal 102 is made active, the assignment information 123 and the assignment information 124 are
Both are “L”. Therefore, the assignment information 125 of the output of the AND circuit 23 becomes "L".

The F / F 21 fails and the assignment information 123
Is 0, the assignment information reset signal 1
When the assignment information set signal 101 is activated when 02 is inactive, the assignment information 124 becomes “H”, but the assignment information 123 remains “L”. Therefore, the assignment information 1 of the output of the AND circuit 23
25 also remains "L".

The F / F 21 fails and the assignment information 123
If the value becomes "1", the assignment information reset signal 1
When the assignment information set signal 101 is activated when 02 is inactive, the assignment information 124 becomes “H” and the assignment information 123 remains “H”. Therefore, the assignment information 12 of the output of the AND circuit 23
5 becomes "H". When the assignment information set signal 101 is made inactive and the assignment information reset signal 102 is made active in this state, the assignment information 124 becomes "L" and the assignment information 123 remains "H". However, since the assignment information 125 is “L”,
The assignment information is reset.

The same applies when the F / F 22 fails.
That is, even if one of the two F / Fs fails, the assignment information will not remain set.

FIG. 9 is a block diagram showing a fourth embodiment of the present invention.

The embodiment shown in FIG. 9 is obtained by adding an exclusive OR circuit to the embodiment shown in FIG.

Assignment information 123 and assignment information 124 are input to the exclusive OR circuit 24, and a failure detection signal 126 is output.

Since the assignment information 123 and the assignment information 124 in the normal state are in the same state,
The failure detection signal 126 output from the exclusive OR circuit 24 is
It is always "L".

The F / F 21 fails and the assignment information 123
Is 0, the assignment information set signal 10
When 1 is activated, assignment information 1 as described above
Although 24 becomes "H", the assignment information 123 remains "L". Therefore, the assignment information 125 of the output of the AND circuit 23 also remains "L". At this time, since the input signals of the exclusive OR circuit 24 do not match, the failure detection signal 126 becomes "H", and it is reported that the circuit has a failure.

The F / F 21 fails and the assignment information 123
Is “1”, the assignment information 123 is also assigned information 1 when the assignment information 125 is set.
Since 24 also becomes "H", the failure detection signal 126 becomes "L" and the failure of the circuit cannot be detected. However, when the assignment information is reset, that is, when the assignment information reset signal 102 is activated, the assignment information 124 becomes "L", so the exclusive OR circuit 24
The input signals of No. 1 do not match, and the failure detection signal 126 becomes "H".

The same applies when the F / F 22 fails.
That is, even if one of the two F / Fs fails, the assignment information does not remain set, and it is further reported that the circuit has failed.

[0042]

As described above, the assignment information holding circuit of the present invention is a holding circuit for holding assignment information by an assignment information holding command issued from a host device and releasing the holding of assignment information by an assignment information cancellation signal. And a time data holding circuit that holds time data set in advance or a time data holding circuit that inputs time data and a time data setting signal from a higher-level device and holds the time data according to the time data setting signal, and assignment information. A timer circuit that starts timing by a holding command and outputs a timing end signal when the set time has elapsed, and a logic that outputs an assignment information cancellation signal by the logical sum of an assignment information cancellation command issued from a higher-level device and the timing end signal. By providing a sum circuit, the assignment information can be reset within a predetermined time. Automatically there is an effect that it is possible to reset the assignment information in the absence. In addition, two holding circuits that hold the assignment information by the assignment information holding command issued from the host device and release the holding of the assignment information by the assignment information release signal, and output signals of the two holding circuits are input to them. By providing the AND circuit that outputs the assignment information based on the logical product of, even if the assignment information holding circuit fails, it is possible to prevent the assignment information from being kept set.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a block diagram showing details of a timer circuit of the embodiment of FIG.

FIG. 3 is a timing chart showing the waveform of a signal during normal operation of the embodiment of FIG.

FIG. 4 is a timing chart showing a waveform of a signal when the host device fails and the assignment information is not reset within a predetermined time in the embodiment of FIG.

FIG. 5 is a block diagram showing a second embodiment of the present invention.

6 is a circuit diagram showing details of a time data holding circuit of the embodiment of FIG.

FIG. 7 is a circuit diagram showing details of a time data holding circuit of the embodiment of FIG.

FIG. 8 is a block diagram showing a third embodiment of the present invention.

FIG. 9 is a block diagram showing a fourth embodiment of the present invention.

[Explanation of symbols]

1, 5, 9, 21, 22 flip-flop circuit (F
/ F) 2 OR circuit 3 Timer circuit 4 · 10 time data holding circuit 6 Clock circuit 7 · 23 AND circuit 8 Counter circuit 24 Exclusive OR circuit 101 Assignment information set signal 102 Assignment information reset signal 103 · 123 · 124・ 125 Assignment information 104 Timing end signal 105 Flip-flop circuit reset signal (F / F
Reset signal) 106/107/116 Time data 108 Time data setting signal 111 Clock control signal 112/113 Clock signal 114 Count end signal 126 Failure detection signal

Claims (4)

[Claims] 1. A holding circuit that holds assignment information by an assignment information holding command issued from a higher-level device and releases the holding of the assignment information by an assignment information release signal, and time data that holds preset time data. A holding circuit, a timer circuit that sets the time data held by the time data holding circuit by the assignment information holding command, starts time counting, and outputs a time counting end signal when the set time has elapsed, An assignment information holding circuit, comprising: an OR circuit that outputs the assignment information cancellation signal by a logical sum of an assignment information cancellation command and the time counting end signal. 2. A holding circuit for holding assignment information by an assignment information holding command issued from a higher-level device and releasing the holding of the assignment information by an assignment-information cancellation signal, and time data and a time data setting signal from the higher-level device. A time data holding circuit that holds the time data by inputting the time data setting signal and the time data held by the time data holding circuit by the assignment information holding command are set to start time counting. A timer circuit that outputs a time counting end signal when the set time has elapsed, and a logical sum circuit that outputs the assignment information cancellation signal by a logical sum of an assignment information cancellation command issued from the host device and the time counting end signal An assignment information holding circuit comprising: 3. Two holding circuits for holding the assignment information by an assignment information holding instruction issued from a higher-level device and releasing the holding of the assignment information by an assignment information release signal, and output signals of the two holding circuits. And an AND circuit that outputs the assignment information based on the logical product of the input information and the assignment information holding circuit. 4. Two holding circuits for holding assignment information by an assignment information holding command issued from a higher-level device and releasing the holding of the assignment information by an assignment information cancellation signal, and output signals of the two holding circuits. And a fault detection circuit for inputting the output signals of the two holding circuits and outputting a fault detection signal when they do not match each other. An assignment information holding circuit characterized by: