JP3157662B2 - LSI diagnostic control circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an LSI diagnostic control circuit for diagnosing an LSI used in an information processing apparatus.

[0002]

2. Description of the Related Art When a failure occurs in an information processing apparatus, the internal state of the information processing apparatus is read to investigate the cause of the failure. For the purpose of such diagnosis, a scan method is generally used as a means for reading the state of a register in an LSI used in an information processing apparatus.

In the scan method, first, the clock supplied to the register is stopped, and then the register to be read is connected in series, and then the supply of the clock is started to read the contents of the register in series. Prior to this scan operation, the clock is stopped by one of the following two methods to maintain the internal state. The first method is
This is a method for stopping the clock supplied from outside the LSI, and the second method is a method for stopping the distribution of the clock inside the LSI.

[0004]

In the conventional LSI diagnosis means as described above, in the case of the clock stop means according to the first method, it is necessary to provide a circuit for controlling the clock outside the LSI. Therefore, there is a disadvantage that the number of parts increases. In the case of the clock stopping means according to the second method, since a circuit for controlling the clock exists inside the LSI, the clock distribution is delayed, and the difference in the clock distribution time between the LSI and other LSIs is delayed. There is a problem that (skew) increases.

[0005]

A first LSI diagnostic control circuit according to the present invention comprises: a register group which is activated by an external request or an internally generated event and holds the contents thereof; A shift register that converts an output signal of the selection circuit into serial data, a counter that controls the operation of the selection circuit, and decodes a request from the outside to hold the register group. And a control unit for canceling the operation and controlling the operation of the counter.

A second LSI diagnostic control circuit according to the present invention comprises a first register group which is activated by an external request or an internally generated event and holds the contents thereof, and a content of the first register group. A first selection circuit, a shift register that converts an output signal of the first selection circuit into serial data, a counter that controls the operation of the first selection circuit, and a second A register group, a second selection circuit that selects one of the output signal of the shift register and the output signal of the second register group, and decodes a request from the outside to hold the register group. And a control unit for canceling the operation and controlling the operations of the counter and the second selection circuit.

A third LSI diagnostic control circuit according to the present invention comprises a plurality of register groups which are activated by an external request or an internally generated event and hold their contents, and the contents of each of the plurality of register groups. A plurality of first selection circuits, a counter controlling the operation of the plurality of first selection circuits, and a second selecting one of the output signals of the plurality of first selection circuits A selection circuit, a shift register that converts an output signal of the second selection circuit into serial data, and releases a hold of the register group by decoding a request from the outside and releases the counter and the second selection. A control unit for controlling the operation of the circuit.

[0008]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention.

The LSI diagnostic control circuit shown in FIG. 1 comprises registers 11 to 14 which are activated by an external request or an internally generated event and hold their contents,
And a shift register 4 for converting an output signal of the selection circuit 2 into serial data.
And a counter 3 for controlling the operation of the selection circuit 2 and a control unit 5 for decoding the request from the outside to release the hold of the registers 11 to 14 and controlling the operation of the counter 3.
And

The control unit 5 decodes the diagnostic command 101 and outputs a register hold instruction 102 and a counter control signal 103. The registers 11 to 14 hold and release the contents of the registers 11 to 14 according to the register hold instruction 102 from the control unit 5. The register hold instruction 102 is output not only by decoding the diagnostic command 101 but also by an event occurring inside the LSI, for example, occurrence of a failure.
The control unit 5 also initializes the counter 3 by the counter control signal 103 and starts the counting operation. The selection circuit 2 selects one of the output signals of the registers 11 to 14 according to the selection signal 104 output from the counter 3. Register 11 selected by selection circuit 2
14 are converted into serial data by the shift register 4 and output as read data 105.

Thus, the contents of the registers 11 to 14 can be read out serially without stopping the clock signal for the registers 11 to 14.

FIG. 2 is a block diagram showing a second embodiment of the present invention.

The LSI diagnostic control circuit shown in FIG. 2 includes registers 11 to 14 which are activated by an external request or an internally generated event and hold the contents thereof,
And a shift register 4 for converting an output signal of the selection circuit 2 into serial data.
A counter 3 for controlling the operation of the selection circuit 2, registers 61 to 63 through a scan path, and a shift register 4
And a selection circuit 7 for selecting one of the output signals of the registers 61 to 63, and decoding the request from the outside to release the hold of the registers 11 to 14,
And a control unit 51 for controlling operations of the counter 3 and the selection circuit 7.

The control unit 51 decodes the diagnostic command 101 and outputs a register hold instruction 102, a counter control signal 103, and a selection signal 109. The registers 11 to 14 hold or release the contents of the registers 11 to 14 in response to a register hold instruction 102 from the control unit 51. The register hold instruction 102 is output not only by decoding the diagnostic command 101 but also by an event that occurs inside the LSI, for example, when a failure occurs. The control unit 51 also initializes the counter 3 by the counter control signal 103 and starts the counting operation. The selection circuit 2 selects one of the output signals of the registers 11 to 14 according to the selection signal 104 output from the counter 3. The output signals of the registers 11 to 14 selected by the selection circuit 2 are converted into serial data by the shift register 4 and output to the selection circuit 7 as the shift register output 108. The selection circuit 7 is controlled so as to select and output the shift register output 108 by the selection signal 109 from the control unit 51, so that the contents of the registers 11 to 14 are serially output as the read data 105.

The diagnostic command 101 causes the register 61
When the reading of instructions from # 63 to # 63 is instructed, the selection circuit 7 selects the scan output 107 from the registers 61 to 63 to which the scan input 106 is input by the selection signal 109 from the control unit 51, and outputs it as read data 105 I do.

Thus, without stopping the clock signal for the registers 11 to 14, the contents of the registers 11 to 14 having no scan path and the contents of the registers 61 to 63 passing through the scan path can be read from the common read data 105. It becomes possible to read.

FIG. 3 is a block diagram showing a third embodiment of the present invention.

The LSI diagnostic control circuit shown in FIG. 3 is activated by an external request or an internally generated event, and stores registers 11 to 14 and register 1
5-18, a selection circuit 21 for selecting the contents of the registers 11-14, a selection circuit 22 for selecting the contents of the registers 15-18, and one of the output signals of the selection circuits 21 or 22 is selected. A selection circuit 8 and a shift register 4 for converting an output signal of the selection circuit 8 into serial data
And a counter 3 for controlling the operations of the selection circuits 21 and 22;
14 and a control unit 52 for releasing the hold of the registers 15 to 18 and controlling the operations of the counter 3 and the selection circuit 8.

The diagnostic command 101 causes the register 11
When the reading of .about.14 is instructed, the control unit 52 initializes the counter 3 by the counter control signal 103 and starts the counting operation. The selection circuit 21 selects one of the output signals of the registers 11 to 14 according to the selection signal 104 output from the counter 3 and outputs the selected signal as the selection circuit output 110 to the selection circuit 8. The selection circuit 8 outputs the selection circuit output 1 according to the selection signal 112 from the control unit 52.
10 is sent to the shift register 4. The shift register 4 converts it into serial data and outputs it as read data 105.

The diagnostic command 101 causes the register 15
The same operation is performed when the reading of .about.18 is instructed.
That is, the control unit 52 initializes the counter 3 by the counter control signal 103 and starts the counting operation. The selection circuit 22 selects the selection signal 1 output from the counter 3.
In step 04, any one of the output signals of the registers 15 to 18 is selected and output to the selection circuit 8 as a selection circuit output 111. The selection circuit 8 selects the selection circuit output 111 based on a selection signal 112 from the control unit 52 and sends the selection circuit output 111 to the shift register 4. The shift register 4 converts it into serial data and outputs it as read data 105.

Thus, the contents of the registers 11 to 14 or the registers 15 to 18 can be selectively read from the read data 105 without stopping the clock signal for the registers 11 to 18.

[0023]

As described above, the LSI diagnostic control circuit according to the present invention includes a register group that is activated by an external request or an internally generated event and holds the contents of the register group and the register group. Providing a selection circuit for selecting and a shift register for converting an output signal of the selection circuit into serial data has an effect that the contents of the register can be read without stopping a clock signal to the register. Therefore, there is no need to provide a circuit for controlling the clock, and there is no delay in clock distribution.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a block diagram showing a second embodiment of the present invention.

FIG. 3 is a block diagram showing a third embodiment of the present invention.

[Explanation of symbols]

 2.7.7.21.22 selection circuit 3 counter 4 shift register 5.51.52 control unit 11-18.61-63 register 101 diagnostic command 102 register hold instruction 103 counter control signal 104.109.112 selection signal 105 Read data 106 Scan input 107 Scan output 108 Shift register output 110/111 Selector output

Claims (3)

(57) [Claims] 1. A register group which is activated by an external request or an internally generated event and retains the contents of the register group, a selection circuit for selecting the contents of the register group, and an output signal of the selection circuit which outputs serial data. A shift register, a counter for controlling the operation of the selection circuit, and a control unit for decoding the external request, releasing the hold of the register group, and controlling the operation of the counter. An LSI diagnostic control circuit characterized in that: 2. A first register group which is activated by an external request or an internally generated event and holds the contents thereof, a first selection circuit which selects the contents of the first register group, A shift register that converts an output signal of the first selection circuit into serial data, a counter that controls the operation of the first selection circuit, a second register group that passes through a scan path, and an output signal of the shift register Or a second selection circuit that selects one of the output signals of the second register group, and decodes the external request to release the hold of the register group, and releases the counter and the second An LSI diagnostic control circuit comprising: a control unit that controls an operation of a selection circuit. 3. A plurality of register groups which are activated by an external request or an internally generated event and hold the contents thereof, and a plurality of first selection circuits which select respective contents of the plurality of register groups. A counter that controls the operation of the plurality of first selection circuits, a second selection circuit that selects one of the output signals of the plurality of first selection circuits, and the second selection circuit A shift register that converts the output signal of the register into serial data, and a control unit that decodes the external request to release the hold of the register group and controls the operation of the counter and the second selection circuit. An LSI diagnostic control circuit, comprising: