JPS6057455A - Memory access controller - Google Patents

Abstract

PURPOSE:To reduce the effect to the system clock cycle owing to an increase of memories by using a means which selects and delivers the duplicate access requests to plural operation state checking circuits and memories. CONSTITUTION:Operation state checking circuits 220, 221, etc. supply access requests CPU0 and CPU1 via memory means 210 and 211. These requests are collated with operation state registers 250, 252, etc. Then an access request is delivered if the actuation is possible. A duplication preventing circuits 300 uses the plural access requests given from means 210 and 211 as inputs to select either one of both access requests in response to the prescribed priority order in case the memories designated by said inputs are coincident and duplicated with each other. In such a way, the effect to the system clock cycle due to an increase of memories can be reduced with use of operation state checking circuits and duplication a preventing circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical field to which the invention pertains] The present invention relates to a storage control device used in an information processing device, and in particular, to a storage control device used in an information processing device, and in particular to an access control device when a plurality of access request devices make access requests to a plurality of storage devices. The present invention relates to a memory access control device that performs control.

[Prior art]

Generally, in an information processing system, a plurality of central processing units and storage devices are used in parallel to improve information processing speed. For this reason, memory access control devices that control access from central processing units to storage devices have become extremely complex.

FIG. 1 shows an example of the configuration of an information processing system to which the present invention is applied. In the figure, two central processing units 1. A storage control device 2 and a plurality of storage devices 3 operate in synchronization with a system clock, and access requests from a central processing unit engineer are sent to the storage device 3 via the storage control device 2.

The storage control device 2 includes a memory access control device 21 and a plurality of selection circuits 22 corresponding to the storage devices 3. The memory access control device 21 receives access requests from the two central processing units 1, checks whether these access requests can be operated on the storage device 3, and checks if there are duplicate access requests to the same storage device. Performs priority selection control, etc.

The selection circuit 22 selectively selects access requests from the two central processing units 1 based on instructions from the access control device 21 and sends the selected access requests to the corresponding storage device 3. In order to improve the processing speed of the information processing system as described above, the number of central processing units 1 and storage devices 3 is increased and/or
If the stem clock cycle is shortened, the operating speed of the memory access control device 21 becomes a problem.

FIG. 2 is a block diagram showing an example of a conventional memory access control device compatible with the information processing system shown in FIG.

In FIG. 2, storage means 210 and 211 are registers that each receive access requests cpo and CPI from two central processing units in a one-to-one correspondence, and are updated in synchronization with the system clock. Operating state inspection circuits 220 , 221 .

222'' and 223 are respectively provided corresponding to a plurality of storage devices, and access requests cpo and CPI from the central processing unit are inputted via the storage means 210 and 211, and are specified in the inputted access requests. Operation status register 250 indicating the storage device and the operation status of each storage device
．． 251, 252, and 253, respectively.
If the requested storage device l is operational, access request cp.

and the output corresponding to CPI is set to °1".

The priority circuits 230, 231, 232, and 233 are.

Each is provided corresponding to the operating state inspection circuit.

Operating state inspection circuits 220, 221, 222, 22
2 corresponding to the access request CPO and CPI from 3.
When both input signals are "1", one of them is selected according to a predetermined priority order, and the memory access signals MOO and o- corresponding to the selected access request are input. yt O1.

MIO and Ml 1 , M2O, t: and Ml1. M
One of 2O and 43i is set to 'l'.Memory access signals MOD and MOI, MIO and Mll.

M2O and Ml1. M2O and M31 are memory access signals MOO, MIO, and M2O, respectively, corresponding to four storage devices.

M2O becomes '°1' when an operation is executed on the storage device specified by the access request cpo.Furthermore, the memory access signals MOI and Mll.

Ml1. M31 specifies that when an operation is to be performed on a storage device specified by the access request CPI, one of the following is l#.
become.

The OR circuits 240, 241, 242, 243 are.

Memory access signal MOO corresponding to each storage device
and MOI, Ml, 0 and Ml 1 , M2O and Ml1゜M
The logical sum of 2O and M31 is performed, and if the output is 1'', the corresponding operating status register 250°251.25
Set °'1" to 2,253, respectively. Also,
The NOR circuit 260 performs the logical sum of the memory access signals M00°MIO2M201M30 corresponding to the access request CPO, and outputs the negative value of the result. The NOR circuit 261 provides NOR for memory access signals MO1, MIL, Ml1, and M31 corresponding to the access request CPI.
It performs the same thing as the OR circuit 260. AND circuit 270
teeth.

The access request cpo via the storage means 210 and the output of the NOR circuit 260 are ANDed. That is, this AN
Although the D circuit 270 has an access request CPO at the output of the storage means 210, the operation state inspection circuits 220, 221, 222° 223 and the priority circuit 23
0.231.232233 when the operation for the storage device cannot be started, the value becomes 1n, and the storage means 2
The contents of 10 are held so that the above-described series of operations for the same access request can be executed at the next system clock. AND circuit 271 access request CPI
◇ Incidentally, in the conventional memory access control device shown in FIG. 2 described above, in order to receive access requests from the central processing unit every system clock cycle, the
Operating status inspection circuit, priority circuit, NOR circuit and AN
The problem is the delay time d of the path that passes through the D circuit and controls whether or not to retain the contents of the storage means. For example, the storage means 21o, the operating state inspection circuit 220. Priority circuit 230.
The delay time of the path that holds the contents of the storage means 210 via the NOR circuit 260 and the AND circuit 270 must be within the system clock cycle.

However, as the processing speed of information processing systems improves, the number of storage devices in use, which operate at relatively slow speeds, increases, and as a result, the delay time of the path increases, and the system clock cycle increases. The lead line is in a very difficult condition.

[Object of the Invention] The object of the present invention is to provide a plurality of storage devices that check whether or not a corresponding one of a plurality of storage devices is operational in response to access requests from a plurality of central processing units. By configuring the operation state inspection circuit and the means for selecting and outputting any one access request when the plurality of access requests overlap to the same storage device to be able to operate in parallel. The object of the present invention is to provide a memory access control device which eliminates the above-mentioned drawbacks and in particular minimizes the influence on the system clock cycle due to an increase in the number of storage devices used.

[Structure of the invention]

The present invention provides a memory access control device that controls access requests from a plurality of access request devices to a plurality of storage devices, including a plurality of operation state registers each storing an operation state of the plurality of storage devices; a plurality of storage means provided correspondingly to the plurality of access requesting devices and storing access requests from the corresponding access requesting devices; a plurality of operation state inspection circuits that check whether the requested storage device is operable or not and output the access request if the storage device is operable; a plurality of logic utilization means that take a logical sum corresponding to each access requesting device, and a plurality of logical means that perform logical summation based on a predetermined priority order when access requests from the plurality of storage means overlap with the same storage device. The present invention is characterized in that it includes a plurality of inhibiting circuits that inhibit the output of the logical sum means using the plurality of inhibiting signals.

[Embodiments of the invention]

Next, two aspects of the present invention will be described in detail with reference to the drawings.

FIG. 3 is a block diagram showing an embodiment of the memory access control device of the present invention.

In FIG. 3, circuits with the same reference numbers and reference numbers as the conventional memory access control device shown in FIG.
The circuits and signals have similar functions to conventionally used circuits and signals. Operating state inspection circuit 220, 221, 222,
223 is an access request cp from two central processing units.
o, c, and pl are stored in storage means 210 and 21, respectively.
1 through the access request and operating status register 25o.

251 + '252.253 respectively.

If the access request is operational, the access request is output to the corresponding storage device.

The duplication prevention circuit 300 receives a plurality of access requests from the storage means 210 and 211 as input.

The storage devices specified in the plurality of access requests match,
That is, when there are duplicate access requests to the same storage device, one of the access requests is selected according to a predetermined priority order, and a deterrent signal is output to suppress the other of the duplicate access requests.

The logical sum means 26σ and 261' are N in FIG.
It operates almost the same as the OR circuits 260 and 261, except that the output is "true".The outputs of the OR circuits 26σ and 261' indicate that the access requests cpo and CPI can be operated on the storage device, respectively. If the access request cpo and CPI specify the same storage device, both outputs become 1.A.
The ND circuits 310 and 311 are connected to the operating state inspection circuit 22.
The output corresponding to the access requests CPO and CPl from 0 is suppressed according to the corresponding suppression signal from the double duplication prevention circuit 300, and the access request cp is generated.

Even if the same storage device is designated by the memory access signals MOO and M'01, only one of the memory access signals MOO and M'01 is set to '1#'.

Similarly, AND circuits 312 and 313, 314, 315, 316 and 317, respectively,
It operates similarly to AND circuits 310 and 3tt, and outputs memory access signals M10, Mll, and M2O, respectively.
and M21. Only one of M2O and M31 is output. In addition, the suppression circuits 320 and 321
inhibits the corresponding outputs of the inputs from the OR means 260' and 261' according to the inhibition signals from the two duplication prevention circuits 300, and outputs the corresponding outputs from the AND circuits 270 and 261'.
Output to 71.

The duplication prevention circuit 300 has a circuit configuration as shown in FIG. 4, for example, when there are two central processing units as access requesting devices. The access request CPO from the storage means 210 in FIG. 3 corresponds to the set consisting of the request signal ABO, storage address signals AOO and AIO in FIG. 4, and similarly the access request cpf from the storage means 211 is
This corresponds to the set consisting of the request signal AEI, storage device address signals AOI and All in FIG.

In FIG. 4, exclusive OR circuits 401 and 402
sets the output to 1# when the storage device address signals AOO and AOl and AIO and All match, respectively. AND circuit 403 outputs "IN" when both exclusive OR circuits 401 and 402 are "1" and both request signals AEO and AEI are "1#". Therefore, when the output of the AND circuit 403 is 1#, the third
This figure shows a case where access requests from storage means 210 and 211 overlap to the same storage device. N
AND circuits 4o4 and 4o5 are AND circuit 403
When the output is "'1", the priority signal pc as before
According to the lower priority inhibit signals APO and AP
Which one of I makes one °'0''.

The NOT circuit 406 is used to create an inverted signal of the priority signal 1)C.

FIG. 5 shows a case where the number of access requests of the duplication prevention circuit 300 in FIG.
An example of the circuit configuration for a stand is shown.

In FIG. 5, circuits and signals with the same reference numbers and reference numbers as in FIG. 4 have the same functions as the circuits and signals shown in FIG. Also.

AE2. The inhibit signal AP2 is formed from the storage device address signals AO2 and A12, and the inhibit signal AP2 is the access request CP.
2' is shown. Note that the duplication prevention circuit 5 for access requests c p o' and CPf
0. Duplication prevention circuit 51 for access requests CPf and CP2'. Access requests c p o' and CP 2
The duplication prevention circuits 52 for ' have the same circuit configurations as the duplication prevention circuits 300 in FIG. 4, so the explanation will be omitted.

The priority signal PCOI is the access request c, p o'
The priority order signal PC12 indicates the priority order of and cpf.

The priority order signal PC20 indicates the priority order of access requests cpf and CP2'.
and the priority order of each.

NAND circuits 500, 501, and 502 correspond to two access requests with low priority when all of the access requests c p o', c p 1', and c p 2' overlap in the same storage device. Set the inhibition signal to "o".

The priority signals PC30, PC31, and PC32 are access x 2 pieces are given l″ and 1.N
AND circuit 510 + 511 + 512.

Duplication prevention circuit 5 when two access requests overlap among access requests CPO', CI)1', and C))2'
The output signal from 0.51.52 is ANDed with the output from the NAND circuits 500, 501 and 502 when three access requests overlap, and the negative output is the inhibition signal A.
PO, API, AI)2.

Hereinafter, the principle is the same even when there are four or more access requesting devices.

In the memory access control device showing one embodiment of the present invention shown in FIG. 3 described above, the storage means 21. '0 and 21゛・
Operation status inspection circuits 220 and 2 that inspect whether the plurality of access requests sent through 7 through 1 can be operated on the storage device.
21, 222, 223, and a duplication prevention circuit 300 that selects any one of the duplicate access requests and suppresses other access requests when a plurality of access requests overlap in the same storage device. operate in parallel. Therefore, the path 71 determines whether or not the storage means 210 and 211 are to be stored or not, depending on whether or not an access request from the storage means 210 and 211 is started in the storage device.
For example, storage means 210. OR means 260', NA
There is no need for a priority circuit in the path leading to the storage means 210 via the ND circuit 320 and the AND circuit 270, and the delay time of the path can be significantly reduced.

Note that there are two routes for determining whether or not to store the memory means 210 and 211, for example, a route leading to the memory means 210 via the memory means 210, the duplication prevention circuit 300, the NAND circuit 320°, and the AND circuit 270. but,
Since this route has fewer physical quantities than the above-mentioned routes, it can be integrated into a circuit all at once, and therefore the delay time due to wiring between circuits can be extremely reduced, resulting in a small delay time.

□In the above description, the memory access control device of the present invention has been described as controlling access to a plurality of storage devices, but it is assumed that the memory access control device of the present invention controls access to a plurality of storage devices. In a storage device having a common control circuit, it can be easily inferred that the above-described access control can be performed by replacing the storage device with the storage circuit and replacing the memory access control device with the control circuit.

〔Effect of the invention〕

As described above, the present invention includes an operation state inspection circuit that checks whether a plurality of access requests from a plurality of access request devices are operable in a storage device; In parallel with a duplication prevention circuit that outputs a suppression signal that suppresses the lowest priority access request among the duplicated access requests when duplicates occur in the storage device, and does not suppress only the one access request with the highest priority. By configuring the system so that it can operate in a timely manner, the delay time required for access control can be significantly reduced, and the impact on the system clock cycle due to an increase in the number of access requesting devices and storage devices in use can be greatly reduced. This has the effect of significantly increasing the processing speed of the system.

Remaining days below

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a configuration example of an information processing system, FIG. 2 is a block diagram showing a conventional memory access control device, FIG. 3 is a program diagram showing an embodiment of the present invention, and FIG. The figure is a circuit diagram showing an example of the structure of the duplication prevention circuit shown in FIG. 3, and FIG. 5 is a circuit diagram showing an example of the structure when the duplication prevention circuit shown in FIG. 3 is applied to three access requests. It is a diagram. 1...Central processing unit, 2...Storage control device, 3...
-Storage device, 21...Memory access control device, 22
...Selection circuit, 210.211...Storage means, 22
0 to 223... Operating state inspection circuit, 230 to 233.
...Priority circuit, 250-253...Operating status renostar. 300... Duplication prevention circuit, 401.402... Exclusive OR circuit.

Claims (1)

[Scope of Claims] 1. In a memory access control device that controls access requests from a plurality of access request devices to a plurality of storage devices, a plurality of operations of storing the operating states of the plurality of storage devices, respectively. a status reno star, a plurality of storage means provided corresponding to each of the plurality of access request devices and storing access requests from the corresponding obscene devices; a plurality of operation state inspection circuits that check whether the requested storage device is operable by comparing the contents of the operation state register and output the access request if the storage device is operable; a plurality of OR means for logically ORing access requests from the plurality of operation state inspection circuits corresponding to the access requesting devices, and access requests from the plurality of storage means duplicated to the same storage device. a duplication prevention circuit that outputs a plurality of deterrence signals so as to select one of the access requests based on a predetermined priority order when the plurality of access requests is selected; A memory access control device comprising: a plurality of inhibiting circuits that inhibit according to the following.