JPH01240938A - Data read back method - Google Patents

Abstract

PURPOSE:To simplify constitution and to prevent a load from being applied on a CPU by storing command data in each memory area at the time of writing each command data and reading each command data by designating each memory area at the time of reading back. CONSTITUTION:In case of performing write on a control register 22-1, a RAM 27 receives a write signal and the command data passing a data bus 21, and stores the command data in the memory area corresponding to the control register 22-1. Next, in case of reading back the command data in the control register 22-1, stored command data is read out from the memory area of the control register 22-1 by the input of a read signal by the RAM 27, and the command data is sent to the CPU 20 via the data bus 21. In such a way, it is possible to make a three-state buffer unnecessary, and the number of out of the data bus 21 can be also reduced. Also, since read back can be performed only by designating an address to the RAM 27 by the CPU 20, the load on the CPU 20 can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a data readback method for reading back command data written in, for example, a latch type control register.

(Prior art) Each command data issued from the CPU <central processing @II) to each device, for example, when issuing command data for permission of printing operation to a printing machine as a device, this command data is stored in a latch type write-only control register. write to,
This control register is given to the printing machine. If the printing operation is not permitted, command data for not allowing the printing operation is written in the control register.

By the way, each latch type controller register used to issue such command data to each device is write-only and cannot be directly read. Therefore, when reading, a buffer is connected to the output terminal of the controller register, and the CPU
Reading is performed at FIG. 3 is a circuit configuration diagram when writing and reading command data to and from such a control register. A timing control circuit 4 is connected to the CPU via an address bus 2 and a control bus 3. Each control register 6-1 is connected to this timing logic circuit 4 via a write line 5.
5-n are commonly connected, and the three-state buffers 8-1 to B-n are also commonly connected via lead wires 7. And each control register 6-1 to 5-n
The output terminals of each are 3-state buffers 8-1 to 8.
- connected to n. The CPU also controls each control register 6-1 to 5-n and each control register 3 via the data bus 9.
It is connected to state buffers 8-1 to f3-n.

In addition, as mentioned above, each control register 6-1 to 6-5-
Devices 10-1 to 10-1 are connected to each of n.

For example, when writing command data to the control register 6-1, the CPU 1 sends an address specifying the control register 6-1 to the address bus 2, sends a write signal to the control bus 3, and then sends a write signal to the data bus 3. Send command data to 9. This results in
The control register 6-1 receives its own address, receives a write signal, receives command data coming through the data bus 9, and writes it internally. When the command data is written in this way, the control register 6-1 gives this command data to the device 1o-1 and also sends it to each of the three-state buffers 8-1 to F3-n.

On the other hand, the CPU 1 controls each control register 6-1 to 6-5-.
The command data is read back in order to confirm the contents of the command data written to n and to determine whether the command data with the same contents as before has been written. For example, when reading back command data from the control register 6-1, the CPU sends the address of the 3-state buffer 8-1 to the address bus 2 and also sends a read signal to the control bus 3. Then, when the 3-state buffer 8-7 receives its own address and also receives the read signal, the control register 6-1
The command data received from the CPU is sent through the data bus 9.
Give it to i. The CPU 1 then determines the contents of the command data written into the control register 6-1 from this command data.

However, with the above configuration, 3-state buffers 8-1 to B-n are connected to control registers 6-1 to 6-n, respectively, so the number of connected control registers 6-1 to 5-n is limited. As the number of 3-state buffers 8-1 to B-n increases, the number of connected 3-state buffers 8-1 to B-n also increases. Therefore, the area occupied by the 3-state buffers 8-1 to 8-n becomes larger and the area occupied by the 3-state buffers 8-1 to 8-n increases.
-The number of outs of data bus 9 to n increases. moreover,
In addition to this, power consumption increases and the patterns formed on the circuit board become more complex.

(Problems to be Solved by the Invention) If the readback function is provided as described above, the number of connected 3-state buffers 8-1 to B-n will increase, resulting in an increase in the size of the entire system.

Therefore, an object of the present invention is to provide a data readback method that has a simple configuration and does not place a burden on the CPLI.

[Structure of the Invention] (Means and Effects for Solving the Problems) The present invention provides a control register for each write-only control register that gives each command data written by a central processing unit to each device. In the data readback method of reading back each specified data, when writing each command data, these command data are stored in each memory area corresponding to the address of each control register to be written, and each memory area is specified at the time of readback. This data readback method attempts to achieve the above object by reading each command data written in each control register.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a data readback device to which the data readback method is applied. A plurality of write-only control registers 22-1 to 22-n are connected to the CPU 20 via a data bus 21. Also, CPU2
0 is connected to a timing logic circuit 25 via an address bus 23 and a control bus 24, and each of the control registers 22-1 to 22-n is further connected to this timing logic circuit 25 via a write line 26. .

Now, a RAM (Random Access Memory) 27 is connected to the CPU 20 via the data bus 21 and address bus 23. The RAM 27 and the timing logic circuit 25 are connected by a write line 26 and a lead line 28. This RAM 27 includes each control register 22-1 to 22-2 as shown in FIG.
Each memory area corresponding to each address of 2-n is formed, and command data is stored in each of these memory areas.

Next, a data readback operation in the device configured as described above will be explained.

First, the writing operation of command data will be explained. For example, when writing to the control register 22-1, the CPU 20 sends the address of the control register 22-1 to the address bus, sends a write signal to the control bus 24, and then sends command data to the data bus 21. do. Thereby, the timing logic circuit 25 decodes the input address and write signal and sends the write signal to the write line 26.

Note that this write signal is sent to the control register 22-1.
only. As a result, only the control register 22-1 operates, and the control register 22-1 receives the command data coming through the data bus 21, writes it internally, and provides this command data to the device 10-1.

On the other hand, since the write signal sent from the timing logic circuit 25 at this time is also sent to the RAM 27,
This RAM 27 receives a write signal and command data coming through the data bus 21, and stores this command data in a memory area corresponding to the control register 22-1.

Next, the readback effect will be explained. For example, when reading back command data from the control register 22-1, the CPU 20 sends the address of the control register 22-1 to the address bus 23 and a read signal to the control bus 24. Thereby, the timing logic circuit 25 decodes the address and read signal and sends the read signal to the lead line 28. In the RAM 27, the command data stored in the memory area of the control register 22-1 is read by inputting the read signal, and this command data is sent to the CPU 20 through the data bus 21. Here, the CPU 20 determines the command data written to the control register 22-1 from the read command data.

In this way, in the above embodiment, when each command data is written, these command data are stored in each memory area corresponding to the address of each control register 22-1 to 22-n to be written, and when read back, each memory area is stored. By specifying the area, each control register 22-1 to 22-
nk: Since each written command data is read, there is no need for a 3-state buffer at all, so space on the circuit board can be used more effectively, and pattern formation on the circuit board is simplified. . Moreover, data bus 2
The number of 1 outs can also be reduced. Also, CP (J20 is RAM
Since readback can be performed simply by specifying an address to CPLI 27, the load on the CPLI 20 is small. Further, bit operations and logical operations can be performed on each control register 22-1 to 22-n, further reducing the burden.

Note that the present invention is not limited to the above-mentioned embodiment, and may be modified without departing from the spirit thereof. For example, the present invention is applicable not only to the latch type control registers 22-1 to 22-1 but also to other types of control registers.

[Effects of the Invention] As described in detail above, according to the present invention, it is possible to provide a data readback method that has a simple configuration and does not place a burden on the CPU.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram showing an embodiment of a data readback device to which a data readback method according to the present invention is applied;
FIG. 2 is a schematic diagram of the inside of the RAM in the same device, and FIG. 3 is a diagram for explaining the prior art. 20...CPU, 21...Data bus, 22-1~
22-n...Control register, 23...Address bus, 24...Control bus, 25...Timing logic circuit, 26...Write line, 27...
・RAM, 28...Lead wire. Applicant's agent Patent attorney Takeshi Suzue Sangyo 1 Figure 2

Claims (1)

[Claims] In a data readback method for reading back each specified data written in each write-only control register that provides each command data written by a central processing unit to each device, writing each command data. At times, these command data are stored in each memory area corresponding to the address of each of the control registers to be written, and at the time of readback, each of the memory areas is specified and each command data written in each of the control registers is read. A data readback method characterized by: