JPS61237158A - Shared memory device - Google Patents

Abstract

PURPOSE:To prevent the drop of a throughput at competition time of accesses by providing a data memory and a flag memory on each processor, and providing a duplicator for copying a data which is written newly in the data memory, to other data memory. CONSTITUTION:A shared memory device 5 is constituted of data areas 6a, 6b and 6c having the same internal structure, which is provided on each processor 2, 3 and 4, respectively, and a duplicator 7 for copying a data. The areas 6a, 6b and 6c are provided with data memories 8a, 8b and 8c for storing a data, and flag memories 9a, 9b and 9c for storing a write address of the data, respectively. The duplicator 7 checks successively and cylindrically a set state of each flag of the flag memory at every address, and when a new data is written in one of them, this duplicator transfers and writes the written new data to the same address position of the data memory of other processor. In such a way, the drop of a throughput of the time of an access competition can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a random access memory device used as a storage device for electronic computers, and more particularly to a shared memory device accessed by a plurality of processors.

BACKGROUND OF THE INVENTION The structure of a conventional shared memory device of this type is shown in FIG. A conventional shared memory device has a shared memory 1 that is considered to be one physically and logically, and a plurality of processors 2, 3, 4 are commonly connected to this shared memory 1. The configuration was such that each of the processors 2, 3, and 4 could access the system.

Problems to be Solved by the Invention When using the conventional shared memory device as described above, when accesses from the respective processors 2, 3 and 4 to the shared memory 1 overlap, simultaneous access is not possible, so the priority is It was necessary to allow access to the highest processor and prohibit access to other processors. For this reason, in conventional shared memory devices, throughput has been reduced due to access contention.

The present invention has been made in order to solve the above problems, and provides a shared memory device of this type that does not require access waiting even when accesses from multiple processors compete, and does not reduce throughput. .

Means for Solving the Problems As described in the claims, the present invention provides a shared memory device that is randomly accessed by a plurality of processors, including a data memory for storing data and a single address for the address of the data memory. Each processor is provided with a flag memory that corresponds to one-to-one correspondence and sets a flag at the address location when new data is written to the data memory, and each processor only writes data to the corresponding data memory. In addition to being configured to be accessible, the set state of each flag in each flag memory is cyclically checked for each address, and when new data is written to any data memory, it is written to the data memory. This problem is solved by providing one dusolicator for data copying, which transfers and writes new data to the same address location in the data memory of another processor.

Function: Each processor accesses its corresponding data memory and reads and writes required data from each data memory. Therefore, each data memory functions as a local memory for each processor, and even if access from each processor overlaps, it can be accessed freely without any restrictions.

On the other hand, when any processor writes new data to a predetermined address in the corresponding data memory, the flag at the corresponding address in the flag memory provided as a pair with the data memory is set to 1''. The dusolicator checks this flag 11'' to detect the address, reads new data at the address location in the data memory, transfers the data to the same address location in another data memory, and transfers the same data to the same address location. Write.

In this way, when new data is written to any data memory, it is copied by the dusolicator to the same address in the other data memory, and the data content of each data memory is always maintained the same.

Therefore, although there are physically a plurality of data memories provided for each processor, logically they function as one data memory having the same data content. Therefore, even if the accesses of the respective processors overlap, the corresponding data memories can be accessed simultaneously, and there is no reduction in throughput due to access contention as in conventional shared memory devices.

Embodiment FIG. 1 is a block diagram showing the configuration of a shared memory device according to the present invention.
, 3. Data area 6 with the same internal structure provided every 4
a, 6b, 6c, and a dusolicator 7 for data transfer. Data areas 5a, 6b, and 5c are each
Data memo for data storage! Flag memo to store J8a, 8b, 8c and data write address! J9a
, 9b.

It is equipped with 9c. In addition, each data memo IJ 8 a
.

The same data is stored at the same address in each of 8b and 8c.

FIG. 2 shows a specific example of the internal structure of the data area 6a, representing the data areas 6a, 6b, and 5c. The other data areas 6b and 6c also have exactly the same configuration. In the figure, 8a is the data memo for storing the data mentioned above! j, 9a
is also the flag memory mentioned above. 10a, 11a
12a is an address multiplexer that selectively connects the address signals input to data memory 8a and flag memory 9a to the local bus side (7' processor 2 side) and the common bus side (dusolicator 7 side); 12a is a data memory I;
A data multiplexer 13a is a control circuit for selectively connecting the data input and output to the J8a to the local bus side and the common bus side.

The flag memory 9a contains the same number of flags as the addresses of the data memory 8a, and each flag is associated with each address of the data memory 8a on a one-to-one basis. The configuration is such that the corresponding flag becomes 1' when new data is written.

The dusolicator 7 has data memories 8a and 8b.

When new data is written to any of the data memories 8c, this is written to the flag memo J9a.

It is detected that the flag of the corresponding address of 9b, 9c becomes 11", and the new data is transferred to another data memory, copied and written to the same address position, and the data of each data memory 8a, 8b, 8c is The data content is always kept the same.

This dusolicator 7 is always a flag memo, except when writing from the local bus side. j9a.

9b and 9c, and checks each flag cyclically.

In the above configuration, when the processor 2 accesses the data area 6a to read data, the control circuit 13a issues a read command to the data memory 8a on the condition that the common bus (dusolicator 7) is not being accessed. . This causes the read address to be read via the address multiplexer 10a.

The data stored at the address is read out and output to the processor 2 through the data multiplexer 12a.

FIG. 6 shows a flowchart of the above operation.

The data read operation described above is performed by each processor 2.3.4.
The processing is executed independently for each corresponding data area 5a+6b+60. Therefore, each processor can access the corresponding data memory regardless of the presence or absence of access requests from other processors, and there is no reduction in throughput due to access contention.
A write operation when a new data write request is received from the processor 2 and a data duplication (data transfer) operation of the new data by the dusolicator 7 will be described.

Now, when there is a write request for new data from the processor 2, the control circuit 13a of the data area 6a corresponding to the processor 2 gives a write command to the data memo J8a in accordance with the write request from the processor 2. As a result, the write address is input through the address multiplexer 10a, and new data sent through the data multiplexer 12a is written into the corresponding address position of the data memory 8a. At the same time as this write operation, the control circuit 1
3a switches the address multiplexer 11a from the common bus side to the local bus side, sends the write address sent from the processor 2 to the flag memory 9a through the address multiplexer 11a, selects the flag at the write address position, and sets the flag. Set to 1'. With the above steps, data writing from the processor 2 to the data area 6a and setting of the flag memory are completed.

When the above data writing and flag setting are completed, the control circuit 13a connects the address multi-layer sensor 11a to the dusolicator T side (common bus side) again. As shown in FIG. 3, the dusolicator T includes an address 1 counter 14 and a control circuit 15 therein, and sequentially and cyclically outputs a flag address signal specifying a flag position. Therefore, each data area 6 a + 6 b, 6
Each address multizolexer 11a in c.

11b and 11c receive the flag address signal and write each flag memo! j All flags in 9a, 9b, and 9c are cyclically selected one after another in the order of their addresses.

As a result, each data area 6a + 5b, 5c sends the set state of each flag to ``1'' or ``10'' as a flag signal to the duplicator 7 every time a flag is selected, and the duplicator 7 transmits this to the fourth Check the circuit as shown in the figure.

Now, when the flag address output by the address counter 14 in FIG. 3 reaches the address position where new data has been written by the processor 2, the flag signal output from the data area 6a to which the new data has been written becomes 11#. Nasi,
The flag signals output from the other data areas 6b and 6c to which no data has been written are 10'. As a result, in FIG. 4, the output of the AND gate 21 changes from 11# to 0#, and it is detected that new data has been written.
The signal is output as a dusolation (transfer) request signal. At the same time, the output of the AND gate 16 is '1',
This becomes the output 10' of the AND gates 17 and 18, indicating that data should be read from the data area 6a to which the AND gate 16 provides the output 11'.

The dusolicator 7 transmits the current flag address to each data area 5a, 5 via the common bus according to the dusolization request signal output from the AND gate 21.
The data memories 8a, 8b, 8c in the data memories 8a, 5c are selected, and the corresponding address of each data memory 8a+8b, 8c is selected. Then, the new data at the corresponding address position of the data memory 8a of the data area 6a where the new data has been written is read out to the dusolicator 7 via the data multi-layer sensor 12a, and then the dusolicator 7 transfers the read new data to other data. The new data is transferred to the data memories 8b and 8c, and the new data is copied and written to the same selected address position. Data memo! When data is written to J 8b and 8c, the data memo! Write completion signals corresponding to J8b and J8c are output. The dusolicator 7 indicates that all data areas have been written to the fifth state.
The AND gate 22 as shown in the figure is detected. This AND
Output of gate 22 flag memories 9a, 9b, 9c
Set the flag at the corresponding address position to 10', and
The address counter 13 in the figure updates the flag address,
Outputs the next flag address. Through the above steps, data dusolization by the dusolicator 7 is completed. 70 charts of the above operation are shown in FIGS. 7 and 8.

When the data dusolation operation is completed, the new data written to the data memory 8a in the data area 6a is transferred to the data memo! of the other data areas 5b and 5c. J
It is transferred and stored at the same address position of 8b and 8c. Therefore, although there are physically multiple data memories in each data area, logically they have the same data content.
It functions as an individual memory, and also functions as a so-called shared memory.

Note that if new data is written to two or more data areas at the same time, a priority is given to each data area in advance as shown in FIG. 4, and the data duplication is performed according to the priority. It is sufficient to perform the solification operation on the one with the highest priority. That is, in FIG. 4, the data area 6a is in the first position, the data area 6b is in the second position, and the data area 6c is in the third position. When data is written, the data area 6a has a higher priority, so the AND gate 16 outputs the output 11' and the AND
When the gate 17 outputs %OI, duplication of the data written in the first order data area 6a is executed. When the dusolation of the data area 6a is completed, the contents of all flag memories at the address location are reset to 0', and the data at the second position is discarded.

Furthermore, it is desirable to use high-speed memories as the flag memories 9a, 9b, and 9c. By employing a high-speed memory, it is possible to read the flag state of the shift flag memory from the common bus side without substantially interfering with access from the local bus side.

Effects of the Invention Since the present invention has the configuration 1 function as explained above, there are physically multiple data memories provided for each processor, but only one memory having the same data content logically. This function has the advantage that even if access from each processor overlaps, the corresponding data memory can be accessed at the same time, and throughput does not decrease due to access contention as with conventional shared memory. It has a great effect.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of the shared memory device of the present invention, FIG. 2 is a diagram showing a specific configuration example of the data area portion, and FIG.
The figure shows an example of the configuration of an address counter part that is a part of the dusolicator, FIG.
The figure shows one part of the write completion detection circuit, which is part of the duplicator.
Example diagrams, Fig. 6 is a flowchart when an access request is made from the local bus, Fig. 7 is a flowchart when a due diligence request is made from the common bus, Fig. 8 is a flowchart when a dusolicator performs data dusolicitation, and Fig. 9 is a flowchart when a dusolicator requests data. FIG. 1 is a block diagram of a conventional shared memory. 2.3.4: processor, 5: shared memory device, 5a,
5b, 5c: Data area, 7: Dusolicator, 8a
, 13b, 8c: data memory, sa, 9b+9C: flag memory. Figure 5 Figure 6 Figure 0 Tsuka 1C ~ Candy - 6 words - Sleep Figure 7 Figure 8

Claims (1)

[Claims] In a shared memory device that is randomly accessed by multiple processors, a data memory that stores data;
Each processor is provided with a flag memory that corresponds one-to-one to the address of the data memory and that sets a flag at the address location when new data is written to the data memory. In addition, the set state of each flag in each flag memory is cyclically checked for each address, and when new data is written to any data memory, the corresponding A shared memory device comprising one duplicator for data copying, which transfers and writes new data written in a data memory to the same address location in the data memory of another processor.