JPH0120781B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a memory access control device,
More specifically, the present invention relates to a memory access control device that selectively accesses memory at any time, either in word units or byte units.

(Prior art) Conventional technology has an input/output control port with a bus width of 1 byte and an input/output control port with a bus width of 2 bytes in the same configuration to enable either 1-byte data transfer or 2-byte data transfer. As a technique, for example, there is a technique disclosed in Japanese Patent Publication No. 58-46727. The contents are as follows: A bus switching device is placed between the memory and the main bus, and whether the device transfers 2 bytes, the upper byte of 1 byte, or the lower byte of 1 byte. Therefore, we control the way the memory is connected to the main bus, thereby enabling either 2-byte transfers (word-by-word memory access) or 1-byte transfers (byte-by-byte memory access). It is.

However, in this case, if an attempt was made to add more memory modules, a bus switching device would have to be added correspondingly, resulting in a disadvantage that the entire system would become larger.

(Objective) An object of the present invention is to provide a memory access control device that eliminates the above-mentioned drawbacks and performs both 2-byte data transfer and 1-byte data transfer without increasing the size of the system even when memory modules are added. There is a particular thing.

(Embodiment) The present invention has a configuration in which a bus switching device is disposed between a control circuit section consisting of a central processing unit, etc., and a main bus, so that the control circuit section selectively accesses memory in units of words or bytes at any time. be done.

The present invention provides, for example, a data processing device in which a central processing unit, a direct memory access control device, an input/output control port, and a memory capable of specifying words and bytes are connected to a main bus. A signal indicating a first memory portion consisting of the upper byte of the memory capable of both word specification and byte specification of the bus control signal, and a second memory portion consisting of the lower byte. Referring to at least one of the signals instructing the memory portion, each of the central processing unit and the direct memory access control device disposed between the control circuit unit and the main bus may access the memory in units of words. It consists of a bus switching device that selectively accesses byte units at any time.

FIG. 1 is a block diagram schematically showing an embodiment of the present invention.

1 is a 16-bit main central processing unit (hereinafter referred to as
Abbreviated as CPU. ), and the direct memory access (hereinafter abbreviated as DMA) control circuit 2 has memory 5 and memory 6 connected to main buses 21 and 22.
(added memory), 8-bit input/output port 7,
This circuit controls DMA transfer between 8 16-bit input/output ports. Further, the bus switching device 4
This is a control device that connects internal buses 23, 24 and main buses 21, 22. Further, 51 and 61 are memories 5 and 6 configured in word (2 byte) units.
The memory consists of the upper bytes of 5
2 and 62 are memories consisting of lower bytes.

Next, the operation of the present invention will be explained using FIG.
Now, the case where 2 bytes (1 word) are transferred from the 8-bit input/output port 7 to the memory 5 will be explained. First, each signal that will be used in the following explanation will be explained.

(DMA transfer request signal) This is a signal sent from the input/output port 7 or 8 to the DMA control circuit 2 when the data to be sent is ready.

(DMA transfer permission signal) This is a permission signal for (DMA transfer permission signal) and is sent from the DMA control circuit 2 to the port. When this is received by the port, the port begins to send the data.

(Data transfer permission signal) In the DMA transfer cycle, the
This is a signal sent to the DMA control circuit 2, and is a signal for synchronizing according to the speed of the memory.

(Address strobe signal) Indicates that the address indicated by address bus lines A ₁ to _{A 23} (not shown) has been determined.

(Low byte data strobe signal) Indicates that the lower byte memories 52 and 62 are being accessed.

(Upper data strobe signal) Indicates that the upper byte memories 51 and 61 are being accessed.

(Upper byte instruction signal) This is a signal output from the DMA control circuit 2, which indicates the transfer of data corresponding to the upper byte side of the memory in DMA transfer from or to a port.

R/ (Lard write signal) Indicates whether the main bus is used in a read state or a write state.

The above signals are omitted in FIG. 1 for simplicity.

Now, when the data is ready, a DMA transfer and request signal is sent from 8-bit input/output port 7.
The signal is input to the DMA control circuit 2. Then, the DMA control circuit 2 outputs a main bus acquisition request signal (not shown) to the main CPU 1, and the main bus 21,
Get 22. After that, from the DMA control circuit 2,
Address bus lines _A1 to _A23 , upper data strobe signal, address strobe signal, read/write signal R/ (in this case, write state),
An upper byte instruction signal is output, and a DMA transfer permission signal is returned to the 8-bit input/output port 7, starting a DMA transfer cycle.

At this time, since the upper data strobe signal is active, the memory 51 is accessed, and since the upper byte instruction signal is also active, the bus switching device 4 is activated, and the internal buses 23, 24 and the main bus 21 are accessed.
Connect.

Also, since the read/write signal R/ indicates that the data is to be written to the memory, the data from the 8-bit input/output port 7 follows the path indicated by the dotted line 30 in FIG. 1 to the upper byte. The data is stored in the side memory 51. At this time, a data transfer permission signal is sent from the memory to the DMA control circuit 2 in order to synchronize according to the speed of the memory.

The next 2nd byte data transfer follows a similar sequence, but in this case, unlike the 1st byte data mentioned above, it is transferred to the lower byte memory 52, so the upper data strobe signal is not active. Instead, the low byte data strobe signal becomes active.
Also, the upper byte instruction signal does not become active. Therefore, the bus switching device 4 does not operate. In this case, data from the 8-bit input/output port 7 is stored in the lower byte side memory 52 via the path indicated by the dotted line 31 in FIG. At this time, the bus switching device 4 does not need to operate.

The above describes the transfer of data from the 8-bit input/output port 7 to the memory 5.
Transfer of data from 8-bit input/output port 7 to 8-bit input/output port 7 is basically the same sequence except that the read/write signal R/ is changed. Furthermore, data transfer between the 16-bit input/output port 8 and the memory 5 is carried out in word units using the main buses 21 and 22 simultaneously, as is clear from FIG. This point is self-evident.

Further, although the above explanation has been about reading and writing to the memory 5, it goes without saying that the completely similar sequence applies to the expanded memory 6 as well. Also, although the present invention has been explained using DMA transfer as an example, 16-bit main CPUs 1 and 8
Needless to say, even in a dual processor system consisting of a bit slave CPU 3, each CPU accesses the common memory 5 or 6 through the action of the bus switching device 4.

(Effects) As explained above, the present invention has a configuration in which a bus switching device is disposed between the main bus and the control circuit section consisting of a central processing unit and a direct memory access control device. However, it is possible to selectively implement word-based memory access and byte-based memory access at any time without adding any other hardware, and has the effect of making the system more compact.

[Brief explanation of drawings]

FIG. 1 is a schematic block diagram showing one embodiment of the present invention. 1... 16-bit main CPU, 2... DMA control circuit, 3... 8-bit slave CPU, 4... Bus switching device, 5, 6... Memory, 7... 8-bit input/output port, 8... 16-bit Input/output port.

Claims (1)

[Claims] 1 A bus disposed between a control circuit section consisting of a central processing unit and a direct memory access control device and a main bus, through which the control circuit section selectively accesses memory either in word units or byte units at any time. A memory access control device comprising a switching device.