JPH03219360A - Multiprocessor control system - Google Patents

Abstract

PURPOSE:To prevent the through-put of a system from being reduced when a fault is generated in a processor by optimizing a processor to be used for substitutive processing, updating substitutive processing information table and then executing the substitutive processing. CONSTITUTION:At the time of detecting a fault of the processor 2, the 2nd bit corresponding to the processor 2 on an operation status table stored in a main storage 11 is cleared to indicate an operation enabled state. All operatable processors 1, 3, 4 on the operation status table are extracted, the processing capacity of loads of respective processors 1, 3, 4 is checked based upon a substitutive processing capacity table, the combination of processors capable of minimizing the deviation between the load and capacity even at the time of executing the substitutive processing of the processor 2 generating the fault is recalculated and '1' is written in the processor 2 bit of the entry of the substitutive processor so that the processor can execute the substitutive processing of the processor 2 generating the fault. Consequently, demerits such as deviation on the load of the processor for executing substitutive processing and the insufficient display of system performance can be removed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a multiprocessor control system for an information processing device having a plurality of processors.

[Conventional technology]

Conventionally, this type of multiprocessor control system has an information table that stores the presence or absence of a processor that can perform alternative processing in the event of a processor failure. Regardless of the situation, alternative processing was performed.

[Problem to be solved by the invention]

The conventional multiprocessor control method described above checks the presence or absence of a processor that can perform alternative processing as control information when a processor failure occurs, and assigns it to alternative processing without determining the load status of the available processor, so it is difficult to perform alternative processing. The drawback is that the load on the processor is uneven, making it impossible to bring out the full performance of the system.

[Means to solve the problem]

The present invention provides a multiprocessor control method for an information processing device that includes a plurality of processors that operate under the control of firmware and a main memory that can be referenced from each processor. Equipped with an alternative processing information table that outputs the processor number and an alternative processing capacity table that shows the processing capacity and load of each processor, when a processor failure occurs in a multiprocessor system, the operating status table
Recalculate the load of each processor for all alternative combinations, select one of the combinations that minimizes the deviation in the load of each processor, and update the alternative processing information table. This feature is characterized in that the alternative processing is controlled to be performed according to the contents of the alternative processing information table.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

This embodiment includes processors 1 to 4, buses 5 to 8 that connect the processors to the buses, a bus 9 that connects the main memory to the buses, a bus 10, and a main memory 11.

FIG. 2 is a diagram of an operating status table on the main memory 11 used in the embodiment shown in FIG. This table shows that the bits corresponding to the processes and processors that are operating normally are “1”.
” is set.

FIG. 3 is a diagram of an alternative processing information table on the main memory 11 used in the embodiment shown in FIG. This table shows which processor each processor is currently operating as.

FIG. 4 is a diagram of an alternative processing capacity table on the main memory 11 used in the embodiment shown in FIG. This table shows the processing power status of each processor.

Next, the operation of this embodiment will be explained. It is assumed that processors 1 to 7 are connected as a multiprocessor system. When this multiprocessor system starts up, bits 11111 corresponding to each processor in the operating status table 111 in FIG. 2 and the alternative processing information table 112 in FIG. 3 are written via buses 5 to 9 and bus 10. . If all the processors are capable of normal operation, they are set in the operating status table and alternative processing information table as shown in FIGS. 2 and 3. Next, as an example of a failure occurring in a processor, consider a case where a failure occurs in processor 2 during operation of a multiprocessor system.

When this processor failure is detected, the second bit corresponding to processor 2 in the operating status table on the main memory is cleared to indicate an inoperable state. Then, it extracts all the processors that can operate from the operating status table, checks the processing capacity of each processor for the load from the alternative processing capacity table for the extracted processors, and checks the processing capacity of each processor for the load even if the alternative processing for the failed processor 2 is performed. Recalculate the combination that minimizes the deviation in performance, write "1" to the bit of processor 2 in the entry of the alternative processor in the alternative processing information table of the alternative processor 1, and replace that processor with the failed processor. 2 alternative processing is possible.

〔Effect of the invention〕

As explained above, in a multiprocessor system, when a failure occurs in some of the processors, the present invention checks the presence or absence of a processor for alternative processing by referring to the operating status table, and creates an alternative processing information table. By referring to the processing capacity table, optimizing the processor to perform alternative processing based on it, and updating the alternative processing information table to perform alternative processing,
This has the effect of not reducing the throughput of the system when a processor failure occurs.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a block diagram of an embodiment of the present invention.
A diagram showing the operating status table in the main memory in the figure, FIG. 3 is a diagram showing the alternative processing information table in the main memory in FIG.
FIG. 4 is a diagram showing an alternative processing capacity table in the main memory in FIG. 1. 1-4...Processor, 5-8...Path, 9...
Pass, 10... Pass, 11... Main memory, 111...
- Operating status table, 112... Alternative processing information table, 113... Alternative processing capacity table.

Claims (1)

[Claims] In a multiprocessor control method for an information processing device that includes a plurality of processors that operate under the control of firmware and a main memory that can be referenced by each processor, a processor number is input to the main memory and an operable processor number is output. The system is equipped with an alternative processing information table that shows the processing capacity and load of each processor, and an alternative processing capacity table that shows the processing capacity and load of each processor. The load is recalculated, one of the combinations with the smallest deviation in the load of each processor is selected, the alternative processing information table is updated, and the alternative processing information table is updated according to the contents of the alternative processing information table. A multiprocessor control method characterized by controlling processing.