JPS60124744A - Error testing and diagnosing apparatus - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a data processing system comprising at least one processor, one main memory, and one service processor interconnected by a high-speed system bus. Error testing and diagnostic equipment for.

[Prior Art] Testing large-scale integrated logic circuits and memory circuits in chips that make up electronic control elements, processors, and other data processing systems involves It greatly depends on the ease of access (ease of observation, ease of control). Digital systems require extremely high error tolerances, and testing large integrated circuit structures requires such VL
It is problematic because it is time consuming and expensive due to the circuit density of SI (large scale real design). Processing devices such as microprocessors contain very complex chips, and testing these chips requires examining the large number of states that bistable storage elements can assume while executing program routines. The larger number of state change orders that these storage elements can take must be carefully considered.

Viewing microinstructions as finite functional entities, testing microinstructions that are generally well specified and well defined, such as setting the state storage locations of arithmetic and logic elements (AI, U) is a problem that can be easily evaluated after execution of the add microinstruction. However, if, while performing such an add microinstruction, the state of a bistable storage element changes, indicating a bus demand, If all of the above (whether or not) have to be tested in the same way, then we arrive at Tamen 1.

Secondary functions generally require a large number of storage elements associated with the data flow and control logic of the processor. In general, even when special microinstructions are used, it is difficult to directly access storage elements for testing purposes without changing the current state of all storage elements that act as state indicators. He is incapable of locomotion.

The testable large-scale integration and system architecture is LSSD (Level 5en).
rules known as sitiveScan Design rules are often used. According to that rule, a logic subsystem, for example, is sensitive to the level of a signal only if its response to changes in the human input signal in steady state is independent of circuit and wiring delays in the subsystem. (//A Logic
Design 5structure for LSIT
e5tability〃by E, B, Kiche
lberger-Proceedings of th
eDesign Automation 0onfer
ence, A 14゜June 20-22 197
7, New Orleans, Louisiana.

(See PP, 462-468) Kot1. etc. (1) Based on the I+ S S D rule, in order to make the entire storage element observable and controllable, the master/slave controller placed between the logic stages is
The flip-flops are interconnected in test mode to form a shift register chain or several shift register chains. These shift register chains are used to shift test patterns and result patterns to and from the actual logic, respectively.

The shift register chain transfers, for example, complete state data of seven lip-flops to or from a complex logical grouping of multiple chips or modules that are separated from each other in relation to the packaging of the ethical group.
It can also be used to shift register state data. This shift register approach has the benefit of requiring a relatively small number of input/output terminals and
All first package level shift register chains are connected to a common second package level shift register chain, etc.
If implemented, it has the benefit of greater flexibility between different packaging levels without affecting the chip logic.

Since the memory elements of the processor are mostly comprised of shift register stages, secondary functions can be tested either by the integrated service processor or by a separate tester that can be connected. That is, before or after the execution of the microinstruction to be tested, the contents of the interconnected bistable storage elements for testing the shift register are shifted into the service processor or tester, where the state differences are applied. compared to the desired value.

Microinstruction test diagnostics for exchanging data and instructions in a processing unit and between processors by applying test routines to smaller functional entities, such as clock steps of the microinstruction being tested. It is conceivable to improve the ability even more markedly. Such an approach would result in significant improvements in the error tolerance of automated testing.

However, the testing method described above requires high speed transfer of states stored in a large number of bistable circuit elements.

Such high speed transfers are inappropriate for service processors or in-factory testers that rely on slow test circuitry and serial shift mechanisms. Aside from this,
Despite the ultra-high speed technology of processor flyers, it is not possible to further increase the speed of the shift ring. This is because the shift ring consists of two relatively low speed networks, one extending from processor to service processor and the other extending from service processor to processor. (Lines 14 and 1 are tangent to Fig. 1.
3) However, typically a data processing system includes processors 9, 10 . ---n, main memory bag N3. Main memory controller 4. A parallel Akane speed system bus is provided which interconnects different devices such as input/output controller 5 and service processor v6. However, in known data processing systems, these system buses do not provide for service processors to directly access bistable elements of the processor, including state information and other information. The only exception is Meerotspa patent application 83 105 172. '7 is a test and diagnostic device for digital computers. In the case of the data processing systems covered by this application, the storage elements (flip-flops) interconnecting the logic subsystems during normal operation are linked in the form of an addressable matrix for error testing and error diagnosis. A given service processor can provide address information to control the individual storage elements of the matrix, test data to be placed into the storage elements of the matrix, and test control and clock information to be sent to the elements being tested. can be transferred onto the high-speed system bus.

Further, after the logic subsystems are tested, their result data is placed into the connected storage elements, and the address information and control information transferred from the interconnected storage elements in the form of a matrix to the service processor. is then sent to the system bus.

The storage elements of the matrix are made of so-called master flip-flops, which cannot be realized in the usual way by shift registers consisting of master/slave flip-flops, which is why many design concepts of data processing systems This is extremely disadvantageous to

Another drawback of the known system is that the test buses 13 and 14
has only one core and may cause line interference or failure of the entire test bus and thus failure of the data processing equipment. This is because the service processor performs system operating functions in addition to test functions, for example by controlling a system console with a display and a keyboard.

[Problems to be Solved by the Invention] Therefore, it is an object of the present invention to provide an extremely fast, reliable, and inexpensive test in the test mode performed under LSS DyA. The purpose is to provide a possible logical structure.

[Means for Solving the Problems] Therefore, the error test and diagnosis device of the present invention comprises at least one processor to be tested and one service processor interconnected by a high-speed system bus, In a data processing system, a plurality of logical subsystems in a processor are arranged to be interconnected by a plurality of storage elements during a normal operating mode, and the storage elements are arranged to be interconnected by a plurality of storage elements during an error test and diagnostic mode. a plurality of said memories included in predetermined positions of said shift register chain, wherein said elements are connected to form a ring-shaped shift register chain and said start and end stages of said shift register chain are linked by controllable switches; The plurality of storage elements are connected between the system bus and the processor logic comprising the plurality of logic subsystems such that the elements form each stage of an interface register, and during testing, After transferring test data in parallel to the interface registers via the system bus, the test data is sequentially routed through the shift register chain to the logic subsystem and then transferred from the logic subsystem to the logic subsystem when testing is complete. The present invention is characterized in that after the result data is sequentially input to the interface register through the shift register order, the result data is transferred in parallel to the service processor via the system bus.

[Embodiments] Details of embodiments according to the present invention will be described below with reference to the accompanying drawings.

FIG. 1 shows a block diagram of a modular data processing system with l-chip processors (from pul to PUn), referenced 9 to n, which are connected to each other via a (standardized) system bus 8. and a main memory device (MS) 3, a main memory control device (M
SO) 4, a human output control device (TEC00) 5, and a service processor (SVP) 6. Further, connection paths 13 to 17 are provided between the above-mentioned system elements on one side and the service processor 6 on the other side.
control signals, clock signals, and test data are transferred thereto. These connections also include a clock line 15 linking the system elements to a clock generator (OL) 7, which is also connected to a service processor 6 as shown in FIG. There is.

Instead of a central clock generator, such as clock generator 7, each of the processors 9 to n may be provided with an independent clock generator.

The invention will be explained below with reference to a processor 9 designed according to the principles of large-scale integration. For this embodiment, the system bus 8, which may for example be a standardized bus, has a width of 4 bytes, to which both the bus driver (DR) 11B and the bus receiver circuit (R) 19 are adapted. Assume. (See Figures 2, 5 and 7) In many cases, so-called polarity retention
hold) Storage element 23 called a flip-flop
．． 24 is designed as a master/slave flip-flop according to the LSSDSS described above. In test mode, these seven lips are interconnected to form a chain of shift registers.

The manual stage of the shift register is the nl position t in the lower left corner of Figure 2.
f, and its manual power stage includes an inverter 37 and two A,
Follow switch 44 consisting of ND gates 38 and 39 and test bus! Connection to the service processor 6 has been completed via 0A13. Shift register mirror is at position 31
．． 21.11, n2.32.22.12, ---- n
111 of m % 3 m % 2 m and 1 m! :i
)j'- shift register stages. rank [1
The output of the slave flip-flop (Sl,T) at input stage n1 is connected through test bus line 14 to the service processor 6 and through switch 44 to the master flip-flop (MI,T) at input stage n1. connected to. In this way, a connection is established between the processing device to be tested, such as the processor 9, and the service processor 6.

The above-mentioned switch 44 is used to connect the output of the shift register chain to its input, so that the information content of the shift register stages is circulated sequentially from one stage to the next within the shift register chain itself. I can do it.

In known data processing systems, test data, or test patterns, are transferred 1J13 in response to a shift clock applied to the processing device 4 to be tested by a test shift clock line 15 from the service processor 6.
and into the shift register chain. This shift clock, indicated as 5H-OLl in the drawing, corresponds to the shift register stage clock applied at an early stage, and is clocked by the delay means 25 to control the data transfer to the master flip-flop 23. The time will be delayed only by the tip. The delayed clock labeled 5H-OL2 corresponds to the second shift clock of the shift register stage that controls the data transfer from the master flip-flop of @IJ to the slave 7 rig 70 tube (SI, T).

Test data is typically shifted into the shift register chain via line 13. After test data is received at the individual shift register stages, these data are sent to the logic subsystem 20 to be tested. Logic subsystem 20 is typically constructed from different types of logic, such as NAIJD, NOR% inverters, exclusive ORs, and the like. In the logic subsystem 20, test data is either transferred directly from the central clock generator 7 via fil16 to the processor 9, or alternatively generated by a clock generator associated with the processor. is processed in response to the functional clock signal FOL.

The response of the logic subsystem 20 to the test data, ie the result data, is later received by the shift register stage and m by the shift clock 5H-OLI and SR-OL 2 for error analysis or Dljt.
14 into the service processor 6.

Since this serial transfer process is too slow for the large amounts of data needed to test the actual structure of the data processing system, a high speed bit-parallel system bus 8 is used as the transfer means. However, this means that the result data stored in the shift register stage is sent from the interface register of the system bus at the same rate that it is sent in the direction of transfer to the interface register between the system bus 8 and the logic of the processor 9. A problem arises when the test data of the processor being tested is input to the shift register in the direction of reception of the processor being tested.

garland containing the interface register stage
If the shift register chains are arranged in such a way that a structure of fJ is obtained, the parallelization of accesses required by the parallel system bus 8 is possible in the test and diagnostic mode. Garland type shift; - The power and output of the register chain are connected in the form of a ring by switches 44. This ring has connecting lines 49 linking the individual stages of parallel garland elements consisting of positions fJ n 1.31.21 and 11 shift register stages, and connecting lines 49 linking the remaining parallel elements of the shift register chain. 46.47
and 48.

The above-mentioned stage of the Inter7 Ace register is at position lX.

12, ----1 It is the same as the shift register of m.

Data entering at high speed from a service processor or a tester in the factory connected to the system bus 8 and control lines 15 to 17 is sent to the bus receiving circuit 19, the connection line 3b and the master flip-flop 2 of each of the interface register stages.
3 through the manual gate 30. control line 1'7
The control signal at a switches switch 44 to the test mode to couple the garland shift register chain into a ring.

In addition, the pulse of shift clock 5H-OLI is #l1
15 and is transferred to all master flip-flops 23 of the shift register chain. This shift pulse is also transferred to the delay means 25 which generates the pulse of the shift clock 5H-OL2, and the shift clock S
The H-OL 2 pulse is applied to all slave flip-flops in the shift register chain. Also, the master flip-flop 23 of the interface register stage is configured so that the data enters the system bus 8 at a reasonable time.
The control pulse that switches the human-powered gate 30 is the control line l.
Required on '7b.

This completes the first shift step so that in the next shift step new data can enter through the master 7 register flop 23 of the inter 7 ace register. The data of the previous transfer step is transferred from the slave flip 70 via connections 46, 47 and 48 to nl
, n2, ---- to the master flip-flop of the next shift register stage at the nm position.

In this way, data can be sent to the shift register chain much faster than it would be transferred in pure serial mode. In addition, a shift clock that is even more erroneous than the shift clock sent from the service processor 6 to the processor chip may occur within the VLSI chip with a single high frequency mh pulse train.

This also applies to shift clocks 5H-OLI and 5H-OL
Shift clock 5H-OLI without overlapping 2 and without providing margin for the worst 4S case of signal propagation time between adjacent 2 (1iW) shift register stages along the shift register chain. and 5H-OL2
avoids the usual clock screws that limit the pulse frequency of the clock. Since the entire shift register chain is placed in an IU VLSI chip rather than in a single VLSI chip, the pulse frequency of the shift clock is also
You can choose much higher.

Due to the fact that the shift register stud is the other side of the Curland type, and the fact that the stages of inter 7 ace registers are included in the shift register chain, it is also possible to use a single external clock applied by the processor chip 9. The pulses of the shift clocks 5H-OLI and 5R-OL2 generated in response to the pulses are stepwise.
occurs, all interface register stages can be loaded with new information.

The processing time IMj involved is shown in more detail in FIG.

The second line in FIG. 3 shows the clock pulse train 5H-OLI transferred from the service processor or tester to line 15. In this example, the shift clock 5H-CL2 generated by the delay means 25 is delayed and appears on the clock 50 at dt.

Assuming that the maximum delay Δt of the clock system extending beyond the boundaries of the processor chip is twice the maximum delay Δt (1) of the clock confined to the processor chip, the test and result data are It can be shifted by using the oiliness of the mouth. A single external clock pulse shifts the chip clock 5H-O
Generate LI and 5R-OL2. Subsequently, control i 17 b from the service processor 6 or the connected tester
The clock S transferred to the processor 9 via
L trains the manual stage 30 of the master flip 70 block of the interface register stage so that the test data passes through the lines of the system bus 8 and reaches the interface register. JJ. This process is illustrated in the last line of FIG. 3, according to which the subsequent test data ND process is performed directly on the clock SIR, -QL O) pulse.
The result is placed in the interface register. DF6 (data from 6) shown in this last line of FIG. 3 indicates that service processor 6 is the source of these data. Since no bus transmitter circuitry is required, controller C8'KM17Q remains de-energized while transferring result data from processor 9 over system bus 8. (See the penultimate beat J in Figure 3) As shown in Figure 3, the data transfer operation from the service processor 6 to the system bus 8 overlaps with the internal shift step, so the 32-bit For a wide system bus, the time required to access a shift register stage is 64 times faster than the time required to access a regular shift register stage operating under Shorten.

After each test step has been completed in the shift register stage, the result data to be transferred to the service processor 6 for error testing or diagnosis is the output of the interface register master 7'J rough flop 23. , via line 45, bus transmitter circuit 18 and system bus 8 to service processor 6 in the same manner. The time of each transfer is determined by a signal on control line 17c generated, for example, by a service processor energizing bus transmitter circuit 18. However, before that step, the result data of the logic subsystem 20 reaches the master flip 7tff tube 23 through the input stage 26. For stages other than the remaining shift register stages, i.e., interface registers, the result data of the logic subsystem is transferred to the master flip 70 block, e.g., to the master shift register stage at position 21. It is transferred from flip-flop z3 to the associated slave flip 70 tube 24 and via line 49 to the input 27 of the respective subsequent shift register stage. This transfer continues until the result data finally reaches the interface register stage, and the result data is transferred from the interface register to the service processor 6 along the route already described. - In the service processor 6; trlJ control clock S engineering R
Although instead of -OL, a control clock 5T-OL controlling the respective subsequent (result) data, labeled NDO in the last line of FIG. 4, is generated in the service processor 6 or in the connected tester. The time diagram of FIG. 4 is very similar to that of FIG. Following the last line of FIG. 4, these result data are taken from the interface register master flip-flop 23 and transferred to the system bus 8. The signal shown on the second line from the last line in FIG. , controls the bus transmitter circuit 18.

A tester associated with the processor 9 is shown in FIG. 5, which has been improved by introducing an additional power stage 34 of the slave flip-flop 24 of the interface register stage and by a receive line 36a to the bus receiver circuit 19. How an alternate mode for transferring test data and result data by linking stages 34 provides 32 times higher speed than normal transfer of test data and result data with the help of LSSD shift chain It shows that.

FIG. 6 shows the relevant time diagram of the alternation mode.

In comparison with FIGS. 3 and 4, the shift clock 5H-O
It can be seen that the frequencies of LI and 5H-OL2 are reduced by 50%. This is due to the fact that the data transfer rate through the bidirectional system bus 8 is constant and
This is due to the fact that the data are separated by test data and result data.

Compared to the data transfer, which is affected only in the transfer direction from the processor chip 9 to the service processor 6, the control signals on the control JjJ l 7 a activating the bus transmitter circuit 18 have an alternating pattern. (See penultimate line) This alternating pattern also controls the output of the test data, since the pulses of this clock are used to control the input stage 34 of the slave flip-flop 24 of the interface register stage. , [Reflects the state of the clock on l17b. For this purpose, the shift clock 5H-OL2 for the slave flip-flop of the inter-7 ace register stage needs to be switched off. This is done in ring type garland test mode, for example, when control #111 such as binary zero
Gate circuit 25 latched by control signal on 7a
Since this is done with the aid of 'b, the SHIFF)HA/l/S S H-OL 2 generated by the delay means 25a no longer passes. The manual entry of the result data contained in the service processor 6 into an input register (not shown) of this processor takes place in response to the clock TS-OL.

The time charts in FIGS. 3, 4, 6, and 8 show that the shift register stage of the processor 9 has a shift clock 5R-O.
It shows how time is kept by LI and 5H-OL2. In the direction of transfer, ie the movement of result data, the propagation time of the data on the system bus must be taken into account for the transfer lock 5T-OL in the service processor or connected tester. For this purpose, the system bus time 1 is a shift clock SH-OL2, as shown in FIGS. 4 and 6.
will be delayed beyond. When the test data is transferred in the receiving direction, that is, when the test data is transferred, the pulse of the control clock S/R-OL transferred onto the control line 17b is the shift clock 5H.
- It can coincide with the time of OL2.

An additional two-fold speed increase is obtained by using the Kel system bus as a unidirectional bus in test mode.

In this embodiment, the bus is used to transfer result data. According to FIG. 7, processor chip 9.10.
Since -1 to -n are anyway provided with functional input terminals for testing purposes within the factory, the input bus 40 linking these terminals to the tester establishes a connection to the service processor 6. It is also used, and depending on the connection path,
Test data is transferred to processor chip 9. In this way, the transfer of test data and result data can be duplicated. For this purpose, the system bus receiving circuit 19
and the input bus receiving circuit 42 is connected to the control line 17d and the control line 5.
The control line 51 is controlled by the signal on the inverter 4.
1 reflects the inverted state of the signal on the control line 17cl for which it is responsible.

Transfer of result data is again controlled by a signal on control line 17c which energizes bus transmitter circuit 18.

FIG. 8 is an associated time diagram showing the redundant transfer of the test data exchanger and result data NDO and the resulting frequency doubling of the time control signals in columns 1.2.3 and 5.

In the case of errors in the system bus or in the respective bus transmitter circuits and bus receiver circuits, and also in the case of errors in the interface registers of the service processor 6 or in the interface registers for special test purposes, the test data is 13 and switch 44,
It is placed in a garland type shift register chain.

The signal on control line 17a enables AND gate 39 of switch 44 to transfer test data;
AND gate 38 is then deenergized through inverter 37.

Through the AND gate 39 and by the shift clock 5R-OI,1 on the control line 15 and the diad clock 5H-OL2 generated in the processor chip 9, the test data reaches the shift register chain step by step. After the chain loading is complete, test data is applied from each logic subsystem 20. Logic subsystem 20 is responsive to the result data to generate result data that is sequentially transferred from the logic subsystem to the shift register chain. From the shift register chain, the resultant data is transferred for error analysis and error diagnosis with the help of a shift clock on line 14.
It is serially transferred to the service processor 6. Thus,
In the event of an error, the processor logic can be tested and, if necessary, the data processing system can be kept operating at a very low speed. The latter approach is used when continuous operation of the system is more important than what can be achieved with sieving speed.

[Advantageous Effects of the Invention 1] Accordingly, the present invention provides a method in which test patterns and result data transferred on the same high-speed system bus between a service processor or tester and a logic element to be tested are shifted into a chain in a test mode. , or shift), and provides the benefit that the test mode is still performed through the complete respective bus despite malfunctions of the system bus or test)/<.

[Brief explanation of the drawing]

1 is a block diagram of a digital computer using the present invention; FIG. 2 is a block diagram of a processing unit, such as a processor, including a circuit arrangement provided for exchanging test data with a central tester; FIGS. 4 is a time diagram illustrating the exchange of test data; FIG. 5 is a block diagram of a processing device with a decorated circuit arrangement for exchanging test data;
6 is a time diagram illustrating test data exchange in connection with a processing device according to FIG. 5; FIG. 7 is a block diagram of another variant of the circuit arrangement for test data exchange in a processing device; FIG. 8 is a time diagram illustrating the data exchange associated with the processing device according to FIG. 3... Main memory device, 4... Main memory 1tIII
? IgI device, 5... input/output control device, 6...
・Service processor, 7... Clock, 8.
...System bus, 9.10,n...Processor, 20...Logic subsystem, 23...Master flip-flop, 24...Slave...
flip flop. Applicant International Business Machines Corporation Representative Patent Attorney Takashi Tonmiya −
(1 other person)"' 0 JQ, ^; Tomoe ToSc1゜; 2 S+ N-

Claims (1)

Claims: At least one processor to be tested and one service processor interconnected by a high-speed system bus, wherein a plurality of logical subsystems in the processor to be tested are in a normal operating mode. In a data processing system arranged to be interconnected by a plurality of storage elements, the storage elements are connected to form a ring-shaped shift register chain during an error test and diagnostic mode. and a start stage and an end stage of the shift register chain are linked by a controllable switch, the plurality of storage elements being included in predetermined positions of the shift register chain forming each stage of an interface register. an element is connected between the system bus and the processor logic consisting of the plurality of logical subsystems, and during testing, test data is transferred in parallel from the service processor to the interface register via the system bus; After sequentially forcing test data into the logic subsystem through the shift register chain and sequentially passing result data from the logic subsystem through the shift register chain and into the interface register when the test is complete, the result data is is transferred in parallel to the service processor via the system bus,
Error testing and diagnostic equipment.