JPS6293672A - Hierarchy type logical apparatus - Google Patents

Abstract

PURPOSE:To make it possible to efficiently perform the diagnosis of the trouble of LSI on a hierarchy basis without going into an internal circuit, by providing a bypass circuit operating all of the registers as shift registers or bypassing all of them. CONSTITUTION:In such a case that a circuit has a hierarchy structure in an A-D form, for example, when the gate circuit 10 of a hierarchy B is desired to be subjected to trouble diagnosis, only registers 3, 4, 7 are operated as shift registers and registers 1, 2, 5, 6, 8 are bypassed. Whereupon, because scan-in data could be scanned in the shift registers 3, 4, 7 from an external pin 15 and scanned out to an external pin 16, hierarchy diagnosis is enabled.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a hierarchical logic circuit, and particularly to a logic circuit suitable for one-layer fault diagnosis.

[Background of the invention]

The scan design method, in which all flip-flops function as shift registers during testing, is well known, and NCM and ICM have developed a method that can be applied to hierarchically designed circuits.
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However, even when testing a certain hierarchy, this method is disadvantageous in that the scan signal passes through all flip-flops.
This does not enable independent failure diagnosis at the mth level of the hierarchy. Furthermore, it is not clear how to handle cases where there are multiple layers or more.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a logic circuit in which failure diagnosis of a hierarchically designed logic circuit can be efficiently performed separately for each hierarchy.

[Summary of the invention]

Based on the scan design method, the boundaries of each layer are flipped and
To perform fault diagnosis for each layer of a logic circuit that is hierarchically designed to be a flop, (1) partial circuits included in that layer but not included in its lower layers;
2) Flip the boundary between the upper and lower layers of the hierarchy.
The present invention eliminates the need for (3) by adding a bypass circuit. Therefore, in fault diagnosis for each layer, parts unrelated to that layer are no longer required, making true layer-divided diagnosis possible.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to FIGS. 1 and 3.

Figure 1 shows an example of the configuration of a logic circuit having four hierarchical logic blocks A, B, C, and D, and the hierarchical relationship is
Illustrated in the figure. 1, 2.9 are a flip-flop group (constituting a shift register) located at the boundary between the upper layer of layer A and a flip-flop group (constituting a shift register) included in layer A but not included in its lower layer. This is a gate circuit that is included in layer A (constituting a register) and is not included in the lower layer. Similarly, for layer B, 3,4°1
0, 5 and 6.11 for layer C, and 7 and 8.12 for layer C, respectively, indicate the same correspondence as described above.

In the conventional test method based on the scan design method, flip-flop groups 1 to 8 are connected in series.

Since it constituted one large shift register, its state initialization (scan in) and state WA'#
There is a problem that a large test series is required for (scan out), which increases the overall test time.

In addition, for example, when diagnosing the failure of the gate circuit 10 in the hierarchy B, the truly necessary flip-flop groups 3, 4, 7
as well as all other flip-flop information.

FIG. 3 shows an embodiment of the present invention with only the flip-flop groups 1 to 8 shown in FIG. 1 taken out.

13 is a bypass control circuit, its input is given from external input pin 14, and its output signal is sent to shift register 1.
~8 signals, that is, in this case, eight signals are output. Further, 17 is a signal selection circuit, and in this case, there are eight signal selection circuits. This circuit is a circuit that selects either the output signal of the front stage shift register or the output signal of the front stage selection circuit (if not, the scan-in data external input pin 15) according to the output signal of the bypass selection circuit, and outputs the result. . Further, the final stage selection circuit output signal is output to the scan out data external output pin. With this configuration, any of the shift registers 1 to 8 can be freely controlled by the bypass control circuit to operate as a shift register or to be bypassed.

For example, if you want to diagnose the failure of the gate circuit 10 on layer B in Fig. 1, set only 3, 4.7 to operate as a shift register, and bypass 1, 2, 5°6.8. For example, scan-in data can be scanned into shift registers 3, 4.7 from external pin 15.

Hierarchical diagnosis becomes possible because it can be scanned out to the external pin 16.

For example, there is an advantage that a test pattern for an LSI alone can be used as is as a test pattern for a printed circuit board on which an LSI is mounted. In the conventional method, the entire printed circuit board including the mounted LSI is
The design automation system could not handle this until all gates and flip-flops had been developed, but with this method, there is no need to develop the internal circuits of the mounted LSI.

〔Effect of the invention〕

According to the present invention, since hierarchical diagnosis is possible, it is effective in reducing the amount of test data and test time, and it becomes easy to point out the location of a failure. Additionally, a test pattern created for a lower layer alone can be used almost as is as a test pattern for an upper layer, reducing test pattern design man-hours.

Helps reduce processing time for test pattern design automation systems.

[Brief explanation of drawings]

FIG. 1 is a logical circuit diagram having a hierarchical structure of an embodiment of the present invention, FIG. 2 is a diagram representing the hierarchical structure in FIG. 1, and FIG. 3 is a block diagram of an embodiment of the present invention. 1 to 8...Flip-flop group, 9,10,11°12...Gate circuit.

Claims (1)

[Claims] 1. Consisting of a plurality of hierarchical logic blocks based on the scan design method, and in which signal lines at the boundaries of each hierarchy can be directly accessed from external terminals or flip-flops. All the flip-flops are provided with a scan circuit that also operates as a shift register during testing, and all the flip-flops included in the certain hierarchy but not included in the lower hierarchy are In a hierarchical logic device in which a scan order is determined to constitute a partial shift register, a bypass circuit for selecting either a scan-in data signal or a scan-out data signal of the partial shift register; , and a bypass control circuit for generating a control signal for the bypass circuit.