JPH06230088A - Integrated circuit containing array of sequential circuit device and integrated circuit containing logical element - Google Patents

Abstract

PURPOSE: To ensure the propagation by connecting the first and the second latch elements with the first latch output and the second data input and also with the first and the second shift mechanism having a shift input and a test clock input, and giving the data of the shift inputs to the first and second latch elements with the inputs of the first and second test clocks. CONSTITUTION: The data from a combination element 90 is given to the data inputs 104, 114, 124. A scan cell 100 corresponds to ϕ2 clock of an input 106 and stores the data of the input 104 in the inverted form, and this is passed through a data output 101 and then inverter 103 to undergo re-inversion to be fed to the data output 101. Scan cells 110, 120 operate approx. in the same manner wherein only the cell 120 corresponds to ϕ1 clock. In testing the part 92 of an IC 95, the data is taken in from data inputs 91, 94, 93 using the ϕ1 and ϕ2 clocks and loaded in the cells. Then the data is shifted through shift inputs 129, 119, 109 and shift outputs 128, 118, 108 and sent to external pins finally.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION This invention relates to the field of test circuits and test techniques for integrated circuits (ICs), and is particularly used for testing microprocessors, RISC microprocessors, and other ICs including sequential devices. Regarding scan test elements.

After manufacturing an electronic chip or IC, the IC must be tested to ensure that it operates properly. Scan tests are an efficient way to determine which parts of an IC are working properly. Generally, an IC is tested by providing the IC with specific inputs and analyzing the output from the IC. If the IC provides the proper output for its particular input, then the manufacturer can be sure that the IC is working properly.

Certain defects or deficiencies in ICs are difficult to define because they are not directly detectable or visible from any output pin. Scan test is a test technique that provides visibility to the internal circuitry of an IC. The scan test provides input test data or vectors designed to analyze a predetermined portion of the IC, and the IC
Isolate some parts of the IC by receiving test data that reveals defects in the internal circuitry of the.

Testing can be economically implemented for out-of-order or combinatorial ICs. However, if such an IC contains sequential elements such as latches, flip-flops, or other state devices, testing becomes very difficult. A sequential element includes any device whose output depends on the particular state of the device. ICs that may include sequential elements are microprocessors, input / output processors, peripheral controllers, etc. Therefore, such sequential devices are very difficult to test because the state of the devices inside the IC are not readily known and cannot be easily loaded.

Microprocessor IC using sequential elements
A scan cell is placed in the IC to facilitate testing of the IC such as. Scan cells are generally transparent when the IC is in normal operation or in system mode. If the ICs are in test mode, the scan cells perform the function of the sequential elements they replace,
Generally, specific data can be loaded there.
In addition, scan cells can load or capture data associated with sequential elements. The scan cells may operate similarly to shift registers, propagating or sending captured or loaded data in and out of the IC. Some with scan cells are only used for loading data, others with only loading data. The data provided to the external pins by the scan cells facilitates scan test analysis.

A large number of scan cells are required to scan-test a microprocessor IC or the like. Therefore, it is necessary to minimize the area overhead due to these scan cells. The smallest scan cells in the prior art are generally based on latches, which shift data in and out of the scan cells depending on the master / slave configuration. In this typical prior art configuration, each scan cell includes a master stage and a slave stage. The master stage is clocked by the test master pulse and the slave stage is clocked by the test slave pulse. The output of the slave stage is coupled to the input of the master stage in the next scan cell.

By implementing the master stage and the slave stage, data is transferred from the first scan cell to the second scan cell.
It will be possible to save it when clocked to the scan cell. For example, if the first scan cell master stage stores a logic one and the second scan cell master stage stores a logic zero, the test master clock pulse is stored in the first scan cell master stage. , The stored logic 1 is sent to the slave stage, and the second scan cell master stage is made to send the stored logic 0 to the slave stage. If a test slave clock pulse is then applied to the first and second scan cells, the first scan cell slave stage sends a logic 1 to the second scan cell master stage and the second scan cell master stage. The slave stage sends a logic 0 to a third scan cell, external pin or other output. In this way, the data is propagated through the prior art scan cells and ultimately to external pins.

By implementing this, the prior art scan cells behave like shift registers and can propagate the captured data to the output of the IC in response to the clock inputs of the test master and test slaves. Therefore, the master or slave stage stores the data associated with the scan cell after each test slave or test master clock pulse, so that the data is not lost when it is sent from scan cell to scan cell. . These scan cells, however, are disadvantageous because they add transistors to the integrated circuit. Furthermore, these scan cells require coupling two test clock signal inputs to each scan cell. Therefore, prior art scan cells are not preferred in terms of IC cost, size and speed.

[0009]

SUMMARY OF THE INVENTION The present invention includes a first independent latch and a second independent latch.
An integrated circuit including an independent latch of The first independent latch includes a first latch element coupled to the first latch output and the first shift mechanism. The first shift mechanism is coupled to the first latch element and
Shift input and a first test clock input. The data at the first shift input is provided to the first latch element when the first test clock signal is provided to the first test clock input. The second independent latch includes a second latch element that is coupled to the second data input and the second shift mechanism. The second shift mechanism is coupled to the second latch element and includes a second shift input coupled to the first shift output and a second test clock input. When the second test clock signal is applied to the second test clock input, the data at the second shift input is applied to the second latch element.

The present invention also provides a scan capture device for use in an integrated circuit. The scan capture device has a shift register input, a shift register output, and
A test clock input that receives a test clock signal,
Including latch and. The latch includes a first transfer gate,
And essentially includes a single latch element. The latch element includes a latch element input and a latch element output. The latch element output is coupled to the shift register output and the latch element input is coupled to the first transfer gate. The first transfer gate is coupled to the shift register input to allow the data at the first shift register input to be sent to the latch element input when the test clock signal is present at the test clock input.

The present invention also provides an array of sequential circuit elements in an integrated circuit. Each sequential element includes latch means for storing data and shift means for propagating the stored data. The shift means includes a shift input and a shift output. The shifting means of the sequential elements in the array are interconnected such that the shift input of one sequential element is coupled to the shift output of another sequential element. Each of the shift means is alternately controlled by the test master clock signal and the test slave clock signal.

The present invention also provides an integrated circuit including logic elements. The integrated circuit includes a first sequential element and a second sequential element. The first sequential element is at least one of the logic elements.
A first data input coupled to at least one output of the two, a first shift input, and first storage means for storing data at the first shift input in response to a first test signal. Including and The first storage means also stores the data at the first data input in response to the system clock signal and provides the stored data to the first data output. The second sequential element includes a second data input coupled to one output of at least one of the logic elements, a second shift data input, and the data at the second shift input to a second test signal. Second storage means for responsively storing. The second storage means also stores the data at the second data input in response to the system clock signal. The second storage means provides the stored data to the second data output. The first shift input is coupled to the second data output.

The features of the invention believed to be novel are:
Particularity is set out in the appended claims. The invention, together with its further objects and advantages, will be best understood by referring to the description that follows from them in connection with the accompanying drawings. In the several figures, like reference numbers indicate identical elements.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT FIG. 1 illustrates a circuit portion 92 of an integrated circuit 95 embodying the present invention configured for testing certain sequential devices therein in accordance with the present invention.
2 is a schematic block diagram of FIG. The circuit portion 92 includes a combination element 90, an input 91, an input 94, an input 93, a scan cell 100, a scan cell 110, and a scan cell 1.
Including 20. Scan element or scan cell 100,
110 and 120 are each independent sequential elements that operate as a single latch in system mode (during normal operation of the IC).

The combination element 90 is a circuit that represents an AND gate, an OR gate, a NAND gate, an inverter, or another logic element used in an integrated circuit or a combination thereof. Inputs 91, 94 and 93 may be coupled to external pins or to other circuitry within portion 92 or integrated circuit 95.

The scan cell 100 is a data output 10
1, test master clock input 102, data input 10
4, system clock input 106, shift register input 109, and shift register output 108. Inverter 103 is coupled to scan cell 100 between data output 101 and output 105. Outputs 105, 115 and 125 may be coupled to external pins or to other circuits within integrated circuit 95. Shift register output 108 may be coupled to an external pin or to the shift register input of another scan cell (not shown).

Clock input 102 is coupled to receive the test master clock signal. The test master clock signal and the test slave clock signal are preferably test clock signals, such as internal microprocessor test clock signals well known in the art. The test master clock signal and the test slave clock signal are preferably 180 degrees out of phase with each other. System clock input 106 receives the φ2 clock signal. The φ1 and φ2 clock signals are preferably system clock signals that are 180 degrees out of phase with each other, such as internal microprocessor clock signals well known in the art.

The scan cell 110 outputs the data 11
1, test master clock input 112, data input 11
4, including system clock input 116, shift register input 119 and shift register output 118. Between the data output 111 and the output 115, the scan cell 110
Inverter 113 is coupled to. Clock input 112
Are coupled to receive the test slave clock signal. System clock input 116 receives the φ2 clock signal. Alternatively, the clock inputs 106, 11
6 and 126 can receive any phase of the system clock φ1 or φ2.

The scan cell 120 outputs the data 12
1, test master clock input 122, data input 12
4, including system clock input 126, shift register input 129 and shift register output 128. Between the data output 121 and the output 125, the scan cell 120
Inverter 123 is coupled to. Alternatively, output 10
5, 115 and 125 are the data output 101,
It may be directly bonded to 111 and 121. Even though the shift register input 129 is coupled to the external pin,
It may be coupled to other circuitry within 95 or to the shift register output of another scan cell (not shown). Shift register output 128 is shift register input 1
19 and the shift register output 118 is coupled to the shift register input 109.

When IC 95 is in normal operation, scan cells 100, 110 and 120 operate as independent sequential elements. Specifically, scan cells 100 and 110
And 120 act as latches. The data from combination element 90 is data input 104, 114 and 1
Given to 24. Scan cell 100 responds to the φ2 clock pulse at input 106 to store the data at input 104 in inverted form. The inverted and stored data is provided to the data output 101.

The inverter 103 re-inverts the data,
The data is provided at output 105. Scan cell 110
Operates similar to scan cell 100, except that data is received at data input 114 and sent from data output 111 to inverter 113. Inverter 113 provides the re-inverted data at output 115.

Scan cell 120 receives data from circuit element 90 at data input 124. Scan cell 1
20 stores data in inverted form in response to the φ1 clock pulse at system clock input 126. The stored and inverted data is provided at output 121. Inverter 123 reinverts the data and provides the data at output 125. Therefore, scan cells 100, 110, and 120, when in the normal mode of operation, provide a latch function controlled by system clock signals φ1 and φ2.

To test portion 92 of IC 95, test master test clock signals and test slave test clock signals are provided to scan cells 100, 110 and 120. The data is input using the system clock signals of φ1 and φ2, and the data is input 91, 9
By loading at 2 and 93 it is loaded into the scan cell as explained above. The stored data is then transferred to shift register inputs 129, 119, and 109 and shift register outputs 128, 11
8 and 108, and eventually to external pins (not shown).

The data on shift register input 129 is loaded into scan cell 120 in response to a test master clock pulse on test clock input 122.
The data is stored in the scan cell 120 in inverted form. In response to the same test master clock pulse on test clock input 102, scan cell 100 receives data on shift register output 118 and shift register input 109. The scan cell 100 stores the data in an inverted form. Scan cells 100 and 1
Any data previously stored in 20 will be destroyed or lost when the scan cell receives new data in response to the test master clock pulse. The data in scan cell 110 remains unchanged in response to the test master clock pulse.

The data stored in scan cells 120 may then be shifted into scan cells 110 when a test slave clock pulse is applied to test clock input 112 of scan cells 110. The data previously stored in the scan cell 110 is the same as the data from the scan cell 120.
Shifted to 10 will destroy or be lost. The scan cell 110 stores the data in an inverted form.

The data stored in scan cells 110 may be shifted into scan cells 100 when a test master clock pulse is applied to test clock input 102. This data is scanned 100, 11
The process of shifting through 0 and 120 continues until all the required test data is provided on one or more external pins. However, since half of the data is lost or destroyed during propagation, it is the scan cells 110, 1 that propagate to the external pins.
Every other one of 20 and 130 would be the only data originally stored.

For example, if scan cells 100, 110, and 120 respectively capture a logic 1, logic 0, and logic 1 and shift register input 129 is a logic 1, the form of logic 0 is stored in scan cell 110 and shifted. The logic 1 form of register input 129 is a test master clock pulse followed by a test slave clock pulse,
And is propagated to the shift register output 108 in response to subsequent test master clock pulses. Specifically, in response to a first test master clock pulse, a logic 1 on shift register input 129 is stored in scan cell 120 as a logic 0 and stored in scan cell 110, provided at shift register output 118. Logical 0 is
Stored as a logic 1 in scan cell 100. The stored logic one in scan cell 100 is provided at shift register output 108. Scan cells 100 and 1
The data originally stored in 20 is destroyed by the propagation of this data.

In response to the test slave clock pulse, the logic zero stored in scan cell 120 is shifted to scan cell 110 as a logic one. Scan cell 100 continues to store a logic one and provides that logic one at shift register output 108. In response to the second test master clock pulse, scan cell 120 stores an unknown logic level at shift register input 129 and scan cell 110 continues to store a logic one. Further, the scan cell 100 converts the logic 1 in the scan cell 110 into a logic 0.
Memorize as. This logic 0 is the shift register output 1
It is output at 08. In this way, the logic 0 originally stored in scan cell 110 is provided to shift register output 108 as a logic 1 after the first test master clock pulse, with a logic 1 at shift register input 129 being the second. 1 is provided to the shift register output 108 as a logic zero after the test master clock pulse of.

The data originally stored in scan cells 100 and 120 is transferred to shift register output 108.
To propagate to scan cells 100, 110 and 1
20 is reloaded with logic 1, 0 and 1 respectively. Once reloaded, the test slave clock pulse followed by the test master clock pulse are clock input 122 and clock input 102, respectively.
And 122, which causes the data to be propagated to the shift register output 108.

Specifically, in response to a test slave clock pulse, a logic one stored in scan cell 120 is shifted into scan cell 110 and stored as a logic zero. Scan cells 100 and 120 continue to store a logic one. Therefore, after the test slave clock pulse, the shift register output 108 is provided with a logic one.

In response to the test master clock pulse,
Scan cell 100 is a logical 0 in scan cell 110
Is stored as logic 1. This logic one is provided to shift register output 108. Therefore, scan cell 12
A logic 1 in the 0 is output at the shift register output 108 after the test slave clock pulse followed by the test master clock pulse.

Therefore, scan cells 100, 110 and 120 are preferably pseudo-master slave scan cells, which shift data out of integrated circuit 95, preferably by alternating test slave clock pulses and test master clock pulses. Operate. Under this method, the data in every other scan cell will be lost or destroyed.
0 and 120 are advantageous because they use fewer transistors. Further, the corrupted data could be recovered by reloading scan cells 100, 110 and 120 and applying the test clock pulses in reverse order. The test time required to shift the data out of portion 92 requires an extra capture pulse to reload the scan cell after the first set of test data is output from IC95. Other than that, it is the same as other prior art systems that use a conventional master-slave configuration.

Referring now to FIG. 2, this illustrates the capture scan cell 100 of FIG. 1 for practicing the present invention in accordance with this preferred embodiment. The capture scan cell 100 uses fewer transistors because it does not require a slave stage as described with reference to FIG. Since the scan cell 100 can remove the slave stage from its structure, the overhead can be advantageously reduced by nearly 30-40%. Capture scan cell 100 is also representative of capture scan cells 110 and 120. The capture scan cell 100 has a latch portion 13
1 and a shift mechanism or circuit, which includes a test clock input 102, a shift register input 109,
It includes a pass gate or transfer gate 134 and a shift register output 108.

The latch portion 131 includes a latch element 130 and a transfer gate 132. Latch element 130 is an inverter-inverter structure or latch gate, as is well known in the art. A transfer gate is a device that allows data at its input to be provided at its output in response to a control signal.
Transfer gates 134 and 132 typically include built-in inverters coupled across the inverting and non-inverting control inputs. The latch element or latch gate 130 has a feedback mechanism for storing a logical value.

System clock input 106 is coupled to the control input of transfer gate 132 and data input 104 is coupled to the input of transfer gate 132. The output of transfer gate 132 is coupled to the input of latch element 130. The input of latch element 130 is also coupled to the output of transfer gate 134. The input of the transfer gate 134 is the shift register input 1
It is bound to 09. The control input of transfer gate 134 is coupled to test clock input 102. Latch element 13
0 output is shift register output 108 and data output 1
01 and are combined.

In operation, the combination element 90
Data from (FIG. 1) is provided to scan cell 100 by data input 104. The data on data input 104 is provided to latch element 130 when system clock input 106 is provided with a logic high. More specifically, when a φ2 clock pulse is applied to system clock input 106, transfer gate 132 causes data input 10
4 data is given to the latch element 130. Latch element 1
30 inverts the data and shift register output 1
08 and data output 101.

Latch element 130 also receives data from shift register input 109. Test clock input 1
If the 02 signal is a logic high, the transfer gate 134 transfers data from the shift register input 109 to the latch element 130.
To be sent to. Latch element 130 inverts the data and provides the data to shift register output 108 and data output 101.

Although the various conductors / connectors are represented in the drawings as a single line, it should be understood that these are not meant to be limiting, as is understood in the art. . Furthermore, the above description is of preferred exemplary embodiments of the present invention, and the invention is not limited to the particular forms shown. In addition, although only a portion of the various ICs are shown, the present invention is not limited to various different types of ICs such as RISC microprocessors, registers and caches.
Alternatively, any other IC required to test a digital integrated circuit can be used to advantage.
Further, while certain signals are inverted to logic low or logic high, this circuit may be modified to accommodate different logic signals. Further, scan cells may be used to replace any sequential or logic element. These and other variations can be made in the design and arrangement of the elements described herein without departing from the scope of the invention as set forth in the claims below.

[Brief description of drawings]

FIG. 1 is a schematic block diagram of an integrated circuit embodying the present invention configured for testing sequential devices including scan cells therein in accordance with the present invention.

FIG. 2 is a schematic diagram of a scan cell configured in accordance with a preferred exemplary embodiment of the present invention.

[Explanation of symbols]

 95 integrated circuit 100 scan cell 110 scan cell 120 scan cell

Claims (20)

[Claims] 1. A first independent latch comprising a first latch element coupled to a first latch output and a first shift input coupled to a first latch element. And a first shift mechanism including a first test clock input, the data at the first shift input being latched when the first test clock signal is provided at the first test clock input. A second independent latch provided to the element, the second independent latch being coupled to the second data input and the second independent latch element being coupled to the second latch element. A second shift mechanism, including a second shift input coupled to the output and a second test clock input, the data at the second shift input being the second test clock signal at the second test clock signal. An integrated circuit provided to a second latch element when provided at the lock input. 2. The integrated circuit of claim 1, wherein the first shift mechanism further comprises a first transfer gate coupled between the first shift input and the first latch element. 3. The first transfer gate includes a first control input coupled to a first test clock input.
The integrated circuit according to. 4. The first latch comprises a first data input and
The system further includes a first system clock input and a second transfer gate coupled between the first data input and the first latch element, the second transfer gate having a first system clock signal at a first level. 3. The integrated circuit of claim 2, which enables the data at the first data input to be sent to the first latch element when present at one system clock input. 5. The second latch includes a second data output and
The system further includes a second system clock input and a third transfer gate coupled between the second data input and the second latch element, the third transfer gate having a second system clock signal present. 5. The integrated circuit of claim 4, which enables the data at the second data input to be sent to the second latch element if 6. The integrated circuit according to claim 2, wherein the first latch element is an inverter-inverter latch gate. 7. A scan capture device for use in an integrated circuit, the scan capture device comprising a shift register input, a shift register output, a test clock input for receiving a test clock signal, and a latch, wherein the latch is , A first transfer gate and, essentially, a single latch element having a latch element input and a latch element output, the latch element output being coupled to the shift register output and the latch element input being the first transfer gate. And a first transfer gate is coupled to the shift register input to enable the data at the shift register input to be sent to the latch element input when the test clock signal is present at the test clock input. Capture element. 8. A system clock input, a second transfer gate, and a data input, wherein the second transfer gate is coupled between the data input and the latch element input, and the second transfer gate is the system. 8. The scan capture device of claim 7, which enables the data at the data input to be sent to the latch device when the clock signal is present at the system clock input. 9. An integrated circuit comprising an array of sequential circuit elements, each of the sequential elements having a latch means for storing data and a shift input and a shift output for propagating the stored data. And shifting means of the sequential elements in the array are coupled to each other such that shift inputs in one sequential element are coupled to shift outputs in another sequential element, each of the shifting means being a test master. Alternately controlled by the clock signal and the test slave clock signal,
Integrated circuit. 10. The integrated circuit of claim 9, wherein at least one shift output is coupled to an external pin. 11. The integrated circuit of claim 9, wherein at least one shift input is coupled to a logic circuit element. 12. The integrated circuit of claim 9, wherein each of the latch means includes a system clock input for enabling data to be stored in the latch means in response to the system clock signal. 13. The integrated circuit of claim 12, wherein at least one latch means receives a first system clock signal and at least one latch means receives a second system clock signal. 14. The integrated circuit of claim 9, wherein the first system clock signal and the second system clock signal are 180 degrees out of phase with each other. 15. The integrated circuit according to claim 9, wherein the test master clock signal and the test slave clock signal are 180 degrees out of phase with each other. 16. An integrated circuit including a logic element, the integrated circuit comprising: a first data input coupled to at least one output of at least one of the logic elements; a first shift input; First storage means for storing data at the first shift input in response to the first test signal and for storing data at the first data input in response to the first system clock signal. A second data input coupled to at least one output of at least one of the logic elements, the second data input including a first sequential element, the storage means providing the stored data at a first data output, and a second data input Of the shift data input and the data at the second shift input in response to the second test signal and the data at the second data input in response to the second system clock signal. And a second storage means for storing,
An integrated circuit including a second sequential element, the second storage means providing the stored data at a second data output, the first shift input being coupled to the second data output. 17. The circuit of claim 16, wherein the first and second system clock signals are the same signal. 18. The circuit of claim 16, wherein the first and second data outputs are coupled to other logic elements or external pins. 19. Each of the first and second storage means comprises:
17. The circuit of claim 16 consisting of one latch. 20. The circuit of claim 16 wherein the first storage means is directly coupled to the first data output and the second storage means is directly coupled to the second data output.