JPH04135248A - Trace data reading system - Google Patents

Abstract

PURPOSE:To attain the repetitive reference to the trace data in the necessary frequency by generating a data set inhibiting signal for a period when the reference is given to the trace data set at a holding circuit and inhibiting the output of an enable signal to the output of the trace data holding circuit in response to the data set inhibiting signal. CONSTITUTION:A data set inhibiting signal is produced from a signal production circuit 6 for a period when the reference is given to the trace data set at a trace data holding circuit 2. Thus the output of an enable signal is inhibited to a data set inhibiting circuit 8. Therefore the trace data is never set to the circuit 2 for the relevant period and the trace data set at the circuit 2 is set to the set pulse which is supplied to a scan data holding circuit 4 within the period to be referred to. Thus the repetitive reference is possible to the trace data.

Description

[Detailed Description of the Invention] [Summary] Regarding a trace data readout method that can hold trace data during a repeated reference period, the present invention aims to enable repeated reference of trace data a required number of times, A trace data holding circuit sets trace data to the trace data input in response to an enable signal to the set pulse and enable signal inputs, and sets data to the data input in bit parallel in response to a cent pulse to the set pulse input. In a tracer having a scan data holding circuit that sets and outputs bits in series, the data set prohibition signal is output during a period when trace data set in the trace data holding circuit is referenced. a signal generation circuit, a data set inhibit signal input connected to the data set inhibit signal output, and an output connected to the enable signal input of the trace data retention circuit, the trace data retention circuit responsive to the data set inhibit signal; The configuration includes a data set prohibition circuit that prohibits the output of the enable signal to the output of the data set.

[Industrial application field]

The present invention relates to a trace data reading method that allows repeated reference to trace data.

In an information processing device, there is a demand to refer to data set in a register within the device multiple times.

The reason why such a device configuration is adopted is from the viewpoint of improving the reliability of the device.

[Conventional technology]

An example of a circuit configuration that meets the above requirements is shown in Figure 3.
In this figure, trace register 32, trace register 34, trace register 36 are transferred via data bus 30 when a data set clock pulse is applied thereto, provided that a select signal is provided. This is used to set data. The select signal is also provided to multiplexer 38, multiplexer 40, and multiplexer 42. Each data bit of the trace register output from the corresponding multiplexer by the select signal is set in bit parallel in the scan register 44 by the data set clock pulse. The data set in the scan register 44 includes the trace data of the trace register and the scan-in data from the scan-in.
Data control to the scan register 44 is performed so that data is set in the scan register 44 in a time-division manner. The bit-serial scan data from scan-in is
scan register 64 by scan clock pulse
bit serially set to 4. Scan register 44
Data is read out bit-by-bit serially by scan clock pulses.

[Problem to be solved by the invention]

The setting of trace data to the trace registers 32 to 36 and the setting of data to the scan register 44 are performed by the data set clock pulse as described above, so the circuit configuration shown in FIG. A time sequence in which one of trace registers 32 to 36 is set by a data set clock pulse as shown, and set to scan register 44 by the next data set clock pulse is If it were to occur in the circuit described above, the trace register 3 would have set the trace data on the data bus 30 by the data set clock pulse as described above.
On the next data set clock pulse, any trace register of trace registers 2 through 36 will write data on the next data bus 30, the trace data on that data bus 30 will be stored as shown in FIG. As such, the data may be different from that at the time of the above-mentioned data set clock pulse. Therefore, the trace register 32 which has set the data on the data bus 30 by the data set clock pulse
When any one of the trace registers 36 is referenced again in response to a request to refer to the same data, the data will no longer be there. Therefore, the purpose of the reference cannot be achieved.

The present invention was created in view of such technical problems, and an object of the present invention is to provide a trace data reading method that allows repeated reference to trace data.

[Means for solving the problem] FIG. 1 is a block diagram of the principle of the present invention. As shown in this figure, the invention according to claim 1 has a set pulse input, an enable signal input, and a trace data input, and the set pulse to the cent pulse input and the enable signal to the enable signal input. a trace data holding circuit 2 for setting trace data to the trace data input in response to a cent pulse input; and a data input connected to a cent pulse input and an output of the trace data holding circuit 2; The tracer includes a scan data holding circuit 4 which sends data to the data input in parallel bits and outputs data in serial bits in response to the set pulse of the tracer, and is constructed by providing the following components. Its components include a signal generation circuit 6 which has a data set prohibition signal output and generates the data set prohibition signal during a period in which trace data set in the trace data holding circuit 2 is referenced; a data set inhibit signal input connected to an inhibit signal output, an enable signal, and an output connected to an enable signal input of the trace data holding circuit 2; This is a data set prohibition circuit 8 that prohibits the output of an enable signal to the data set 2.

The invention according to claim 2 has a set pulse input, an enable signal input, and a trace data input, and the trace data is output in response to a set pulse to the set pulse input and an enable signal to the enable signal input. It has a trace data holding circuit 2 for setting trace data to an input, a set pulse input, a data input connected to the output of the trace data holding circuit 2, a scan clock pulse input, and a scan-in input. bit-parallel data to the data input in response to the set pulse to the set pulse input; and bit parallel scan-in signals to the scan-in input in response to a scan clock pulse to the scan clock pulse input. The tracer is configured by providing the following components in a tracer having a scan data holding circuit 4 which is set in series and read bits serially. Its components include a scan clock pulse input, an input connected to the output of the scan data holding circuit 4, and a data set prohibition signal output, and a period for referring to the trace data set in the trace data holding circuit 2. During this period, the signal generation circuit 6A that generates the data set prohibition signal, the data set prohibition signal input connected to the data set prohibition signal output of the signal generation circuit 6A, the enable signal input, and the enable of the trace data holding circuit 2. A data set prohibition circuit 8A has an output connected to a signal input, and prohibits output of an enable signal to the trace data holding circuit 2 in response to the data set prohibition signal. The dotted line in FIG. 1 indicates the characteristic portion of the invention according to claim 2.

[For production]

According to the present invention, during the period when it is desired to refer to the trace data set in the trace data holding circuit 2, the data set prohibition signal is generated from the signal generation circuit WI6.6A, and the data set prohibition signal is generated from the data set prohibition circuit 8.8A. Output of the enable signal is prohibited. Therefore, setting of trace data to the trace data holding circuit 2 is prohibited during that period.

The trace data sent to the trace data holding circuit 2 is set to one or more set pulses supplied to the scan data holding circuit 4 within the period and is used for reference.

When referring to trace data, the trace data that is first set in the trace data holding circuit 2 is set as is in the scan data holding circuit 4, so there is no problem that the trace data is destroyed during the reference as in the conventional case. It disappears.

[Embodiment] FIG. 2 shows an embodiment of the present invention. In this diagram,
Components that are the same as those in FIG. 3 are given the same reference numerals and their explanations will be omitted. Selective output of trace register 32 to trace register 36 data to scan register 44 is performed by multiplexer 41 .
In this embodiment, it is configured. A trace data select signal to multiplexer 41 is generated at the output of decoder 48. The output value of the counter 46 is supplied to the input of the decoder 48 . The counter 46 receives first identification data indicating which of the trace registers 32 to 36 the trace data on the data bus 30 should be set to, and one of the trace registers 32 to 36. Second identification data indicating in which trace register the trace data set should be read is output. The first identification data is output in response to a count signal supplied to the count input of the counter 46 via the count signal line 51. The second identification data is output by shifting in a trace register number supplied to a set input of a counter 46 via a scan loop described later in response to a scan clock pulse supplied to a scan clock input. Ru. The trace register number is input to the scan register 44 from the scan-in, is set in the scan register 44 by the scan clock pulse, and then outputted from the scan register 44 as a scan loop signal by the scan clock pulse.

Then, the count value (first identification data) of the counter 46 or the trace register number (second identification data) is supplied to the scan-in input of the flip-flip circuit 52 in bit series in response to the scan clock pulse.

Ll is supplied to the D input of the flip-flop circuit 52, and a clock pulse is supplied to the clock pulse input. The L1 is "1" (a high level signal). The Q output of the flip-flop circuit 52 is also supplied to the other input of the AND circuit 54, and
It is also applied to one input of multiplexer 56 to complete the scan loop to scan out. The scan inhibit signal that has passed through the inverter 49 and the scan clock pulse are supplied to the AND circuit 50 that generates the scan clock pulse (AM).The scan inhibit signal is also supplied to the multiplexer 56 as its switching signal.

In FIG. 2, trace register 32.3436 is
The scan register 44 corresponds to the trace data holding circuit 2 in FIG. 1, and the scan register 44 corresponds to the scan data holding circuit 4 in FIG. The inverter 49, the AND circuit 50, and the flip-flop circuit 52 correspond to the signal generation circuit 6 in FIG. 1, and the AND circuit 54 corresponds to the data set prohibition circuit 8 in FIG.
corresponds to

Next, the operation of the present invention having the above configuration will be explained below.

First, how is the trace data on the data bus 30 transferred to the trace registers 32 to 36?
Which trace register is set in will be explained below.

At that time, the scan inhibit signal is set to l''.

Along with the transfer of the trace data onto the data bus 30, a count signal is provided to the count input of the counter 46 to generate the trace register identification count value to which the trace data on the data bus 30 is to be set. At this time, a clock pulse is supplied to the clock pulse input of the flip-flop circuit 52 to generate a "1" signal at the Q output. This count value is decoded by the decoder 48 and a trace register enable signal is supplied to the trace registers 32 to 36.
A trace data select signal is supplied to multiplexer 41. Therefore, the trace data on the data bus 30 is set in the trace register designated by the trace register enable signal.

As described above, in order to read the trace data set in any of the trace registers 32 to 36, the scan inhibit signal is set to "O".
And times! While outputting a scan clock pulse from 50, a scan-in signal [°0'' and trace register number] is sent from the scan-in to the scan loop (consisting of scan register 44, counter 46, flip-flop circuit 52, and multiplexer 56). Send it in. °'0'' in the scan-in signal is the scan register 44 responsive to the scan clock pulse;
The trace register number is set in the flip-flop circuit 52 via the counter 46.
cents.

Immediately after the cent, the scan inhibit signal is switched to ``1''.This holds the Q output of the flip-flop circuit 52 at 0'' and inhibits the trace data from being sent to the trace registers 32 to 36. , the counter 46 outputs a value for selecting one of the trace registers 32 to 36.

The count value of the counter 46 is supplied to the multiplexer 41 as a trace data select signal via a decoder 48, and is also supplied to an AND circuit 54. Therefore, since the Q output of the flip-flop circuit 52 is ordered to have a "0" signal, the AND circuit 54 does not output the trace register enable signal and does not respond to the next data set clock pulse. data bus 3
The trace data on 0 is newly stored in the trace register 32,
The content of the trace register specified by the trace data select signal passed through the multiplexer 41 is scanned into the scan register 44 in response to the next data set clock pulse while prohibiting the data from being set in the trace register 36.
Heavy bits can be set in parallel. The trace data set in the scan register 44 is the trace data set in the trace register by the previous data set clocker pulse.

Therefore, the trace data can be saved without destroying the previous trace data. This makes it possible to satisfy the request to repeatedly refer to the same trace data at different times.

In order to read the trace data set in the scan register 44 in this way, the scan inhibit signal is set to "0", the AND circuit 50 outputs a scan clock pulse, and the trace data set in the scan register 44 is read out. The trace data is read out by outputting it through a counter 46, a flip-flop circuit 52, and a multiplexer 56.

Note that in the above embodiment, the flip-flop circuit 5
In 2, an example of the configuration in which the prohibition signal "0" that causes output prohibition of the trace register enable signal is set in the flip-flop circuit 52 through the scan loop has been described. It may be something.

[Effects of the Invention] As described above, according to the present invention, setting of data to the trace register is prohibited during the next processing cycle period after setting trace data in the trace register or the required processing cycle period quantity. Therefore, the trace data set in the trace register can be referenced repeatedly without destroying the trace data.

FIG. 2 is a diagram showing an embodiment of the present invention, FIG. 3 is a diagram showing a proposed tracer, and FIG. 4 is a diagram explaining the drawbacks of the tracer shown in FIG. 3.

1 and 2, 2 is a trace data holding circuit (trace register 32.
34.36), 4 is a scan data holding circuit (scan register 44)
, 6 is a signal generation circuit (inverter 49, AND circuit 50,
Flip-flop circuit 52), 8 is a data set prohibition circuit (AND circuit 54).

[Brief explanation of drawings]

Figure 1 is a block diagram of the principle of the present invention. Do-de-27shizutoku0/ri/gu/Lmata 14-a/! , late 70. /'7 figure Figure 1 I'm crying Figure 3

Claims (2)

[Claims] (1) having a set pulse input, an enable signal input, and a trace data input, and transmitting trace data to the trace data input in response to a set pulse to the set pulse input and an enable signal to the enable signal input; a trace data holding circuit (2) to be set, a set pulse input, and the trace data holding circuit (2);
2) a scan data holding circuit (2) having a data input connected to the output of the scan data holding circuit ( 4) in the tracer, the signal generation circuit has a data set prohibition signal output and generates the data set prohibition signal during a period of referring to the trace data set in the trace data holding circuit (2); 6); a data set inhibit signal input connected to the data set inhibit signal output; an enable signal; and an output connected to the enable signal input of the trace data holding circuit (2); 1. A trace data reading method, comprising: a data set prohibition circuit (8) that prohibits output of an enable signal to the trace data holding circuit (2) in response to the trace data holding circuit (2). (2) having a set pulse input, an enable signal input, and a trace data input, and transmitting trace data to the trace data input in response to a set pulse to the set pulse input and an enable signal to the enable signal input; a trace data holding circuit (2) to be set, a set pulse input, and the trace data holding circuit (2);
2) has a data input connected to the output of 2), and a scan clock pulse input and a scan-in input, and sets the data to the data input in bit parallel in response to the set pulse to the set pulse input. , a scan data holding circuit (4) for setting a scan-in signal to the scan-in input in bit series in response to a scan clock pulse to the scan clock pulse input, and reading out the scan data in bit series, The trace data holding circuit (2) has a scan clock pulse input, an input connected to the output of the scan data holding circuit (4), and a data set prohibition signal output.
) during the period of referring to the trace data set to
a signal generation circuit (6) that generates the data set prohibition signal;
A), a data set inhibit signal input connected to the data set inhibit signal output of the signal generation circuit (6A), an enable signal input, and an output connected to the enable signal input of the trace data holding circuit (2). and a data set prohibition circuit (8A) which prohibits output of an enable signal to the trace data holding circuit (2) in response to the data set prohibition signal.