SU1474630A1 - Data input unit - Google Patents

Abstract

The invention relates to the field of automation and computer technology and can be used in telegraph systems, data transmission equipment, information display systems as a keyboard input device. The aim of the invention is to increase the reliability of the input information. The device contains a block of switching elements 1, a polling unit 2, the first 3 and second 4 generators of the code, the control block 5, the buffer storage 6, the first 7 and second 8 registers. The purpose of the invention is achieved due to the fact that block 2 simultaneously polls all the switches of block 1, regardless of their location and number in the keyboard field, and the design of the drivers of codes 3 and 4 is such that it allows to determine the correct sequence of pressing switches in block 1, if the pressing moments differed by more than one period of high-frequency cycles. 2 zp f-ly, 9 ill.

Description

the presence of a closed key-15 re 38, providing a constant corresponding switch connected to the bus of the matrix field of block 1) (fng. whose serial number is equal to the number of this signal input, and in binary code this number is expressed by the number in this the moment at the outputs of the counter 3 then the output of the element And 37 appears a logical signal 1, which is written to the register 38 and fed to the signal input of the block 39, the control input of which is currently from the output of the register 38 receives the enable signal - Oic O (Fig. 8p, l, u, k, l, c, y, time t2). As a result, the output signal of the prohibition element 39 through the element OR 41, the pulse shaper 42 flips the trigger 43 to the state where the operation of the AND elements 31 to AND 44 is blocked, so that the counter 33 from this moment on the signal lines; the driver's turns hold the binary number, which is the corresponding bits (the younger ones at the shaper 3 outputs and the older ones at the shaper 4 outputs) (FIG. 8f, x, y, h, d, e, u, k, l, since

h

From the direct output of the flip-flop 43, the output of the block (shaper) receives a signal of Kots (Fig. 8h). After writing the code to the buffer accumulator 6, the control unit 5 (fig. A signal arrives (fig. 8sh, time t3), which returns the trigger 43 to its initial state, allowing operation of the elements 31 and 44. Counter 38 again starts switching, continuing to control switch 35 after connecting switch 35 to the input element NO 36, the last

0 ches O 0

Wits logical signal 1,

five

five

0

five

The effect of the bits of the shift register 38 (Fig. 2) is the bits of the register 9 (10) numbers (Figs 1). This state of flip-flop 45 is maintained until the next arrival of a pressed signal (fig. 8 8 and time tf) or a signal. The code is incomplete.

After the next signal arrives, the counter 33 is pressed again to alternately connect the signal inputs of the switch 35 to the input element NO 36, At the moment when the input, which has the previous signal log, is again connected, the output of the element 37

but

it is no longer passing through the inhibit element 38, since the inhibit signal is present on its control code — logical 1. It was recorded in the first digit of register 43 in the previous cycle when polling this input of switch 35 and was promoted to this next polling register bit 38. Promotion occurs synchronously with the moments of connecting the inputs of the switch 35 to the input of the NOT element 36. At the same time, as in the previous survey of this input of the switch 35, the logical 1, tf, f is recorded again in the first digit of the register 43. as long as a logical O signal is present at this input, a logical 1 signal is recorded in register 38. Similarly, the processing of a logical O signal is performed on

other inputs of the switch 35, i

If the signal is pressed is not received during the next cycle of the counter 33, which indicates the absence of closed switches in block 1 (Fig. 1), then the second signal from the output of the AND 34 element through the driver 46

and the AND 49 bits of the register 38 will be set to the original State, i.e. reset. The operation of the element And 49 allowed by the signal from the output

trigger 48, which is set to this (resolving) state by a signal from the output of the delay element 47 at the end of each cycle of the counter 33. In this case, the delay time of the element 47 exceeds the pulse duration at the output of the driver 46, which ensures the operation of the element 49 only in if trigger 48 remains in the enable state for at least two cycles. The trigger 48 is reset to its initial state by a logical 1 signal from the output of the HE element 36, which (sig

The logical 1) appears during the cycle of the counter 33 — during the poll cycle of the outputs of the register 7 (8) of the number (FIG. 1) always, if at least one signal input of the element 35 contains a logical O signal, indicating the the presence of a closed switch.

Upon receipt of a code, the incomplete operation of the element 40 is permitted, which allows the signal from the output of the element 37 and, prohibit element 39, to set the trigger 43 to the code presence state. Further, the operation of each of the code generators (first 3 and second 4) occurs analogously.

The operation of the control unit 5 is as follows.

When one of the signals arrives, the presence of a code, for example, from the imaging unit 3 (Fig. 9a, time t), a logic O signal appears on the output of the comparison circuit 57 (Fig. 9c), blocking the operation of the elements

Comrades And 58 and 59 and allowing element 61 to work through element NOT 61. If the second signal The presence of a code (i.e., from the second driver 4) arrives in the same poll cycle of the outputs of registers 7 and 8, i.e. before the signal is generated. The register is polled at the input of block 5, then further operation of block 5 occurs as follows.

At the moment of signal arrival The presence of a code from the second generator (Fig. 96, time tt), the signal at the output of the element 53 appears and the generator 54 generates a pulse (sgD,

nal) Code entry (Fig. 96, g, time t2). Then, after a time sufficient to write the code to the buffer accumulator 6 (Fig. 1), a signal appears at the output of the delay element 55. The code is recorded (Fig. 9e, time tj), allowing the formers 4 and 3 (Fig. 1) continuation of polling cycles, after which the signals to the input of block 5 are received Register is polled (Fig. 9g, 3, moments t4, t5). As a result, at the outputs of the elements And 58, 59, signals appear that enable block 2 (Fig. 1) to continue polling the block (Fig. 2). The operation of the element And 61 is currently blocked by a signal from the output of the element NOT 60 (Fig. 9c, l, from the time L7 to m10 W

five

30 5

0

five

0

five

20 ment tg).

If the signal is the presence of a code from the second driver, it did not arrive in the given survey cycle, i.e. before the occurrence of signals Register polled

(Fig. 9a, b, g, h, moments t6, t) s then the signal is polled through the OR element 62, the delay element 63 and the AND element 61, which is allowed (Fig. 9) by the signal from the output of the element HE 60, has changed There is a flip-flop state 56, and at its direct output, a non-full code appears (Fig. 9z, m, n, o, n, moment t). According to this algorithm, the second driver (Fig. 1) generates a signal with the presence of a code (Fig. 96, time tg). By the result, the signals at the inputs of the And 53 element coincide, after which the Signal and Code signals are generated (Fig. 9a, b, d, d, e, moments tfi, t)

The trigger 56 returns to the initial state last (Fig. 9n, time t,). Further, the operation of block 5 is similar.

Claims (3)

1. A device for inputting information containing a block of switching elements, a polling unit, a control unit, the first code generator, a buffer store, the outputs of the first and second groups of the block, the poll are connected respectively to the inputs of horizontal and vertical buses of the switching elements block, the information outputs of the first code generator connected to the information inputs of the first group of buffer storage, the outputs of which are information outputs of the device, characterized in that, in order to increase the reliability input information, two registers and a second code generator are entered into it, information inputs of the first and second registers are connected respectively to the outputs of the first and second groups of the polling unit, the first and second outputs of the polling unit are connected to the synchronization input of the first and second registers, respectively. which are connected to the information inputs of the first and second code generators, respectively, the third and fourth outputs of the polling unit are connected to the installation inputs of the first and second signals, respectively code generators, information outputs of the second code generator are connected to the information inputs of the second group of the buffer accumulator, the record entry of which is connected to the first output of the control unit, the second and third outputs of which are connected respectively to the first and second control inputs of the code formers, the third and the fourth outputs of the control unit are connected respectively to the first and second control the inputs of the polling unit, the first control outputs of the first and second code formers are connected respectively to the first and second inputs of the control unit, the second control outputs of the first and second code formers are connected respectively to the third and fourth inputs of the control unit, the first synchronization input of the polling unit and the synchronization input of the first shaper of the code is the first clock input of the device, the second synchronization input of the polling unit and the synchronization input of the second shaper of the code are the second clock device input. 2. The device according to claim 1, characterized in that each of the code drivers contains seven AND elements, a switch counter, a NOT element, a register, a prohibition element, three OR elements, three flip-flops, three pulse drivers, an element delays, the first input of the first element AND is the synchronization input of the code generator, the information inputs of the switch are the information inputs of the generator, the output of the first AND element is connected to the first input of the second AND element and to the counting input of the counter, whose outputs are connected to the inputs of the third AND element, addressable the switch inputs and are the information outputs of the driver, the switch output is NOT connected to the first input of the fourth element AND and the reset input of the third trigger through the element, output h of the solid element I is connected to the first input of the fifth element I, to the first input of the prohibition element and to the information input of the register, the output of which is connected to the second input of the prohibition element, the output of which is connected to the first input of the first element OR, the output of which is connected through the first pulse shaper to the setup input of the first trigger, the direct output of which is the first control output of the code generator, and the inverse one is connected to the second input of the first element I and the first input of the sixth (element AND, the output of which It is connected to the reset input of the second trigger and is the second control output of the code generator, the direct output of the second trigger is connected to the second inputs of the second and fourth elements AND, the first input of the third element OR is the installation input of the code generator, the second inputs of the third element OR, and the fifth element And are the second control input of the driver codes, the output of the third element And is connected to the input of the second pulse driver, the output of which is connected to the first input of the seventh element And and the delay moment with the installation input of the third trigger and the second input of the sixth And element, the direct output of the third trigger is connected to the second input of the seventh AND element, the output of which is connected to the register reset input, the output of the second AND element is connected to the first input of the second OR element, which output is connected with the register synchronization input, the output of the third element OR is connected via the third pulse shaper to the reset input the counter, the setup input of the second trigger and the second input of the second element OR, the reset input of the first trigger is the first control input of the driver codes. 3. The device according to claim 1, wherein the control unit comprises four AND elements, a pulse shaper, two delay elements, a trigger, an OR element, a comparison element and an NOT element, the first and second inputs of the first AND element and the comparison element are - responsibly the first and second inputs of the block, the output of the first element I is connected to the input of the pulse former, the output of which is connected to the input of the first delay element and is the first output of the block, the output the first delay element is connected to the reset trigger input and is the second output of the block; the output of the comparison element is connected to the first inputs of the second and third AND elements and through the element NOT to the first input of the fourth And element, the output of which is connected to the trigger installation input is the third output of the block, the outputs of the second and third elements of AND are the fourth and fifth outputs of the block respectively, the first input of the OR element and the second input of the second H. element are the third input of the block, the second inputs lementa OR and the third element and the fourth block are input, an output of OR via second delay element coupled to a second input of the fourth element I. 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