SU1005013A1 - Data input device - Google Patents

Description

memory, the output of which is connected to the first input of the second register and is the output of the device, introducing a trigger, elements 2I-PLI, 2-OR-AND, the second decoder and code converter, the first input of which is combined with the second inputs of the first and second registers connected to the second output of the counter / second input - to the trigger output, the third and fourth inputs of the code converter are combined with the corresponding inputs of the first element 2И-OR and connected to the outputs of the first and second registers, respectively, the fifth input of the code converter element 2ILI-I and with the output of the second decoder, the output of the code converter connected to the information input of the block, the memory the second input of element 2ILI-I is connected to the first control input of the memory block and the second output of the counter, the third input is connected to the input element 2I-OR, and the output to the second control input of the memory unit, the output of the first decoder is connected to the input of the keyboard and to the input of the microprogram control unit, the output of which is connected to the input of the second decoder.

Figure 1 shows the block diagram of the proposed device; figure 2 - the timing diagram of his work.

The circuit includes generator 1, counter 2; the first decider 3, the keyboard 4, the first register 5, the logical block b, the memory block 7, the second register 8, the microprogram control block 9, the control bus 10, the address bus 11, the code converter 12, the element 2IL-I 13, the element 2I- OR 14, second decoder 15, trigger 16, information on bus 10 LD1R, values of the first and second bits of the 11UPR-1 bus, UPR-2, and TO-T4 clock pulses.

The device works as follows

in a way.

 The generator 1 and the counter 2 form a sequence of addresses on the bus 1 and the synchronization pulses on the bus 10 (see figure 2). The signals on bus 11 through the decoder 3 interrogate the keyboard 4. The keys connected to one output of the decoder 3 form one group with a specific type. The information from the key group is rewritten to input register 5 and fed to logic block b. Simultaneously with polling the keyboard 4, the decoder 3 polls the block 9, at the output of which a command code is generated, which can take five different values according to the number of command types, which determines the algorithm of operation of the logical 1 of block 6. From the high bits of the counter 2 on 1Л1 not 11 stakes of numbers of groups of buttons goes to the lower address inputs of block 7. From the highest bus size 10-UPR-1 from counter 2 to the highest bit of block

7 A logical level arrives that does not switch over the keyboard polling time 4 to the two memory areas of block 7: with a logical unit of oi, with a logical one (zero auxiliary (see Fig. 2). But there is no powerful memory area (pressed-not clicked) of the previous survey cycle.

 At the same time, under the pony polling cycle, there is a time between successive polls of the same group of keys.

The 8 main areas of the memory block of the storing nts command formed by logic block 6. After the next change of address on bus 11, the current information (A) from the group of keys is rewritten into register 5 (interval TO-T1 of FIG. 2) and from there goes to the direct the inputs of the 2I-LN 14, simultaneously with the inverting inputs of this block, from register 8 receives a code corresponding to the state of the same group of keys in the previous interrogation cycle. The signal at the output of block 2I-IL 14 is determined by the expression

A, / VS) V (/ I2AC2) V ... V (, (1)

where AK is the k-th bit d A;

CK code bit at the output of the register 8.

The single result of this operation means that at least one key has been pressed in this group of keys since the previous block polling cycle. In the interval T1-T2 (see FIG. 2), information A is recorded into the auxiliary storage area of unit 7.

Claims (2)

In the interval T2-T4, the signal at the UPR-1 has a single value (see FIG. 2). This calls the main area of the block 7, from which the command (B) generated in the previous poll cycle is copied to register 8 and received from the outputs of register 8 to the input of the transponder 12 code. The code converter generates a code at the information inputs of block 7, which depends on the code combination at its inputs. At logic zero on the UPR-1, the converter 12 of the copa transmits to the output a code from the output of the register 5. With a logical unit on the UPR-1, it performs bitwise logical operations with the codes from the registers 5. The command code (.1 coming from block 9 is decoded by the decoder 15 and received (m at the input of the converter 12 of the code. When a code arrives, corresponding), the 1-st command of the retransmission (00001) or the command with mutual exclusion (00010) the converter of the 12 code sends the output code from the output of the register 5 to the output. code corresponding to single commands (100100), The code converter 12 generates a code, each bit of which represents the sum modulo two corresponding code bits from the outputs of registers 5 and 8. When codes are received that correspond to one-time commands (01000 or general reset commands (10,000 code converter 12 produces a code corresponding to Each logical addition of codes from the output of registers 5 and 8, while the output of the converter 12 of the code must not have a reset sign (logical O). In the presence of a prize reset (logical 1), the pre | 7 code generator forms a zero code on the receiver. In this case, the reset signal for the commands with a common reset is the signal on the first digit of register 5, and for one-time commands, the signal from the trigger output 16. Trigger 16 is set to one by the signal from the EEP arriving at its S input at the end of the exchange. Trigger 16 is reset at the end of the first cycle of polling the keyboard 4 with a signal Transfer from counter 2. Commands generated by the code converter are recorded in block 7 when there is a recording signal at the output of element 2OR-E 13 that performs the following logic function (), (2) g -de UPR2 - signal value on the UPR-2 bus; D is the value of the signal at the output of block 2I-OR 14; P g value of the signal at the output of the decoder 15 - corresponding to the retransmission command. The use of the invention makes it possible to issue an already formed array of commands to the EZP, in which each bit is assigned to a specific key, and a single value of the bit corresponds to issuing a command. Due to this, there is no need for additional processing of information in a computer. Invention The device for entering information contains a keyboard, the output of which is connected to the first input of the first register, the microprogram control unit, a pulse generator, which is connected to the smsggi descent, the first output of which is: n with the input of the first decoder and with the address input of the memory block, the output of which is connected to the first input of the second register and is the output of the device, I distinguish DieecH in that As part of the device application, by introducing a command set into an EEC, a trigger, 2I-OR and 2IL-I elements are entered into the device, the second disinfator and code converter, the first input of which is combined with the inputs of the first and second registers and connected to the second output of the counter, the second input - to the trigger output, the third and fourth inputs of the code converter are combined with the corresponding inputs of the first element 2I-LII and connected to the outputs of the first and second registers, respectively, the fifth input of the code converter is connected to the first input One element of the 2ILI and with the output of the second decoder, the output of the code converter is connected to the information input of the memory block. the second input of the 2ILI-I element is connected to the first control input of the memory unit and the second output of the counter, the third input is connected to the output of the 2I-OR element, and the output is connected to the second control input of the memory unit, the output of the first decoder is connected to the input of the keyboard and the input of the firmware control unit, the output of which is connected to the input of the second decoder. Sources of information taken into account in the examination 1. Authorship certificate of the USSR 726522, cl. G06 F 3/02, 1979. 2. Authorship of the USSR. 499565, class G06 F 3/02, 19 () 9 (prototype).