SU1203498A1 - Digital function generator - Google Patents

Description

the output of the first memory block is connected to the second information output of the digital function generator; the address inputs of the rows of the first and second memory blocks are combined and connected to the output

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The invention relates to automation and computing and can be used in data compression equipment for data transmission, for analyzing and processing audio and video signals, for spectral analysis of random processes,

The purpose of the invention is to increase speed by reducing the number of cycles for the formation of functions.

FIG. L is a functional diagram of the digital generator of the Haar and Schauder functions in FIG. 2, the first eight functions of the Haar and the corresponding Schauder functions.

The digital function generator contains registers 1 and 2 of shift, binary counters 3-5, reversible counter 6, triggers 7 and 8, element OR-NOT 9, elements AND 10 and 11, blocks 12 and 13 of memory, element IS-CLIP OR 14 , element OR 15, one-shot 16, clock input 17, outputs 18-20.

The digital function generator works as follows.

In the initial state, in all counters, memory blocks and register 1, the zero code is recorded, in register 2, the code 001, trigger 8 is set to 1, and trigger 7 is set to O. The clock pulses arrive at the synchronization input of the binary counter 5 (coefficient recalculation p) and through the element OR NOT to the synchronization inputs of the registers 1 and 2 of the shift. As; the contents of shift register 1 is zero, then through n, EfogjN clock pulses at the output of binary counter 5 appears 1, on the front of which

The third binary counter, the synchronization input of which is combined with the output of the end of the formation of the functions of the digital function generator and connected to the transfer output of the continuous version of the counter.

the one-shot 16 generates a pulse which sets the trigger 1 to 1, and the binary code 3 records the code, ..., oSn (i.e., 000). 5 Next, the clock pulses through the element 10 and arrive at the synchronization inputs of the binary counter 3 and the reversing counter 6, as well as the input of the element EXCLUSIVE OR

0 14. Element OR-NOT 9 prohibits the passage of clock pulses to the clock inputs of shift registers 1 and 2. At the output of the binary counter 3, the address codes are generated.

15 columns of cells 12 and 13, c; which are the values of the HO Haar functions (block 12) and S Schauder (block 13) according to FIG. 2. By accumulation in a reversible counter 6

0 N pulses at the output of its transfer, coinciding with the output 1B of the device, appears 1, signifying the end of the formation of the functions H and 8 &, according to which the contents of the binary

5, counter 4 is increased by 1,

shift register 1 writes the following code, cdi, -and, and function numbers 001, and the contents of the remaining counters. Triggers and Register 2

0 is being restored.

At the output of binary counter 4, the addresses of the rows of the RAM blocks .12 and 13 are formed, therefore, the values of the ordinates of the functions H and S are written

5 in the next line with the number 001. For the following clock pulses, information is shifted in registers 1 and 2 of shift. Upon detection of 1 In the most senior de register 1

 the shift trigger 7 is set to 1, which is fed through the OR element 15 to the input of the one-oscillator 16, at the output of which a pulse is formed, along which the lower bits are written to the high bits ..., Hu of the binary counter 3

 code bits .e. x (x,,, etc., with a shift by one bit.

 functions H and S, and nonzero sign-. functions are added to the corresponding. The 3 cells of the blocks 12 and 13, which are located in the binary counter, are the outputs of the reversible counter 6 and shift register 2 connected to the inputs of the element 11, which produces 1, when the codes on its inputs coincide. When this trigger 8 is set to O, therefore, the reversible counter 6 starts

It works in the subtraction mode, and the element 1 s; KEY OR 14 transmits 7-act pulses without inversion. Thus, the negative ordinates of the Haar functions and the decays of Schauder functions are formed.

When resetting the reversible counter 6, a pulse appears at the output of its transfer, signifying the end of the formation of the function. The content of binary counter 4 is increased by 1, the following code is entered into the shift register 1, and the contents of the remaining trigger counters and shift register 2 are restored and the following functions are generated in a similar way.

 co§ / roffeHi // f

Phi.1

Claims (1)

A DIGITAL FUNCTION GENERATOR containing two triggers, two shift registers and the first element And, the first input of the first element And connected to the output of the first trigger, the synchronization input of which is connected to the output of the highest bit of the first shift register, characterized in that, in order to improve performance , it introduced Three binary counters, a reversible counter, an IPI-NOT element, a second AND element, an EXCLUSIVE OR element, an OR element, a one-shot, two memory blocks, and the synchronization input of the first binary counter is combined with the first input of the OR-HE element, the second input of the first AND element and is connected to the synchronization input of a digital function generator, the output of the first binary counter is connected to the first input of the OR element, the output of which is connected to the input of the single-vibrator, the output of which is connected to the combined control input of the second binary counter and the installation input of the first trigger, the output of which is connected to the combined second input of the OR element and the second input of the IPI-NOT element, the output of which is connected to the combined synchronization inputs of the first go and second shift registers, exit! the least significant bits of the first shift register are connected to the high-order inputs of the second binary counter, the synchronization input of which is combined with the first input of the EXCLUSIVE OR element, the synchronization input of the reverse counter, the least significant bit input of the first memory block and connected to the output of the first bit AND, the input of the most significant digit of the first block memory is connected to the output of the element EXCLUSIVE OR, the second input of which is combined with the control input of the reverse counter and connected to the output of the second trigger, setting the second input of which is connected to the output of the second element And, the first input of which is connected to the output of the second shift register, the second input of the second element And is combined with the information input of the second memory block and connected to the output of the reverse counter, the output of the second memory block is connected to the first information output of the digital function generator, the column address input of the second memory block is combined with the column address input of the first memory block and is connected to the output of the second binary counter, the output of the first memory block is connected to toromu digital data output of the function generator, the address input lines of the first and second memory blocks are combined and connected to the output of the third binary counter whose clock input is combined with the output of the digital closure forming function and the function generator is connected to the output of the transfer down counter.