SU739515A1 - Device for data input to digital computer - Google Patents

Description

Video & relate to the field of communications and computing and can be used to enter information into the computer. A scanning device is known that determines changes in the chains of telephone systems and contains a memory element for each scanning point of the recording of a change in the state of the latter, a buffer register from which reading occurs in the process 1. The disadvantage of this device is the ability to enter s buffer register and the subsequent reading into the processor of unreliable information that may occur due to the presence of pseme in the line. The closest to the invention of the technical essence and the achieved result is a noise suppression device used for reading alphanumeric information and Sbde1 ka1 its serially connected first coder, register and scanner, the first outputs of which are connected to the computer, the second outputs - with the first inputs of the elements And not the first switch, the other inputs of which are connected to the first inputs of the comparison unit, the second inputs of which connect to the outputs of the register, and the outputs through the second switch with input odes of the register. The disadvantages of this device are a significant amount of memory, a preliminary analysis of interference and programming of possible true combinations, the complexity of the device. The aim of the invention is to increase the reliability of the input information. .. This is achieved by the fact that the OR elements and the distributor, whose inputs are connected to the corresponding inputs of the device, the scanning unit and the input of the second switch, the first and second outputs to the second switch, the third output to the comparison unit, the fourth output with the register, the fifth output - with the second inputs of the AND elements, the outputs of which are connected to the first BFJM inputs of the OR elements, the second inputs of which are connected to the outputs

block comparison, and the outputs - with the Vhos1Mi register.

The block diagram of the device is presented in the ria drawing.

The device contains the first switch 1, the device inputs 2, the register 3, the scanning unit 4, the device outputs 5, the comparison unit 6, the second switch 7, the distributor 8, the AND 9 elements, the OR 10 elements, the readiness signal bus 11, the device 12.

The device works as follows.

. On bus 11, scanning unit 4 issues a device readiness signal to enter information, which also enters the distributor 8 input. In response to this signal, the input start signal arrives at the device input, which arrives at the distributor 8. The latter generates a series of three service signals. separated from each other by a time interval slightly more than or equal to the duration of the interference.

The first service signal is fed to the input of the second switch 7 and then to the input of the register 3. Information about the state of the inputs 2 of the device is taken by the first switch 1 and fed to the inputs of the register 3. From the other outputs of the first switch 1, the information is fed to the inputs of the comparison unit 6, where the second service signal from the distributor 8 is compared with the contents of the register 3.

In the case of the corresponding states of the bits of the outputs of the comparison block B, logical O are formed, which through the element OR 10 sets the corresponding trigger of register 3 to the initial state in case of discrepancy - signals from the outputs of the comparison block 6 arrive at the inputs of the second switch 7. The third service signal from the distributor 8, arriving at the second switch 7, passes to the output ONLY; in the case of permission at the respective inputs, ensuring: the ability to write to the triggers of register 3,

. If it is written in register 3, it is fed to the inputs of scan unit 4.

Scanner block 4 gives you-. moves at the address address of only those points. which have a sign of the presence of an infarction.

. When reading each register bit 3 simultaneously with the appearance of a signal at the device output, it also enters the corresponding input of the first switch 1, prohibiting the passage of information through the corresponding input.

As confirmation of the reception. The first address to the device input 12 is a reset signal, which, Q has passed through the circuit: distributor 8, elements AND, 9, elements OR 10,. . will return the corresponding trigger register 3 to the zero state. At the output of register 3, the state is removed and the next output is then polled, and so on.

At the end of the scan, the output of the scanner unit 4 appears — a signal that goes to the reset input of the second switch 7 and to the 0 input of the distributor 8, returning them to the initial state.

Claims (2)

1. US patent, 3532827, CL.179-18, 1971., five 2. Japan patent, 50-13093, cl. 97/7 / B62, 1975 (prototype).