RU1807494C - Data exchange device - Google Patents

Abstract

The invention relates to computer technology, in particular to devices for exchanging information (data) between a computer and a user, as well as between various computers in a data transmission network of a ring structure. The purpose of the invention is to reduce the volume of equipment for the device and to increase the impedance of communication channels between computers in data transmission networks of a ring structure. A second comparison unit, a counter, an AND element, an OR element, a block of AND-or-NOT elements and their connection is introduced into the device, which makes it possible to identify the moment of recording information from the corresponding computer channels in all information registers of the device at the beginning of the device’s operation cycle, and also provide information from a computer in the channel of which a sign of an empty (nullified) register is detected. Each computer can record information in its register several times per. M-cycles of the device. The recorded information is continuously circulated in the channel registers, and when the recipient address is recorded in the information register, the computer number is read from the computer in the channel of which the comparison was made. Recording of information from each computer to the channel information register occurs synchronously at the beginning of the next cycle of the device’s operation (simultaneously to all information registers) and is identified by a counter every N-cycles of the device’s operation; asynchronously - during a queue cycle, upon detection of an empty register sign in the information register, when all zeros are stored in it, and if the recipient address is greater than the current address code at the counter outputs. 3 ill. (L С 00 о VI Ю 4

Description

The invention relates to computer technology and can be used in digital computer systems and networks, data exchange systems between a computer and a user.

The aim of the invention is to reduce the amount of equipment of the device and increase the channel capacity.

In FIG. 1 is a functional diagram of a device; in fi g. 2 — a scheme for placing information in a channel register; in FIG. 3 is a timing diagram of a device.

The device contains a counter 1 and N channels, consisting of a block 2, element And 3, element OR 4, first 5 and second 6 switches, information register 7, second block 8, element block And 9, block element OR NOT 10 , the first information input 11, the second information input 12, the second information output 13, the first. information output 14, the address output 15, the first 16 and second 17 clock inputs, the first control input 18 and the first control output 19.

The first information input 11 and the output 14 of the 1st channel (1 1, N-1) are respectively the input and output for connecting the information output and the input of the i-th computer, the second information input 12 of the 1st channel is connected to the second information output 13 (1 + 1) channels, the second information output 13 of the N-ro channel is connected to the second information input 12 of the first channel, the first clock inputs of the channels are connected to the first clock input 16 of the device, and each channel consists of the first 5 and second 6 switches, block Comparison 1, the first information inputs which are connected to the first information inputs of channel 11, information register 7, the first and second information inputs of which are connected respectively to the outputs of the first 5 and second 6 switches, the second information and control inputs of which are connected respectively to the second information input 12 and the first clock input 16 of the channel , block of elements And 9, the output of which is the first information input 14 of the channel, and the first and second outputs of the information register 7 are connected respectively to the second information the input of the block of elements And 9 and form the second information output 13 of the channel, the second block of comparison 8, the first and second information inputs of which are connected to the first 11 and third 15 information inputs of the device, respectively, of the block of elements OR NOT 10, the information input of which is connected to the outputs information register 7, and the output is the first control output of the channel 19, element And 3, the third input connected to the output of the block of elements OR-NOT 10, the second input connected to the synchronizing input 17 of the channel, and the first input ohm connected to the output of the second comparison unit, the OR element 4, the first and second control inputs of which are connected to the output of the And 3 element and the first control input 18 of the channel, respectively, and the output of the OR element 4 is connected to the second clock input of the switches 5, b and c each channel, the first and second control inputs of the And Block 9 are connected respectively to the output of the comparison unit 8, the second input of the And 3 element and the input of the counter 2, and the input of the counter 2 is the second clock input of the device and is connected to the clock m channel input 17, the first control input 18 connected to the overflow output of counter 2, the address output of which is connected to the third information input 15 of the channel.

Consider the purpose of the elements of the device.,

The second comparison unit 8 compares the recipient address code with the current code at the output of counter 1 and, on the basis of this, gives permission to issue a control signal for receiving information from the computer, which, at the same time, is a signal that the device is ready to receive information.

Counter 1 counts the number of clock pulses and allows the recording of information from the computer in the information registers every N cycles - one cycle

5 of the operation of the device, and also generates a code for the current address for block 1.

Element And 3 generates a control signal in the synchronous mode of operation of the device at the next clock pulse,

0 if the address of the recipient of information is greater than the current address at the output of counter 2.

The OR element 4 allows the recording of information from the computer channel in the information registers at the beginning of the cycle, when the record

5 is initiated by counter 1 or in the middle of a cycle in asynchronous operation when an empty register is detected.

The first and second switches 5 and 6 transmit information from the computer to

0 information registers 7 from the first information input 11 or the second information input 12.

Information register 7 - the memory element of the device performs the functions of receiving and storing information.

Comparison unit 8 compares the recipient address and computer number and, on the basis of this, controls the output of information from information register 7 to the channel

About the computer.

The block of elements And 9 provides information from the information register 7 to the computer for the first information output 14.

5 The block of elements OR-NOT 10 monitors the contents of the information register 7 for the presence of a zero combination (sign of an empty register) and, if the information register 7 is reset, it gives a control signal.

The first information input 11 is for receiving information from a computer channel to the device.

The second information input 12 serves to receive information from the information register 7 of the channel of the previous computer via the second information input 13 into the channel of the subsequent computer,

The first information output 14 is for transmitting information from the device to the computer channel.

The third information input 15 is for transmitting the current address from the address output of the counters 1 to the second comparison unit 2 of each computer channel. . The first 16 and second 17 clock inputs of the device serve to transmit pulses synchronizing the operation of the computer and the device. ..: ...:. -,

The first control input 18 is designed to transmit a control signal from the overflow output of counter 1 to all the channels of the computer of the device through which the recording mode of Information from the computer is initiated at the beginning of the next cycle of the device.

The first control output 19 of the channel is intended for transmitting a control signal to a computer informing about the readiness of the device to receive information after zeroing the information register 7 in asynchronous mode.

The device operates as follows.

L:

In the initial state, the current information is stored in the memory elements of the device — information registers 7: the recipient address and text (see Fig. 2, the installation inputs to the initial state are not shown conditionally). The first clock pulse arriving at the second clock input of the device to the second control input of the block of elements And 9, allows the reading of information from the information register 7 At the information input of the block of elements And 9 into the channel of those computers whose number is received from the first information input 11 channel, coincides with the addressee code / stored in the information register 7. In this case, the first control input of the block of the element And 9 receives the unit potential from the output of the comparison block 8. When reading information from the information register 7, it is set to Zero state (the reset circuits of register 7 are not shown conditionally). By the trailing edge of the first pulse from the second clock input 17, one is added to the contents of counter 1.

At the address output of counter 1, a current address code is generated, which, through the third information input 15, enters the second information input of the second comparison unit 2 of each channel.

If, when taking into account the next clock pulse, the counter overflows, then a single signal is displayed at the control output of the counter. The state of counter overflow indicates that the next cycle of operation of the device has begun in the device. The unit potential at the counter output to the second control input of the OR element 4 initiates the recording mode, i.e. transmitting information on the first information input 11 of the channel through the switches 5 and b in the information register 7 of the device.

The pulse received from the first clock input 16 of the device to the second control input of switches 5 and 6 transcribes the information in the information registers 7 from the second information output 13 of the computer channel via the second information input 12 of the channel of the subsequent computer through the switches 5 and 6 into the information registers 7.

The zero state of the information register 7, rewritten from the previous computer, leads to the appearance of a single signal at the output of the OR-NOT 10 element, i.e. a sign of an empty register, which is fed to the third input of the And 3 element, the first control input of the channel 19 and signals the readiness of the device to receive information from the computer to the channel.

The next information word (recipient address and text) arrives at the first information input of channel 11, the recipient address arrives at the first information input of comparison block 1. If it is greater than the current address received from the address output of the counter, then a control signal is generated at the output of comparison block 1 which, on the trailing edge of the next pulse received from the second clock input 17 of the device, through the AND 3 circuit and the OR element 4 allows recording information on the first information input 11 of the computer channel through the first th and second switches in the information register 7 of the device.

The next pulse from the second clock input 17 of the device allows reading information from the information register 7 in the computer channel if there was a comparison in block 8 of the destination code stored in the information register 7 with the code of the computer number received from the channel. If the comparison does not occur, then the information from the information register 7 enters the second information output 13 kpiel ne second

information input 12 of the subsequent computer, i.e. its census is ongoing.

By the Back Front of the pulse received from the second clock input 17, one is added to the counter content, if the counter is in a state of overfill, a zero state is established before the applied pulse (counter reset circuit

1 not shown).

The zero signal from the counter overflow output or the zero signals from the output of the second comparison unit and the OR-NOT 10 element prohibit the transmission of information from computer channels to information registers 7.

Subsequent (M - 1) pulses from the first clock input 1D of the device are supplied to the second control inputs of the switches 5 and 0 and the information about the registers 7 of the device is copied from the previous to the next.

Claims (1)

SUMMARY OF THE INVENTION A device for exchanging information. containing N channels, the first information input and output of which are the corresponding input and output of the device for connecting to the information output and input of the corresponding computer, the second information output of the 1st channel (i 1, N - 1) is connected to the second information input of the (I + 1) channel, the second information output of the N-ro channel is connected to the second information input of the first channel, the first clock inputs of the channels are connected to the first clock input of the device, each channel containing two switches and a comparison unit, the first information inputs of which are connected to the first information input of the channel, the information register, the first and second information inputs of which are connected respectively to the outputs of the first and second switches, the second information the ion and control inputs of which are connected respectively to the second information input and the first clock input of the channel, the block of elements And, the output of which is the first information output of the channel, the first and second outputs of the information register connected respectively to the second information input of the comparison unit and information input, block of elements And and form the second information output of the channel, which is applicable in that, in order to reduce the amount of equipment of the device and increase throughput, it is further introduced counter, the input of which is the second clock input of the device and connected to the synchronizing input channel, the first control the input connected to the counter overflow output, the third information input connected to the counter output address, and in each channel, a second comparison unit, the first and second information, is entered. the input inputs of which are connected to the pen .BUM and the third information inputs of the device, respectively, the block of elements OR-NO, the information input of which is connected to the outputs of the information register, and the output is the first control output of the device, the element And, the third input connected to the output of the block of elements OR-Н-Е, the second input is to the channel synchronizing input, and the first input is connected to the output of the second comparison unit, the OR element, the first and second control inputs of which are connected to the output of the AND element and the first the channel control input, respectively, wherein the output of the OR elements is connected to the second clock input, and in each channel, the first and second control inputs of the block of AND elements are connected respectively to the output of the comparison unit and the clock input of the channel. FIG. 4