SU1408453A1 - Device for magnetic recording of digital information - Google Patents

Abstract

The invention relates to the technique of magn. records The purpose of the invention is to increase the speed of the device. With a single output cell of the block 6 of the matrix memory, trigger 8 is reversed, and with zero it remains the same. The binary signal from the trigger 8 is recorded on the carrier by the apparatus 9 magn. records The device eliminates the regular repeatability of symbols of the same type, and also reduces the information delay in the device elements, since with the passage of information through the element I 7, the gain is achieved compared to the passage of information through the static trigger of the prototype. 2 Il.

Description

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The invention relates to a magnetic recording technique, namely, processing devices of digital information in a recording channel.

The purpose of the invention is to increase the speed of the device.

FIG. 1 shows a block diagram of the device; in fig. 2 - a schematic of one of the options for implementation.

The device contains a master oscillator 1, input bus 2, shifting registers 3-5, block 6 of matrix memory, element 7, trigger 8 and magnetic recording device 9 15.

The device works as follows.

The bit size and the initial state of the shift register 3 are determined by 20 the required counting number, for example, the number 2 needs 2 bits and the initial state 01, with the number 3-3 bits and the initial state 001, and the number 4-4 bits with the initial state - 25, 0011, with the number of 5-5 bits with the initial state, 00011, etc. The initial state of the trigger 8 and the shift registers 4 and 5 is zero. In block 6 of the matrix memory, bit combinations and binary signals are placed in rows and columns.

In the first cycle of operation, the digital information symbol from bus 2 is recorded in the first register bit, Ara 4, and the output symbol from the matrix memory block 6 is written in the first digit of the shift register 5, the shift register 3 is set to the first state the With a single Q output symbol of block 6 of the matrix memory, trigger state 8 is reversed, and with zero, it remains the same. The binary signal from the trigger 8 is recorded on the carrier by the magnetic recording apparatus 9.

On subsequent cycles, the device operation process is similar to the first cycle. When register 3, having passed all the states, returns to its original state, then the shift register 4 will record the word from the input information, and in register 5 it will appear as a recorded nonzero combination

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nagdi, formed by block 6 of the matrix memory in accordance with the memory program. The non-zero combination from the output of the matrix memory block 6 is fed through the trigger 8 to the magnetic recording apparatus 9.

In the proposed device, regular repetition of symbols of one type is eliminated faster, and the information delay in the elements of the device is also reduced, since when information passes through the element I, the gain is better than the information passed through the static trigger of the known device (under other equal conditions) . The proposed device also reduces the number of elements.

Claims (1)

Invention Formula A device for magnetic recording of digital information containing a master oscillator, a matrix memory block, a trigger whose output is connected to the input of a magnetic recording apparatus, and first and second shift registers whose outputs are connected to the row and column blocks of the matrix memory, respectively , the information and control inputs of the first of the shift registers are connected respectively to the input bus and the output of the master oscillator, and the information input of the second shift register is connected to the output of the matrix block memory, characterized in that, in order to improve speed, it is equipped with a third shift register and an AND element whose output is connected to the trigger input, the first input to the output of the matrix memory block, and the second input to the output of the master oscillator, connected to the control inputs of the second and third shift registers, the output of the latter is connected to inputs for polling the bits of the matrix memory block, while the output of the last bit of the third shift register is connected to the information input of the same register.