SU1339576A1 - Device for interfacing computer with common line - Google Patents

Abstract

The invention relates to computing and may be used in multi-machine computing systems for organizing machine-to-machine interaction. The aim of the invention is to reduce the hardware cost of the device by reducing the number of lines of the common mag J 23 and increasing the functional capabilities by initiating the intermachine exchange from any computer, the target containing the shift register , address selector 2, trigger 6 interrupts, group of receiving trunk amplifiers 9, first group of transmitting trunk amplifiers 10, four transmitting and three receiving trunk amplifiers entered node 4 arbitration, counter 5, t igger control 7, the first AND gate 8 and node 3 transmit audio confirmation signals consisting of a flip-flop 18 state highway ready trigger 19, the second AND gate 22, OR gate 20 and the second group of transmit trunk amplifiers. 1 hp f-ly, 4 ill. & (L oo OO with JV Gf5

Description

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The invention relates to computing and can be used in multi-machine computing systems for organizing machine-to-machine interaction.

The purpose of the invention is to reduce hardware costs by reducing the number of lines of the common highway and expanding the class of tasks to be performed by indicating the inter-exchange traffic on the common highway from computers.

Figure 1 presents the block diagram of the device (channel common highway) in figure 2 is a functional diagram of the node arbitration; Fig. 3 is a timing diagram explaining the procedure for establishing a connection via the main line between the computer that captures the line and the addressable computer; Fig. 4 is a timing diagram explaining the procedure for transmitting data through a common highway between a computer source of data and a computer receiver of data (addressed by a computer),

The device (Fig. 1) contains the shift register 1, the address selector 2, the confirmation signaling transmission node 3, the arbitration node 4, the counter 5,

The 25 formation through the amplifier 21 is outputted to the corresponding lines of the internal highway 26 by a signal at the input 27. After reading 1, the corresponding bit of the main lines

Trigger 6 interrupt; Trigger 7 control-from Amplifiers 21 computers - initiator of the exchange

writes the address word to the register 1 (Fig. 3). Recording to the register 1 from the highway 26 is performed according to the signal at the input 30 of the channel. The signal at input 40 when writing a word to the register in trigger 7 is recorded 1,. With this, since trigger 18 is recorded, the passage of clock pulses is unblocked from input 39 to output element I 8 and through amplifier 15 to line 35, from which sync pulses from channel - the source of data through the amplifier 12 is fed to the clock input of counter 5 and the shift input registers 1 of all channels connected to the common highway, C. The serial output of the register 1 channel that captured the highway (I at node 4 output) through the trunk amplifier 14 in line 34 on syn roimpulsam in line 39 transmitted bits that through amplifiers 11 and delay element 37 are applied to sequentially input register 1 of each channel. The shift by one bit in registers 1 of all channels is carried out on the falling edge of the sync pulse transmitted via line 35. When each bit is transmitted,

laziness, the first element And 8, a group of receiving trunk amplifiers 9, the first group of transmitting trunk amplifiers 10, receiving trunk amplifiers transmitting trunk amplifiers 14-17,

Node 3 contains a trigger 18. the state of the trunk, the trigger 19 readiness element OR-20, the second group of transmitting trunk amplifiers 21 and the second element And 22, the Selector 2 address contains triggers 23 and 24 and element And 25,

The device also has an internal trunk 26, control inputs 27-32, output 33, data lines 34-36, common trunk synchronization and busyness, delay elements 37 and 38, and synchronous input 39,

The node 4 of the arbitration contains the counter 40, the register 41, the triggers 42 and 43 and the generator 44 clock pulses.

Register 41 can be a hard connection of inputs 40 to the logic levels O and 1 so that the channel inputs are applied to the inputs 40 of the counter.

The device works as follows.

Before the start of work, the initial installation is performed by the signal at input 29, while on triggers 6 and 7 O is recorded. Before the start of computer exchange, the data initiator (data source) exposes the requirement of capturing the common highway to input 28. After the highway is captured at the node output 4, a signal is formed and on line 36 through amplifier 16 is set to a low level (busy signal). In the initial state with a free common line on the line

36 has a high potential. At a high level on line 36, the counter 5 is reset, triggers 24. and 19, and I is written to triggers 23 and 18,

After issuing the request for computer trunk capture, the initiator of the exchange through trunk amplifiers 21 analyzes the output of the node to establish the fact of the capture of the trunk. Information through the amplifier 21 leads to the corresponding lines of the internal highway 26 by a signal at input 27. After reading 1 from the corresponding trunk discharge

o Amplifiers 21 computers - initiator of the exchange

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writes the address word to the register 1 (Fig. 3). Recording to the register 1 from the highway 26 is performed according to the signal at the input 30 of the channel. The signal at input 40 when writing a word to the register in trigger 7 is recorded 1,. With this, since trigger 18 is recorded, the passage of clock pulses is unblocked from input 39 to output element I 8 and through amplifier 15 to line 35, from which sync pulses from channel - the source of data through the amplifier 12 is fed to the clock input of counter 5 and the shift input registers 1 of all channels connected to the common highway, C. The serial output of the register 1 channel that captured the highway (I at node 4 output) through the trunk amplifier 14 in line 34 on syn roimpulsam in line 39 transmitted bits that through amplifiers 11 and delay element 37 are applied to sequentially input register 1 of each channel. The shift by one bit in registers 1 of all channels is carried out on the falling edge of the sync pulse transmitted via line 35. When each bit is transmitted,

increasing the content of. counters of all channels. Thus, all address words bit by bit are transferred from source register 1 to registers 1 of all channels,

In the Kth word of the address word, recorded as a result of the exchange in registers 1 of all channels, is 1 when addressing the Kth machine. When establishing communication with one K-th machine in the address word, there is one unit in the K-th category. When establishing a connection with. several computers in the address word contains several units. In the case of a broadcast communication, in all bits, except for the bit corresponding to the computer source, units are recorded.

When the last bit of the address word is transmitted by the transfer signal of the counter 5, the following occurs: O is written into the triggers 8 and 7 (with a delay on the element 38); the formation of a pulse at the output of an element of AND 25 in the presence of for the K-th channel 1 in the K-th channel the discharge of the address word received in registers 1; write O to trigger 23

The signal from the output of the element And 25 in the address channel is recorded 1 in the triggers 19, 24 and 6.

In the case of a single state of the trigger 6 to the corresponding computer, exit machine 33 exits the requirement of machine-to-machine exchange. In the case of the single state of the trigger-19 (installed in the addressable -CAM) through the amplifier 17, the low level is set on line 34. After the transfer of the address word on line 34 before the issuance of the specified signal was high. A signal (low level) to line 34 is provided from all addressable channels (on the basis of mounting OR) and is perceived as a signal of a lack of a communication channel with addressable machines. The peculiarity of the broadcast and group communication is the need to implement inter-exchange communication (transmission of information words) only after the establishment of a communication channel with all addressed machines,

After receiving a machine-to-machine exchange request, each addressable computer zeroes trigger 6 with a signal at input 32. After preparing for the inter-machine exchange (after processing an interrupt), the addressable computer zeroing trigger 19 of its device, reading through

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amplifiers 10 on line 26 register contents 1.

After resetting the flip-flop 19, the K-th device removes the unavailability signal from line 34 through amplifier 17, the total unavailability signal from line 34 is removed only when all addressable computers that remove their unavailability signals from line 34 are swapped the trigger 19 of their channel. In the zero state of the trigger 7, set after the transfer of the address word on the trailing edge, the difference from a low level to a high signal on the line 34 triggers 18 all channels are set to one state,

The computer - the initiator of the exchange (source) after transmitting the address word and all addressable machines after preparing to receive data to identify the establishment of a communication channel by the machine with all addressable machines interrogate trigger 18 via trunk amplifiers 21, After reading the single state trigger 18 and zero trigger 7 of the computer — the source enters (FIG. 4) into register 1 the second-most transmitted word from the internal highway 26. When a word is written into register 1, signal 1 at input 30 records 1 in trigger 7 and at 1 SRI the latch 18 via the AND gate 8 extending to clock input 39,

The clock pulses from the output of the element I 8 through the trunk amplifier 15 are fed to line 35 and through the trunk amplifiers 12 arrive at the shift inputs of the registers the 1st counting inputs of the counters 5 of all channels. For each clock pulse on line 35, the next bit transmitted from the serial output of the register 1 of the source device is transmitted, through line 34 to registers 1 of all channels, the output of the transmitted bit to line 34 and reception of this bit is carried out through trunk amplifiers 14 and 11. , serial bit by bit, transfer of the next word from source register 1 via line 34 to registers 1,

When transmitting through the line 35 of the last bit of the word, at the outputs of the transfer of the readers of 5 all channels, an impulse is formed, through which

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triggers 7 reset (reset register 1) and setting a single state of the triggers to the address of the first computers, the trigger 24 of which contains 1. When writing 1 to the trigger 19, the addressable computer through the trunk amplifiers 21 and the internal highway 26 receives information about the readiness in the register I of the next word.

In the case of a single state of flip-flop 19, a low level is output to line 34 via the trunk amplifier 17 (in the initial state, after the transmission of the next word on the line 34 there was a high level), i.e. set the signal of unavailability of the addressed computer to receive the subsequent word. When read through the internal line 26 through the amplifiers 10 of the contents of the Receiver 1, the signal 31 is triggered by the trigger 19 and the signal of non-restraint is received from the corresponding channel to receive the next word. The total unavailability signal (low level) from the addressable devices (channels) is removed only after reading the contents of registers 1 by all addressable computers.. On a drop on line 34, from a low level to high, with a zero state of Triggers 7, triggers 18 are written 1 (write to a trigger 18 happens ta

the same as when establishing a connection) When the state is zero, trigger 7 and single state trigger 18 computer - source to bring: the next word. Through internal highway 26 to register 1 by signal 30, while recording 1 to trigger 7 and unlocking PW5: sync pulses from the input 39 for the transfer of the next word, which is transmitted through a common line in accordance with the described process.

After the last word of the computer package is transmitted, the source frees the common line by sending a signal to input 29, the common line is released, and a high level is installed on line 36, after which the line can be captured for machine-to-computer exchange with other computers.

Requests for the capture of a common highway (FIG. 2) are triggered by triggers 43 by a signal at input 28, When a common highway is busy on line 36 and

respectively, an input signal is present at input 38. When the signal is put on line 36 at the inlet, 1 installation of the counters 40 of all channels, a signal is sent by which the counters 40 record the codes from the outputs of the corresponding 1X registers 41. At the same time, the accumulation of the contents of the counters 40 is blocked. The signal, the installation of the counters 40 is held for the entire period of the common highway. Thus, by the time the busy signal was removed from line 36, the counters 40 of all channels were entered into

5 channel numbers. When the busy signal is removed from line 36, the operation of the counters 40 in the counting mode is unlocked. Since, after the main line is combined, the numbers of channels are brought into the counters 40, the transfer signals of the counters 40 of different channels are formed at different points in time (different ticks). If the K-th channel received the requirement to capture the highway (1 in the trigger

5 43), the transfer signal from the 40 K-th channel counter records I to a trigger 42, a signal is generated at the output of node 4, and a busy signal (low level) is set via line 36 to blockings through amplifiers 13 the operation of the counters 40 in the counting mode and setting the mode of their installation. In order to release a common computer mainline, the data transfer is set to a signal 29, through which O is triggered at the flip-flops 42 and 43, and the busy signal 36 is picked up through amplifier 16,

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Claims (2)

1. A device for interfacing a common-line computer containing a group of receiving trunk amplifiers whose inputs are connected to the outputs of transmitting main amplifiers of the first group and form the input-output of the device for connecting to the computer information buses, shift register, interrupt trigger, address simulator, the inputs of the first, second and third receivers {s of the main amplifiers are connected respectively to the outputs of the first, second and third transmitting main amplifiers form the inputs-outputs of the device li ne to the data lines and pginam sinhror ization and coupled to71339576 ti common highway, the information flow of the parallel motor register code is connected to the outputs of the receiving no but no ne i ne by ne pe s sch de up no no m no but no s d no i u ma ma gr el ma t st with that o ro si ro ro but no less so until no trunk amplifiers of the group, the output of the fourth transmitting trunk amplifier is connected to the input of the third receiving trunk amplifier, characterized in that, in order to reduce the hardware costs of the device, a counter, address selector, control trigger, AND element, arbitration node, two elements are entered into it delays and a confirmation signaling node consisting of a trunk state trigger, a readiness trigger of a group of transmitting trunk amplifiers, an OR element and an AND element, with the outputs of the main The amplifiers of the confirmation signaling node group are a group of device outputs for connection to computer information buses, and a group of information inputs are connected to the output of the arbitration node, the inverse output of the control trigger, and the outputs of the state trigger and readiness trigger, the first output of the address selector is connected to the setup inputs of the ready trigger and the interrupt trigger, and the second output to the readiness trigger information input, the output, the sync input and the reset input of which are connected respectively to the input of the fourth transmitting trunk amplifier and the outputs of the counter and the OR element, the first input connected to the output of the third receiving trunk amplifier, the resolution input of the address selector and arbitration node, the reset input of the counter and the installation input of the trunk state trigger, the output of the information main input, synchronous input and reset input which are connected respectively with the first input of the first element AND, the inverse output of the control trigger, the output of the element AND of the node of the confirmation signal transmission and the output m counter, a clock input coupled to an output of the main amplifier receiving and shifting input serial shift register the output of which is connected to the input of the first hermatsionnym yn transmitting main amplifier, a control input connected to the input of the second amplifier and the transmission trunk vyho8 0 five 0 five 0 five 0 five element I, the output nepBCj o of the receiving trunk amplifier is connected to the first input of the AND element of the confirmation signaling node and through, the first delay element to the input of the shift register code, the output group of which is connected to the information inputs of the transmitting trunk amplifiers of the first group and the address selector, sync input connected to the output of the counter and through the second delay element to the reset input of the control trigger, the inverse and direct outputs of which are connected respectively to the second input The element D and A elements and the signal transmission node of the confirmation signal, the third input of the arbitration node connected to the output and the input of the third transmitting trunk amplifier, synchronize the shift register connected to the control trigger trigger input and is the device input for connecting the computer information tracking signal output, controlling the inputs of the main transmitting amplifiers of the first group, connected to the second input of the OR element, and the control inputs of the main transmitting amplifiers of the second group, The device input for connecting to the computer polling output, the fourth input of the AND element and the input of the arbitration node are respectively the device input for connecting to the clock outputs and the signal input signal of the computer trunk capture of the device, the reset input and the interrupt trigger output are respectively input and the device output for connecting to the interrupt signal receiving output and the computer interrupt request input, the inputs for setting the initial state of the interrupt triggers, the control and the arbitration node are input devices for connecting to the output of the initial installation of a computer. 2. The device according to claim 1, of which is that the arbitration node contains two triggers, a register, a counter and a clock generator, the clock, information inputs and the write resolution enable input of the counter are connected respectively to the outputs of the clock generator, register and input the node enable, the information input and the synchronous input of the dimensional trigger are connected respectively to the outputs of the first trigger and the counter, and the output and the reset input are respectively connected to the output knot I by the entrance plchp.iinpp yc. i; .1iogch and node, input s.bros and ustchisch ocnr. Pu.od of the second triangle connects the corresponding CTBejfHO with the input of the zanros and the input of the initial installation of the node. 2 P PG  Oh or 1 OECH Pereter "L 31p 1 P PL f x-hgh-71 Compiled by V. Vertlib Editor A.Vorovich Tehred M.Didyk Proofreader S. Order 4224/40 Circulation 672 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4