JP2637276B2 - Tracer - Google Patents

Description

Detailed Description of the Invention [Table of Contents] Overview Industrial application field Conventional technology (Fig. 3) Problems to be solved by the invention Means for solving the problem (Fig. 1) FIG. 2) Effects of the Invention [Summary] Regarding a tracer that reads trace data through a scan loop, scan data captured in response to a set pulse in a time series is scanned by a set pulse next to the set pulse. The trace data input to the trace data input is set when the enable signal is supplied from the enable signal output circuit with the purpose of setting the trace data in the holding circuit and scanning out the trace data via a single pin. In response to one set pulse on the time series applied to the pulse input, the trace data holding circuit is set in a bit parallel manner. Supplying the trace data to the scan data holding circuit. The scan data holding circuit is configured to apply the 1
Trace data supplied in response to a set pulse next to one set pulse is set in the scan data holding circuit in a bit-parallel manner, and scan-out is performed.

[Industrial applications]

The present invention relates to a tracer that reads out trace data via a scan loop.

2. Description of the Related Art Some information processing apparatuses are configured to be able to read out trace data set in a trace register in the apparatus and use the read out trace data. Such a device configuration is adopted from the viewpoint of improving the reliability of the device. Since the trace register in such a device configuration is formed on the LSI, the number of output pins required for reading the trace data is different from that of the other devices.
It becomes a problem in the LSI configuration in relation to the number of pins used for the LSI equipped functions.

[Conventional technology]

FIG. 3 shows an example of a conventional circuit configuration satisfying the above-mentioned requirements. In this figure, trace register 32,
The trace register 34 and the trace register 36 store the data bus 30 when the data set clock pulse is applied thereto, provided that the select signal is supplied.
This is to set the data that is transferred via.
The select signal is also supplied to a multiplexer 38, a multiplexer 40, and a multiplexer 42. The data bits of the trace register (three bits for convenience of explanation) output from the corresponding multiplexer in response to the select signal are output from output pins 60, 62, and 64.

[Problems to be solved by the invention]

The trace data set in the trace registers 32 to 36 are multiplexers 38, 40, and 42 corresponding to each bit of the trace register by a select signal that causes the trace data to be set in the trace register.
Then, the data is output to output pins 60, 62, and 64 provided corresponding to the respective bits of the trace register, thereby reading the data. Therefore, the number of output pins required to read the trace data set in the trace register is equal to the number of bit positions of the trace register. Spending such a number of pins solely on reading the trace data limits the functions that can be implemented in the LSI. In many cases, it is necessary to give more importance to other functions that are subject to the above-mentioned restrictions than to the trace data reading function. Therefore, the above-mentioned restrictions cause problems in the LSI configuration.

The present invention has been made in view of such a technical problem, and sets trace data captured in response to a set pulse in a time series in a scan data holding circuit with a set pulse next to the set pulse. And to provide a tracer whose trace data is scanned out via a single pin.

[Means for solving the problem]

FIG. 1 is a block diagram showing the principle of the first to third aspects of the present invention.

In (A) of FIG. 1 (part 1), reference numeral 2 denotes a trace data holding circuit, which has a set pulse input, an enable signal input, and a trace data input, and a set pulse to the set pulse input and the enable signal. The trace data to the trace data input is set in response to an enable signal to the signal input.

An enable signal output circuit 3 has an output connected to the enable signal input of the trace data holding circuit 2 and outputs an enable signal to the trace data holding circuit 2.

A scan data holding circuit 4 having a set pulse input connected to the set pulse input of the trace data holding circuit 2 and a data input connected to the output of the trace data holding circuit 2; The trace data to the data input is set in a bit-parallel manner in response to the supply of the set pulse following the set pulse in which the trace data is set to the circuit 2 to the set pulse input, and is set in response to the scan clock pulse. The trace data is scanned out in a bit serial manner.

The invention according to claim 1 includes the trace data holding circuit 2, the enable signal output circuit 3, and the scan data holding circuit 4.

In FIG. 1 (part 1) (B), 2A has a set pulse input, a trace data identification signal input, and a trace data input, and the set pulse input to the set pulse and the trace data identification signal input. In response to the trace data identification signal, the trace data to the trace data input is set in a trace data holding circuit specified by the trace data identification signal.

A selection circuit 5 has a trace data input connected to each output of the plurality of trace data holding circuits 2A, and a selection signal input, and is connected to the selection signal input in the plurality of trace data holding circuits 2A. The output data of the trace data holding circuit corresponding to the selection signal is output.

Numeral 7 denotes a signal generation circuit which outputs a scan suppression signal input, an output connected to each trace data identification signal input of the plurality of trace data holding circuits 2A, and an output connected to a selection signal input of the selection circuit 5. A trace data identification signal in a predetermined order to each trace data identification signal input of the plurality of trace data holding circuits 2A in response to supply of a scan inhibition signal to the scan inhibition signal input; and A selection signal for selecting the trace data of the trace data holding circuit corresponding to the signal is output to the selection circuit 5 and a selection signal input.

4A is a scan data holding circuit having a set pulse input connected to a set pulse input of the trace data holding circuit 2A, and a trace data input connected to an output of the selection circuit 5;
The trace data to the data input is set in bit parallel in response to the supply of the set pulse next to the set pulse in which the trace data is set to the set pulse input, and the trace set in response to the scan clock pulse The data is scanned out in a bit serial manner.

The invention according to claim 2 includes a plurality of trace data holding circuits 2A, a selection circuit 5, a signal generation circuit 7, and a scan data holding circuit 4A.

In (C) of FIG. 1 (part 2), a scan clock pulse output circuit 8 is provided in the tracer of the second aspect. The scan clock pulse output circuit 8 has a scan inhibition signal input and a scan clock pulse output, and responds to the signal indicating the cancellation of scan inhibition supplied to the scan inhibition input to output the scan clock pulse to the scan clock pulse output. Is output.

The scan data holding circuit 4A is provided with a scan-in input, and responds to a scan clock pulse output from the scan clock pulse output circuit 8 when a signal indicating cancellation of scan inhibition is supplied to a scan inhibition signal input. The scan data holding circuit 4A is configured to output the trace data identification signal information used for outputting any one trace data identification signal different from the predetermined order, which is supplied to the scan-in input. Configure as 4B.

And stopping the output of the trace data identification signal in a predetermined order and a selection signal corresponding thereto in response to a signal indicating the scan inhibition release supplied to the scan inhibition signal input; The signal output circuit 7 is configured as a signal output circuit 7A so as to output a selection signal for selecting output data of the trace data holding circuit specified by the information.

Therefore, the invention according to claim 3 includes a plurality of trace data holding circuits 2A, a selection circuit 5, a signal generation circuit 7A, a scan data holding circuit 4B, and a scan clock pulse output circuit 8.

(Operation)

In the invention described in claim 1, the trace data holding circuit 2 applies the trace data input to the trace data input to the set pulse input in a state where the enable signal is supplied from the enable signal output circuit 3. The bits are set in parallel in response to one set pulse on the time series.

The trace data set in the trace data holding circuit 2 is supplied to the data input of the scan data holding circuit 4 and the next set of the one set pulse applied to the set pulse input of the scan data holding circuit 4 In response to the pulse, the trace data from the trace data holding circuit is set in the scan data holding circuit 4 in a bit-parallel manner.

The trace data set in the scan data holding circuit 4 is scanned out of the scan data holding circuit 4 in a bit serial manner in response to a scan pulse.

Therefore, the trace data is fetched into the trace data holding circuit 2 in a bit-parallel manner by one set pulse on a time series, and is responded by the next set pulse to the scan data holding circuit 4 in a bit-parallel manner. It can be set and scanned out bit-serial from a single output or output pin in response to a scan pulse.

According to the second aspect of the present invention, the trace data identification signal from the signal output circuit 7 is supplied to each trace data identification signal input of the plurality of trace data holding circuits 2A, and is specified by the trace data identification signal. Causing the trace data holding circuit to set the trace data input to the trace data input in a bit-parallel manner, and that a selection signal from the signal output circuit 7 is supplied to a selection input of a selection circuit 5 so that the selection signal The operation is the same as that of the first embodiment except that the trace data of the designated trace data holding circuit is set in the scan data holding circuit 4A in a bit parallel manner.

Therefore, predetermined trace data in the order of the trace data set in the plurality of trace data holding circuits 2A is chronologically fetched into the trace data holding circuit 2 by one set pulse in the form of one set pulse. In response to the next set pulse, the data is set in the scan data holding circuit 4 in a bit-parallel manner, and in response to the scan pulse, a single output or an output pin can be scanned in a bit serial manner.

According to a third aspect of the present invention, the signal output circuit 7 in the second aspect of the present invention stops outputting the trace data identification signal and the selection signal in response to a signal indicating cancellation of scan suppression. Of the plurality of trace data holding circuits 2A, a selection signal for selecting the trace data of the trace data holding circuit specified by the trace data identification signal information from the scan data holding circuit B is output, and the selection signal is output The selected trace data is supplied to the selection circuit 5 and the selected trace data is supplied to the scan data holding circuit 4B, and the trace data of the trace data holding circuit specified by the selection signal is sent to the scan data holding circuit.
Let 4B be set bit-parallel.

Thereby, of the trace data set in the plurality of trace data holding circuits, the trace data specified by the trace data identification signal information input from the scan-in input is scanned out bit-serial from the scan data holding circuit. Can be done.

〔Example〕

FIG. 2 shows an embodiment of the invention according to claims 1 to 3. In this figure, the same components as those in FIG. 3 are denoted by the same reference numerals, and description thereof will be omitted. In this embodiment, the selective output of the data of the trace registers 32 to 36 to the scan register 44 is performed by the multiplexer 41. The trace data select signal to the multiplexer 41 is generated at the output of the decoder 48. The output of the counter 46 is supplied to the input of the decoder 48. The counter 46
Trace data on the data bus 30 is transferred to the trace register 32
First identification data indicating which of the trace registers 36 to 36 is to be set, and which of the trace registers among the trace registers 32 to 36 is to be read. Is output. The first identification data is output in response to a count signal supplied to the count input of the counter 46 via the count signal line 51. The second identification data is output by shifting in a trace register number supplied to a set input of the counter 46 through a scan loop described below in response to a scan clock pulse supplied to a scan clock input. . The trace register number is input from the scan-in to the scan register 44, is set in the scan register 44 by a scan clock pulse, and is output from the scan register 44 as a scan loop signal by the scan clock pulse.

Then, the count value of the counter 46 (first identification data) or the trace register number (second identification data)
Is supplied to one input of the multiplexer 56 in a bit serial manner in response to the scan clock pulse, thereby completing a scan loop to the scan-out output pin 58. The AND circuit 50 that generates a scan clock pulse is supplied with a scan inhibition signal and a scan clock pulse that have passed through the inverter 49. The scan inhibit signal is also supplied to multiplexer 56 as its switching signal.

In FIG. 1 and FIG.
36 corresponds to the first trace data holding circuit 2, 2A,
The counter 46 and the decoder 48 correspond to the enable signal output circuit 3 in FIG. The scan register 44 corresponds to the scan data holding circuits 4, 4A and 4B in FIG. 1, and the multiplexer 41 corresponds to the selection circuit 5 in FIG. counter
46, a decoder 48, an inverter 49, an AND circuit 50, and a count signal line 51 correspond to the signal output circuits 7 and 7A in FIG.
The inverter 49 and the AND circuit 50 correspond to the scan clock pulse output circuit 8 in FIG.

Next, the operation of the invention having the above-described configuration will be described below.

First, how the trace data on the data bus 30 is set to which of the trace registers 32 to 36 will be described. At that time, the scan suppression signal is set to “1”.

Along with the transfer of the trace register onto the data bus 30, a count signal is provided to the count input of the counter 46 to generate a trace register identification count for which one wishes to set trace data on the data bus 30. The count value is decoded by the decoder 48, the trace register enable signal is supplied to the trace registers 32 to 36, and the trace data select signal is supplied to the multiplexer 41. Therefore, the trace data on the data bus 30 is set in the trace register specified by the trace data enable signal.

When reading the trace data set in the trace register as described above, the scan suppression signal is set to "0". As a result, the scan clock pulse passes through the AND circuit 50 and the scan register 44,
And supplied to the counter 46. Its scan register 44
The trace register number from scan-in is set in bit serial in response to the scan clock pulse.
Then, the trace register number read from the scan register 44 in response to the scan clock pulse is set in a bit serial manner in the counter 46 in the scan loop and set there. When this scan-in operation is performed, the counter 46 is not supplied with a count signal.

At the end of the operation of setting the trace register number in the counter 46, the scan suppression signal is switched to "1" because it has been "0" until then. Thus, the shift operation of the scan-in signal in the scan loop stops. As described above, the trace register number set in the counter 46 remains set therein, and the trace register number of the counter 46 is supplied to the multiplexer 41 as a trace data select signal via the decoder 48. The signal is supplied to the trace registers 32 to 36 as a trace register enable signal. Therefore, the trace data already set in the trace register is supplied to the data bit set input of the scan register 44 in a bit-parallel manner via the multiplexer 41 by the trace data select signal, and in response to the next data set clock pulse. It is set in the scan register 44. At this time, the trace data (for example, an address signal) from the data bus 30 can be set by the trace register enable signal of the trace registers 32 to 36 in response to the next data set clock pulse. Is set in the trace register.

In order to read out the trace data set in the scan register 44 in this manner, the scan inhibit signal is set to “0”, the AND circuit 50 outputs a scan clock pulse, and the trace data set in the scan register 44 is read. Counter 46 and multiplexer 56
To read out the trace data.

In the above embodiment, the case where the generation control system of the trace register enable signal and the trace data select signal is configured in the scan loop has been described. ,
Since the required number of trace data is set to the scan register by the bit parallel type and the required number is reduced by the shift out by the bit serial type, the generation control system of the trace register enable signal and the trace data select signal as in the above-described embodiment. There is no necessity to configure in the scan loop.

〔The invention's effect〕

As described above, according to the first aspect of the present invention, the trace data is fetched into the trace data holding circuit by one set pulse in a time series in a bit parallel manner, and a response is made by a set pulse next to the one set pulse. By setting the scan data holding circuit in a bit-parallel manner, a single output or output pin can be scanned in a bit-serial manner in response to a scan pulse.

According to the second aspect of the present invention, the trace data of the trace data holding circuits in a predetermined order among the plurality of trace data holding circuits can be scanned out as in the first aspect of the present invention.

According to the third aspect of the present invention, the scan-out of the trace data according to the second aspect of the present invention can be specified by the trace data identification signal information input from the scan-in input.

[Brief description of the drawings]

FIG. 1 (part 1) is a principle block diagram of the invention according to claims 1 and 2, FIG. 1 (part 2) is a principle block diagram of the invention according to claim 3, and FIG. FIG. 3 is a diagram showing an embodiment of the invention according to claim 3, and FIG. 3 is a diagram showing a conventional trace data reading method. 1 and 2, reference numerals 2 and 2A denote a trace data holding circuit (trace register 32).
To 36), 3 is an enable signal output circuit (counter 46, decoder 4
8), 4, 4A and 4B are scan data holding circuits (scan registers 44), 5 is a selection circuit (multiplexer 41), 7, 7A are signal output circuits (counter 46, decoder 48, count signal line 51), 8 is Scan clock pulse output circuit (Inverter 49,
AND circuit 50).

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Koichi Odawara 1015 Uedanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture Inside Fujitsu Limited (72) Inventor Kenji Hoshi 1015 Kamikodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Fujitsu Limited ( 56) References JP-A-1-206441 (JP, A) JP-A-1-199243 (JP, A)

Claims (3)

(57) [Claims] And a trace input to said trace data input in response to a set pulse to said set pulse input and an enable signal to said enable signal input. A trace data holding circuit for setting data, an enable signal output circuit having an output connected to an enable signal input of the trace data holding circuit, and outputting an enable signal to the trace data holding circuit; A set pulse input connected to a set pulse input of the circuit, and a data input connected to an output of the trace data holding circuit, and a set pulse next to the set pulse in which the trace data is set in the trace data holding circuit. In response to supplying to the set pulse input Trace data into serial data input is set to bit parallel, characterized in that the trace data set in response provided a scan data holding circuit for scanning out bits serially into the scan clock pulse tracer. 2. The apparatus according to claim 1, further comprising a set pulse input, a trace data identification signal input, and a trace data input, wherein said set pulse input and said trace data identification signal are input in response to a trace data identification signal applied to said trace data identification signal input. A plurality of trace data holding circuits for setting trace data to the trace data input to a trace data holding circuit specified by the trace data identification signal; a trace data input connected to each output of the plurality of trace data holding circuits; And a selection circuit having a selection signal input, and among the plurality of trace data holding circuits, a selection circuit for outputting output data of a trace data holding circuit corresponding to a selection signal to the selection signal input; and a scan suppression signal input; and Each of the trace data identification signals of the plurality of trace data holding circuits is Connected to a selection signal input of the selection circuit, and each trace data identification of the plurality of trace data holding circuits in response to supply of a scan inhibition signal to the scan inhibition signal input. A signal generation circuit that outputs a trace data identification signal in a predetermined order to a signal input, and a selection signal for selecting trace data of a trace data holding circuit corresponding to the trace data identification signal to a selection signal input of the selection circuit; A set pulse input connected to a set pulse input of the trace data holding circuit, and a trace data input connected to an output of the selection circuit, and a set pulse input to the trace data holding circuit next to the set pulse that sets the trace data. Trace data to the data input in response to the supply of a set pulse to the set pulse input Set the data in bit parallel, characterized in that the trace data set in response to the scan clock pulses are provided with scan data holding circuit for scanning out bits serially tracer. 3. The tracer according to claim 2, further comprising a scan suppression signal input and a scan clock pulse output, wherein said scan clock pulse output is provided in response to a signal supplied to said scan suppression input indicating cancellation of scan suppression. A scan clock pulse output circuit that outputs a scan clock pulse, and a scan-in input is provided in the scan data holding circuit, and the scan clock pulse output circuit is provided when a signal indicating cancellation of scan inhibition is supplied to a scan inhibition signal input. Trace data identification signal information used for outputting any one trace data identification signal different from the predetermined order, which is supplied to the scan-in input in response to a scan clock pulse output from a circuit, can be output. Scan data holding circuit A data holding circuit configured to stop the output of the trace data identification signal in the predetermined order and the selection signal corresponding thereto in response to the signal indicating the cancellation of the scan inhibition supplied to the input of the scan inhibition signal, and A tracer, wherein the signal output circuit is configured as a signal output circuit so as to output a selection signal for selecting output data of a trace data holding circuit specified by the trace data identification signal information.